1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/pm_runtime.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <sound/sof.h> 22 #include "../ops.h" 23 #include "../sof-audio.h" 24 #include "hda.h" 25 26 #define HDA_LTRP_GB_VALUE_US 95 27 28 static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream) 29 { 30 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 31 return "Playback"; 32 else 33 return "Capture"; 34 } 35 36 static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream) 37 { 38 struct snd_soc_pcm_runtime *rtd; 39 40 if (hstream->substream) 41 rtd = asoc_substream_to_rtd(hstream->substream); 42 else if (hstream->cstream) 43 rtd = hstream->cstream->private_data; 44 else 45 /* Non audio DMA user, like dma-trace */ 46 return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)", 47 hda_hstream_direction_str(hstream), 48 hstream->stream_tag); 49 50 return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)", 51 rtd->dai_link->name, hda_hstream_direction_str(hstream), 52 hstream->stream_tag); 53 } 54 55 /* 56 * set up one of BDL entries for a stream 57 */ 58 static int hda_setup_bdle(struct snd_sof_dev *sdev, 59 struct snd_dma_buffer *dmab, 60 struct hdac_stream *hstream, 61 struct sof_intel_dsp_bdl **bdlp, 62 int offset, int size, int ioc) 63 { 64 struct hdac_bus *bus = sof_to_bus(sdev); 65 struct sof_intel_dsp_bdl *bdl = *bdlp; 66 67 while (size > 0) { 68 dma_addr_t addr; 69 int chunk; 70 71 if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) { 72 dev_err(sdev->dev, "error: stream frags exceeded\n"); 73 return -EINVAL; 74 } 75 76 addr = snd_sgbuf_get_addr(dmab, offset); 77 /* program BDL addr */ 78 bdl->addr_l = cpu_to_le32(lower_32_bits(addr)); 79 bdl->addr_h = cpu_to_le32(upper_32_bits(addr)); 80 /* program BDL size */ 81 chunk = snd_sgbuf_get_chunk_size(dmab, offset, size); 82 /* one BDLE should not cross 4K boundary */ 83 if (bus->align_bdle_4k) { 84 u32 remain = 0x1000 - (offset & 0xfff); 85 86 if (chunk > remain) 87 chunk = remain; 88 } 89 bdl->size = cpu_to_le32(chunk); 90 /* only program IOC when the whole segment is processed */ 91 size -= chunk; 92 bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01); 93 bdl++; 94 hstream->frags++; 95 offset += chunk; 96 97 dev_vdbg(sdev->dev, "bdl, frags:%d, chunk size:0x%x;\n", 98 hstream->frags, chunk); 99 } 100 101 *bdlp = bdl; 102 return offset; 103 } 104 105 /* 106 * set up Buffer Descriptor List (BDL) for host memory transfer 107 * BDL describes the location of the individual buffers and is little endian. 108 */ 109 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 110 struct snd_dma_buffer *dmab, 111 struct hdac_stream *hstream) 112 { 113 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 114 struct sof_intel_dsp_bdl *bdl; 115 int i, offset, period_bytes, periods; 116 int remain, ioc; 117 118 period_bytes = hstream->period_bytes; 119 dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes); 120 if (!period_bytes) 121 period_bytes = hstream->bufsize; 122 123 periods = hstream->bufsize / period_bytes; 124 125 dev_dbg(sdev->dev, "periods:%d\n", periods); 126 127 remain = hstream->bufsize % period_bytes; 128 if (remain) 129 periods++; 130 131 /* program the initial BDL entries */ 132 bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area; 133 offset = 0; 134 hstream->frags = 0; 135 136 /* 137 * set IOC if don't use position IPC 138 * and period_wakeup needed. 139 */ 140 ioc = hda->no_ipc_position ? 141 !hstream->no_period_wakeup : 0; 142 143 for (i = 0; i < periods; i++) { 144 if (i == (periods - 1) && remain) 145 /* set the last small entry */ 146 offset = hda_setup_bdle(sdev, dmab, 147 hstream, &bdl, offset, 148 remain, 0); 149 else 150 offset = hda_setup_bdle(sdev, dmab, 151 hstream, &bdl, offset, 152 period_bytes, ioc); 153 } 154 155 return offset; 156 } 157 158 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 159 struct hdac_ext_stream *hext_stream, 160 int enable, u32 size) 161 { 162 struct hdac_stream *hstream = &hext_stream->hstream; 163 u32 mask; 164 165 if (!sdev->bar[HDA_DSP_SPIB_BAR]) { 166 dev_err(sdev->dev, "error: address of spib capability is NULL\n"); 167 return -EINVAL; 168 } 169 170 mask = (1 << hstream->index); 171 172 /* enable/disable SPIB for the stream */ 173 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR, 174 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask, 175 enable << hstream->index); 176 177 /* set the SPIB value */ 178 sof_io_write(sdev, hext_stream->spib_addr, size); 179 180 return 0; 181 } 182 183 /* get next unused stream */ 184 struct hdac_ext_stream * 185 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags) 186 { 187 struct hdac_bus *bus = sof_to_bus(sdev); 188 struct sof_intel_hda_stream *hda_stream; 189 struct hdac_ext_stream *hext_stream = NULL; 190 struct hdac_stream *s; 191 192 spin_lock_irq(&bus->reg_lock); 193 194 /* get an unused stream */ 195 list_for_each_entry(s, &bus->stream_list, list) { 196 if (s->direction == direction && !s->opened) { 197 hext_stream = stream_to_hdac_ext_stream(s); 198 hda_stream = container_of(hext_stream, 199 struct sof_intel_hda_stream, 200 hext_stream); 201 /* check if the host DMA channel is reserved */ 202 if (hda_stream->host_reserved) 203 continue; 204 205 s->opened = true; 206 break; 207 } 208 } 209 210 spin_unlock_irq(&bus->reg_lock); 211 212 /* stream found ? */ 213 if (!hext_stream) { 214 dev_err(sdev->dev, "error: no free %s streams\n", 215 direction == SNDRV_PCM_STREAM_PLAYBACK ? 216 "playback" : "capture"); 217 return hext_stream; 218 } 219 220 hda_stream->flags = flags; 221 222 /* 223 * Prevent DMI Link L1 entry for streams that don't support it. 224 * Workaround to address a known issue with host DMA that results 225 * in xruns during pause/release in capture scenarios. 226 */ 227 if (!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) 228 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 229 HDA_VS_INTEL_EM2, 230 HDA_VS_INTEL_EM2_L1SEN, 0); 231 232 return hext_stream; 233 } 234 235 /* free a stream */ 236 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag) 237 { 238 struct hdac_bus *bus = sof_to_bus(sdev); 239 struct sof_intel_hda_stream *hda_stream; 240 struct hdac_ext_stream *hext_stream; 241 struct hdac_stream *s; 242 bool dmi_l1_enable = true; 243 bool found = false; 244 245 spin_lock_irq(&bus->reg_lock); 246 247 /* 248 * close stream matching the stream tag and check if there are any open streams 249 * that are DMI L1 incompatible. 250 */ 251 list_for_each_entry(s, &bus->stream_list, list) { 252 hext_stream = stream_to_hdac_ext_stream(s); 253 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream); 254 255 if (!s->opened) 256 continue; 257 258 if (s->direction == direction && s->stream_tag == stream_tag) { 259 s->opened = false; 260 found = true; 261 } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 262 dmi_l1_enable = false; 263 } 264 } 265 266 spin_unlock_irq(&bus->reg_lock); 267 268 /* Enable DMI L1 if permitted */ 269 if (dmi_l1_enable) 270 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 271 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN); 272 273 if (!found) { 274 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n", 275 __func__, stream_tag); 276 return -ENODEV; 277 } 278 279 return 0; 280 } 281 282 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream) 283 { 284 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 285 int timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 286 u32 val; 287 288 /* enter stream reset */ 289 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 290 SOF_STREAM_SD_OFFSET_CRST); 291 do { 292 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 293 if (val & SOF_STREAM_SD_OFFSET_CRST) 294 break; 295 } while (--timeout); 296 if (timeout == 0) { 297 dev_err(sdev->dev, "timeout waiting for stream reset\n"); 298 return -ETIMEDOUT; 299 } 300 301 timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 302 303 /* exit stream reset and wait to read a zero before reading any other register */ 304 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0); 305 306 /* wait for hardware to report that stream is out of reset */ 307 udelay(3); 308 do { 309 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 310 if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0) 311 break; 312 } while (--timeout); 313 if (timeout == 0) { 314 dev_err(sdev->dev, "timeout waiting for stream to exit reset\n"); 315 return -ETIMEDOUT; 316 } 317 318 return 0; 319 } 320 321 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 322 struct hdac_ext_stream *hext_stream, int cmd) 323 { 324 struct hdac_stream *hstream = &hext_stream->hstream; 325 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 326 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 327 int ret = 0; 328 u32 run; 329 330 /* cmd must be for audio stream */ 331 switch (cmd) { 332 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 333 case SNDRV_PCM_TRIGGER_START: 334 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 335 1 << hstream->index, 336 1 << hstream->index); 337 338 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 339 sd_offset, 340 SOF_HDA_SD_CTL_DMA_START | 341 SOF_HDA_CL_DMA_SD_INT_MASK, 342 SOF_HDA_SD_CTL_DMA_START | 343 SOF_HDA_CL_DMA_SD_INT_MASK); 344 345 ret = snd_sof_dsp_read_poll_timeout(sdev, 346 HDA_DSP_HDA_BAR, 347 sd_offset, run, 348 ((run & dma_start) == dma_start), 349 HDA_DSP_REG_POLL_INTERVAL_US, 350 HDA_DSP_STREAM_RUN_TIMEOUT); 351 352 if (ret >= 0) 353 hstream->running = true; 354 355 break; 356 case SNDRV_PCM_TRIGGER_SUSPEND: 357 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 358 case SNDRV_PCM_TRIGGER_STOP: 359 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 360 sd_offset, 361 SOF_HDA_SD_CTL_DMA_START | 362 SOF_HDA_CL_DMA_SD_INT_MASK, 0x0); 363 364 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 365 sd_offset, run, 366 !(run & dma_start), 367 HDA_DSP_REG_POLL_INTERVAL_US, 368 HDA_DSP_STREAM_RUN_TIMEOUT); 369 370 if (ret >= 0) { 371 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 372 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS, 373 SOF_HDA_CL_DMA_SD_INT_MASK); 374 375 hstream->running = false; 376 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 377 SOF_HDA_INTCTL, 378 1 << hstream->index, 0x0); 379 } 380 break; 381 default: 382 dev_err(sdev->dev, "error: unknown command: %d\n", cmd); 383 return -EINVAL; 384 } 385 386 if (ret < 0) { 387 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 388 389 dev_err(sdev->dev, 390 "%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n", 391 __func__, cmd, stream_name ? stream_name : "unknown stream"); 392 kfree(stream_name); 393 } 394 395 return ret; 396 } 397 398 /* minimal recommended programming for ICCMAX stream */ 399 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 400 struct snd_dma_buffer *dmab, 401 struct snd_pcm_hw_params *params) 402 { 403 struct hdac_bus *bus = sof_to_bus(sdev); 404 struct hdac_stream *hstream = &hext_stream->hstream; 405 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 406 int ret; 407 u32 mask = 0x1 << hstream->index; 408 409 if (!hext_stream) { 410 dev_err(sdev->dev, "error: no stream available\n"); 411 return -ENODEV; 412 } 413 414 if (!dmab) { 415 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 416 return -ENODEV; 417 } 418 419 if (hstream->posbuf) 420 *hstream->posbuf = 0; 421 422 /* reset BDL address */ 423 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 424 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 425 0x0); 426 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 427 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 428 0x0); 429 430 hstream->frags = 0; 431 432 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 433 if (ret < 0) { 434 dev_err(sdev->dev, "error: set up of BDL failed\n"); 435 return ret; 436 } 437 438 /* program BDL address */ 439 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 440 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 441 (u32)hstream->bdl.addr); 442 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 443 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 444 upper_32_bits(hstream->bdl.addr)); 445 446 /* program cyclic buffer length */ 447 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 448 sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 449 hstream->bufsize); 450 451 /* program last valid index */ 452 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 453 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 454 0xffff, (hstream->frags - 1)); 455 456 /* decouple host and link DMA, enable DSP features */ 457 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 458 mask, mask); 459 460 /* Follow HW recommendation to set the guardband value to 95us during FW boot */ 461 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US); 462 463 /* start DMA */ 464 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 465 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START); 466 467 return 0; 468 } 469 470 /* 471 * prepare for common hdac registers settings, for both code loader 472 * and normal stream. 473 */ 474 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 475 struct hdac_ext_stream *hext_stream, 476 struct snd_dma_buffer *dmab, 477 struct snd_pcm_hw_params *params) 478 { 479 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 480 struct hdac_bus *bus = sof_to_bus(sdev); 481 struct hdac_stream *hstream = &hext_stream->hstream; 482 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 483 int ret; 484 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 485 u32 mask; 486 u32 run; 487 488 if (!hext_stream) { 489 dev_err(sdev->dev, "error: no stream available\n"); 490 return -ENODEV; 491 } 492 493 if (!dmab) { 494 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 495 return -ENODEV; 496 } 497 498 /* decouple host and link DMA */ 499 mask = 0x1 << hstream->index; 500 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 501 mask, mask); 502 503 /* clear stream status */ 504 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 505 SOF_HDA_CL_DMA_SD_INT_MASK | 506 SOF_HDA_SD_CTL_DMA_START, 0); 507 508 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 509 sd_offset, run, 510 !(run & dma_start), 511 HDA_DSP_REG_POLL_INTERVAL_US, 512 HDA_DSP_STREAM_RUN_TIMEOUT); 513 514 if (ret < 0) { 515 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 516 517 dev_err(sdev->dev, 518 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 519 __func__, stream_name ? stream_name : "unknown stream"); 520 kfree(stream_name); 521 return ret; 522 } 523 524 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 525 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS, 526 SOF_HDA_CL_DMA_SD_INT_MASK, 527 SOF_HDA_CL_DMA_SD_INT_MASK); 528 529 /* stream reset */ 530 ret = hda_dsp_stream_reset(sdev, hstream); 531 if (ret < 0) 532 return ret; 533 534 if (hstream->posbuf) 535 *hstream->posbuf = 0; 536 537 /* reset BDL address */ 538 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 539 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 540 0x0); 541 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 542 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 543 0x0); 544 545 /* clear stream status */ 546 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 547 SOF_HDA_CL_DMA_SD_INT_MASK | 548 SOF_HDA_SD_CTL_DMA_START, 0); 549 550 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 551 sd_offset, run, 552 !(run & dma_start), 553 HDA_DSP_REG_POLL_INTERVAL_US, 554 HDA_DSP_STREAM_RUN_TIMEOUT); 555 556 if (ret < 0) { 557 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 558 559 dev_err(sdev->dev, 560 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 561 __func__, stream_name ? stream_name : "unknown stream"); 562 kfree(stream_name); 563 return ret; 564 } 565 566 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 567 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS, 568 SOF_HDA_CL_DMA_SD_INT_MASK, 569 SOF_HDA_CL_DMA_SD_INT_MASK); 570 571 hstream->frags = 0; 572 573 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 574 if (ret < 0) { 575 dev_err(sdev->dev, "error: set up of BDL failed\n"); 576 return ret; 577 } 578 579 /* program stream tag to set up stream descriptor for DMA */ 580 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 581 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK, 582 hstream->stream_tag << 583 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT); 584 585 /* program cyclic buffer length */ 586 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 587 sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 588 hstream->bufsize); 589 590 /* 591 * Recommended hardware programming sequence for HDAudio DMA format 592 * on earlier platforms - this is not needed on newer platforms 593 * 594 * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit 595 * for corresponding stream index before the time of writing 596 * format to SDxFMT register. 597 * 2. Write SDxFMT 598 * 3. Set PPCTL.PROCEN bit for corresponding stream index to 599 * enable decoupled mode 600 */ 601 602 if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) { 603 /* couple host and link DMA, disable DSP features */ 604 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 605 mask, 0); 606 } 607 608 /* program stream format */ 609 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 610 sd_offset + 611 SOF_HDA_ADSP_REG_CL_SD_FORMAT, 612 0xffff, hstream->format_val); 613 614 if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) { 615 /* decouple host and link DMA, enable DSP features */ 616 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 617 mask, mask); 618 } 619 620 /* program last valid index */ 621 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 622 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 623 0xffff, (hstream->frags - 1)); 624 625 /* program BDL address */ 626 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 627 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 628 (u32)hstream->bdl.addr); 629 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 630 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 631 upper_32_bits(hstream->bdl.addr)); 632 633 /* enable position buffer, if needed */ 634 if (bus->use_posbuf && bus->posbuf.addr && 635 !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE) 636 & SOF_HDA_ADSP_DPLBASE_ENABLE)) { 637 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, 638 upper_32_bits(bus->posbuf.addr)); 639 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, 640 (u32)bus->posbuf.addr | 641 SOF_HDA_ADSP_DPLBASE_ENABLE); 642 } 643 644 /* set interrupt enable bits */ 645 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 646 SOF_HDA_CL_DMA_SD_INT_MASK, 647 SOF_HDA_CL_DMA_SD_INT_MASK); 648 649 /* read FIFO size */ 650 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) { 651 hstream->fifo_size = 652 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 653 sd_offset + 654 SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE); 655 hstream->fifo_size &= 0xffff; 656 hstream->fifo_size += 1; 657 } else { 658 hstream->fifo_size = 0; 659 } 660 661 return ret; 662 } 663 664 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 665 struct snd_pcm_substream *substream) 666 { 667 struct hdac_stream *hstream = substream->runtime->private_data; 668 struct hdac_ext_stream *hext_stream = container_of(hstream, 669 struct hdac_ext_stream, 670 hstream); 671 struct hdac_bus *bus = sof_to_bus(sdev); 672 u32 mask = 0x1 << hstream->index; 673 int ret; 674 675 ret = hda_dsp_stream_reset(sdev, hstream); 676 if (ret < 0) 677 return ret; 678 679 spin_lock_irq(&bus->reg_lock); 680 /* couple host and link DMA if link DMA channel is idle */ 681 if (!hext_stream->link_locked) 682 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 683 SOF_HDA_REG_PP_PPCTL, mask, 0); 684 spin_unlock_irq(&bus->reg_lock); 685 686 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); 687 688 hstream->substream = NULL; 689 690 return 0; 691 } 692 693 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev) 694 { 695 struct hdac_bus *bus = sof_to_bus(sdev); 696 bool ret = false; 697 u32 status; 698 699 /* The function can be called at irq thread, so use spin_lock_irq */ 700 spin_lock_irq(&bus->reg_lock); 701 702 status = snd_hdac_chip_readl(bus, INTSTS); 703 dev_vdbg(bus->dev, "stream irq, INTSTS status: 0x%x\n", status); 704 705 /* if Register inaccessible, ignore it.*/ 706 if (status != 0xffffffff) 707 ret = true; 708 709 spin_unlock_irq(&bus->reg_lock); 710 711 return ret; 712 } 713 714 static void 715 hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction) 716 { 717 u64 buffer_size = hstream->bufsize; 718 u64 prev_pos, pos, num_bytes; 719 720 div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos); 721 pos = hda_dsp_stream_get_position(hstream, direction, false); 722 723 if (pos < prev_pos) 724 num_bytes = (buffer_size - prev_pos) + pos; 725 else 726 num_bytes = pos - prev_pos; 727 728 hstream->curr_pos += num_bytes; 729 } 730 731 static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status) 732 { 733 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 734 struct hdac_stream *s; 735 bool active = false; 736 u32 sd_status; 737 738 list_for_each_entry(s, &bus->stream_list, list) { 739 if (status & BIT(s->index) && s->opened) { 740 sd_status = snd_hdac_stream_readb(s, SD_STS); 741 742 dev_vdbg(bus->dev, "stream %d status 0x%x\n", 743 s->index, sd_status); 744 745 snd_hdac_stream_writeb(s, SD_STS, sd_status); 746 747 active = true; 748 if ((!s->substream && !s->cstream) || 749 !s->running || 750 (sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0) 751 continue; 752 753 /* Inform ALSA only in case not do that with IPC */ 754 if (s->substream && sof_hda->no_ipc_position) { 755 snd_sof_pcm_period_elapsed(s->substream); 756 } else if (s->cstream) { 757 hda_dsp_compr_bytes_transferred(s, s->cstream->direction); 758 snd_compr_fragment_elapsed(s->cstream); 759 } 760 } 761 } 762 763 return active; 764 } 765 766 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context) 767 { 768 struct snd_sof_dev *sdev = context; 769 struct hdac_bus *bus = sof_to_bus(sdev); 770 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 771 u32 rirb_status; 772 #endif 773 bool active; 774 u32 status; 775 int i; 776 777 /* 778 * Loop 10 times to handle missed interrupts caused by 779 * unsolicited responses from the codec 780 */ 781 for (i = 0, active = true; i < 10 && active; i++) { 782 spin_lock_irq(&bus->reg_lock); 783 784 status = snd_hdac_chip_readl(bus, INTSTS); 785 786 /* check streams */ 787 active = hda_dsp_stream_check(bus, status); 788 789 /* check and clear RIRB interrupt */ 790 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 791 if (status & AZX_INT_CTRL_EN) { 792 rirb_status = snd_hdac_chip_readb(bus, RIRBSTS); 793 if (rirb_status & RIRB_INT_MASK) { 794 /* 795 * Clearing the interrupt status here ensures 796 * that no interrupt gets masked after the RIRB 797 * wp is read in snd_hdac_bus_update_rirb. 798 */ 799 snd_hdac_chip_writeb(bus, RIRBSTS, 800 RIRB_INT_MASK); 801 active = true; 802 if (rirb_status & RIRB_INT_RESPONSE) 803 snd_hdac_bus_update_rirb(bus); 804 } 805 } 806 #endif 807 spin_unlock_irq(&bus->reg_lock); 808 } 809 810 return IRQ_HANDLED; 811 } 812 813 int hda_dsp_stream_init(struct snd_sof_dev *sdev) 814 { 815 struct hdac_bus *bus = sof_to_bus(sdev); 816 struct hdac_ext_stream *hext_stream; 817 struct hdac_stream *hstream; 818 struct pci_dev *pci = to_pci_dev(sdev->dev); 819 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 820 int sd_offset; 821 int i, num_playback, num_capture, num_total, ret; 822 u32 gcap; 823 824 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP); 825 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap); 826 827 /* get stream count from GCAP */ 828 num_capture = (gcap >> 8) & 0x0f; 829 num_playback = (gcap >> 12) & 0x0f; 830 num_total = num_playback + num_capture; 831 832 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n", 833 num_playback, num_capture); 834 835 if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) { 836 dev_err(sdev->dev, "error: too many playback streams %d\n", 837 num_playback); 838 return -EINVAL; 839 } 840 841 if (num_capture >= SOF_HDA_CAPTURE_STREAMS) { 842 dev_err(sdev->dev, "error: too many capture streams %d\n", 843 num_playback); 844 return -EINVAL; 845 } 846 847 /* 848 * mem alloc for the position buffer 849 * TODO: check position buffer update 850 */ 851 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 852 SOF_HDA_DPIB_ENTRY_SIZE * num_total, 853 &bus->posbuf); 854 if (ret < 0) { 855 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n"); 856 return -ENOMEM; 857 } 858 859 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 860 /* mem alloc for the CORB/RIRB ringbuffers */ 861 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 862 PAGE_SIZE, &bus->rb); 863 if (ret < 0) { 864 dev_err(sdev->dev, "error: RB alloc failed\n"); 865 return -ENOMEM; 866 } 867 #endif 868 869 /* create capture streams */ 870 for (i = 0; i < num_capture; i++) { 871 struct sof_intel_hda_stream *hda_stream; 872 873 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream), 874 GFP_KERNEL); 875 if (!hda_stream) 876 return -ENOMEM; 877 878 hda_stream->sdev = sdev; 879 880 hext_stream = &hda_stream->hext_stream; 881 882 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 883 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i; 884 885 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 886 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total + 887 SOF_HDA_PPLC_INTERVAL * i; 888 889 /* do we support SPIB */ 890 if (sdev->bar[HDA_DSP_SPIB_BAR]) { 891 hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 892 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 893 SOF_HDA_SPIB_SPIB; 894 895 hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 896 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 897 SOF_HDA_SPIB_MAXFIFO; 898 } 899 900 hstream = &hext_stream->hstream; 901 hstream->bus = bus; 902 hstream->sd_int_sta_mask = 1 << i; 903 hstream->index = i; 904 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 905 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset; 906 hstream->stream_tag = i + 1; 907 hstream->opened = false; 908 hstream->running = false; 909 hstream->direction = SNDRV_PCM_STREAM_CAPTURE; 910 911 /* memory alloc for stream BDL */ 912 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 913 HDA_DSP_BDL_SIZE, &hstream->bdl); 914 if (ret < 0) { 915 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n"); 916 return -ENOMEM; 917 } 918 hstream->posbuf = (__le32 *)(bus->posbuf.area + 919 (hstream->index) * 8); 920 921 list_add_tail(&hstream->list, &bus->stream_list); 922 } 923 924 /* create playback streams */ 925 for (i = num_capture; i < num_total; i++) { 926 struct sof_intel_hda_stream *hda_stream; 927 928 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream), 929 GFP_KERNEL); 930 if (!hda_stream) 931 return -ENOMEM; 932 933 hda_stream->sdev = sdev; 934 935 hext_stream = &hda_stream->hext_stream; 936 937 /* we always have DSP support */ 938 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 939 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i; 940 941 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 942 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total + 943 SOF_HDA_PPLC_INTERVAL * i; 944 945 /* do we support SPIB */ 946 if (sdev->bar[HDA_DSP_SPIB_BAR]) { 947 hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 948 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 949 SOF_HDA_SPIB_SPIB; 950 951 hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 952 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 953 SOF_HDA_SPIB_MAXFIFO; 954 } 955 956 hstream = &hext_stream->hstream; 957 hstream->bus = bus; 958 hstream->sd_int_sta_mask = 1 << i; 959 hstream->index = i; 960 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 961 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset; 962 hstream->stream_tag = i - num_capture + 1; 963 hstream->opened = false; 964 hstream->running = false; 965 hstream->direction = SNDRV_PCM_STREAM_PLAYBACK; 966 967 /* mem alloc for stream BDL */ 968 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 969 HDA_DSP_BDL_SIZE, &hstream->bdl); 970 if (ret < 0) { 971 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n"); 972 return -ENOMEM; 973 } 974 975 hstream->posbuf = (__le32 *)(bus->posbuf.area + 976 (hstream->index) * 8); 977 978 list_add_tail(&hstream->list, &bus->stream_list); 979 } 980 981 /* store total stream count (playback + capture) from GCAP */ 982 sof_hda->stream_max = num_total; 983 984 return 0; 985 } 986 987 void hda_dsp_stream_free(struct snd_sof_dev *sdev) 988 { 989 struct hdac_bus *bus = sof_to_bus(sdev); 990 struct hdac_stream *s, *_s; 991 struct hdac_ext_stream *hext_stream; 992 struct sof_intel_hda_stream *hda_stream; 993 994 /* free position buffer */ 995 if (bus->posbuf.area) 996 snd_dma_free_pages(&bus->posbuf); 997 998 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 999 /* free position buffer */ 1000 if (bus->rb.area) 1001 snd_dma_free_pages(&bus->rb); 1002 #endif 1003 1004 list_for_each_entry_safe(s, _s, &bus->stream_list, list) { 1005 /* TODO: decouple */ 1006 1007 /* free bdl buffer */ 1008 if (s->bdl.area) 1009 snd_dma_free_pages(&s->bdl); 1010 list_del(&s->list); 1011 hext_stream = stream_to_hdac_ext_stream(s); 1012 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, 1013 hext_stream); 1014 devm_kfree(sdev->dev, hda_stream); 1015 } 1016 } 1017 1018 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 1019 int direction, bool can_sleep) 1020 { 1021 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream); 1022 struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream); 1023 struct snd_sof_dev *sdev = hda_stream->sdev; 1024 snd_pcm_uframes_t pos; 1025 1026 switch (sof_hda_position_quirk) { 1027 case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY: 1028 /* 1029 * This legacy code, inherited from the Skylake driver, 1030 * mixes DPIB registers and DPIB DDR updates and 1031 * does not seem to follow any known hardware recommendations. 1032 * It's not clear e.g. why there is a different flow 1033 * for capture and playback, the only information that matters is 1034 * what traffic class is used, and on all SOF-enabled platforms 1035 * only VC0 is supported so the work-around was likely not necessary 1036 * and quite possibly wrong. 1037 */ 1038 1039 /* DPIB/posbuf position mode: 1040 * For Playback, Use DPIB register from HDA space which 1041 * reflects the actual data transferred. 1042 * For Capture, Use the position buffer for pointer, as DPIB 1043 * is not accurate enough, its update may be completed 1044 * earlier than the data written to DDR. 1045 */ 1046 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1047 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1048 AZX_REG_VS_SDXDPIB_XBASE + 1049 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1050 hstream->index)); 1051 } else { 1052 /* 1053 * For capture stream, we need more workaround to fix the 1054 * position incorrect issue: 1055 * 1056 * 1. Wait at least 20us before reading position buffer after 1057 * the interrupt generated(IOC), to make sure position update 1058 * happens on frame boundary i.e. 20.833uSec for 48KHz. 1059 * 2. Perform a dummy Read to DPIB register to flush DMA 1060 * position value. 1061 * 3. Read the DMA Position from posbuf. Now the readback 1062 * value should be >= period boundary. 1063 */ 1064 if (can_sleep) 1065 usleep_range(20, 21); 1066 1067 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1068 AZX_REG_VS_SDXDPIB_XBASE + 1069 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1070 hstream->index)); 1071 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1072 } 1073 break; 1074 case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS: 1075 /* 1076 * In case VC1 traffic is disabled this is the recommended option 1077 */ 1078 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1079 AZX_REG_VS_SDXDPIB_XBASE + 1080 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1081 hstream->index)); 1082 break; 1083 case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE: 1084 /* 1085 * This is the recommended option when VC1 is enabled. 1086 * While this isn't needed for SOF platforms it's added for 1087 * consistency and debug. 1088 */ 1089 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1090 break; 1091 default: 1092 dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n", 1093 sof_hda_position_quirk); 1094 pos = 0; 1095 break; 1096 } 1097 1098 if (pos >= hstream->bufsize) 1099 pos = 0; 1100 1101 return pos; 1102 } 1103