1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/pm_runtime.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <sound/sof.h> 22 #include <trace/events/sof_intel.h> 23 #include "../ops.h" 24 #include "../sof-audio.h" 25 #include "hda.h" 26 27 #define HDA_LTRP_GB_VALUE_US 95 28 29 static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream) 30 { 31 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 32 return "Playback"; 33 else 34 return "Capture"; 35 } 36 37 static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream) 38 { 39 struct snd_soc_pcm_runtime *rtd; 40 41 if (hstream->substream) 42 rtd = asoc_substream_to_rtd(hstream->substream); 43 else if (hstream->cstream) 44 rtd = hstream->cstream->private_data; 45 else 46 /* Non audio DMA user, like dma-trace */ 47 return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)", 48 hda_hstream_direction_str(hstream), 49 hstream->stream_tag); 50 51 return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)", 52 rtd->dai_link->name, hda_hstream_direction_str(hstream), 53 hstream->stream_tag); 54 } 55 56 /* 57 * set up one of BDL entries for a stream 58 */ 59 static int hda_setup_bdle(struct snd_sof_dev *sdev, 60 struct snd_dma_buffer *dmab, 61 struct hdac_stream *hstream, 62 struct sof_intel_dsp_bdl **bdlp, 63 int offset, int size, int ioc) 64 { 65 struct hdac_bus *bus = sof_to_bus(sdev); 66 struct sof_intel_dsp_bdl *bdl = *bdlp; 67 68 while (size > 0) { 69 dma_addr_t addr; 70 int chunk; 71 72 if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) { 73 dev_err(sdev->dev, "error: stream frags exceeded\n"); 74 return -EINVAL; 75 } 76 77 addr = snd_sgbuf_get_addr(dmab, offset); 78 /* program BDL addr */ 79 bdl->addr_l = cpu_to_le32(lower_32_bits(addr)); 80 bdl->addr_h = cpu_to_le32(upper_32_bits(addr)); 81 /* program BDL size */ 82 chunk = snd_sgbuf_get_chunk_size(dmab, offset, size); 83 /* one BDLE should not cross 4K boundary */ 84 if (bus->align_bdle_4k) { 85 u32 remain = 0x1000 - (offset & 0xfff); 86 87 if (chunk > remain) 88 chunk = remain; 89 } 90 bdl->size = cpu_to_le32(chunk); 91 /* only program IOC when the whole segment is processed */ 92 size -= chunk; 93 bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01); 94 bdl++; 95 hstream->frags++; 96 offset += chunk; 97 } 98 99 *bdlp = bdl; 100 return offset; 101 } 102 103 /* 104 * set up Buffer Descriptor List (BDL) for host memory transfer 105 * BDL describes the location of the individual buffers and is little endian. 106 */ 107 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 108 struct snd_dma_buffer *dmab, 109 struct hdac_stream *hstream) 110 { 111 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 112 struct sof_intel_dsp_bdl *bdl; 113 int i, offset, period_bytes, periods; 114 int remain, ioc; 115 116 period_bytes = hstream->period_bytes; 117 dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes); 118 if (!period_bytes) 119 period_bytes = hstream->bufsize; 120 121 periods = hstream->bufsize / period_bytes; 122 123 dev_dbg(sdev->dev, "periods:%d\n", periods); 124 125 remain = hstream->bufsize % period_bytes; 126 if (remain) 127 periods++; 128 129 /* program the initial BDL entries */ 130 bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area; 131 offset = 0; 132 hstream->frags = 0; 133 134 /* 135 * set IOC if don't use position IPC 136 * and period_wakeup needed. 137 */ 138 ioc = hda->no_ipc_position ? 139 !hstream->no_period_wakeup : 0; 140 141 for (i = 0; i < periods; i++) { 142 if (i == (periods - 1) && remain) 143 /* set the last small entry */ 144 offset = hda_setup_bdle(sdev, dmab, 145 hstream, &bdl, offset, 146 remain, 0); 147 else 148 offset = hda_setup_bdle(sdev, dmab, 149 hstream, &bdl, offset, 150 period_bytes, ioc); 151 } 152 153 return offset; 154 } 155 156 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 157 struct hdac_ext_stream *hext_stream, 158 int enable, u32 size) 159 { 160 struct hdac_stream *hstream = &hext_stream->hstream; 161 u32 mask; 162 163 if (!sdev->bar[HDA_DSP_SPIB_BAR]) { 164 dev_err(sdev->dev, "error: address of spib capability is NULL\n"); 165 return -EINVAL; 166 } 167 168 mask = (1 << hstream->index); 169 170 /* enable/disable SPIB for the stream */ 171 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR, 172 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask, 173 enable << hstream->index); 174 175 /* set the SPIB value */ 176 sof_io_write(sdev, hstream->spib_addr, size); 177 178 return 0; 179 } 180 181 /* get next unused stream */ 182 struct hdac_ext_stream * 183 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags) 184 { 185 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 186 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 187 struct hdac_bus *bus = sof_to_bus(sdev); 188 struct sof_intel_hda_stream *hda_stream; 189 struct hdac_ext_stream *hext_stream = NULL; 190 struct hdac_stream *s; 191 192 spin_lock_irq(&bus->reg_lock); 193 194 /* get an unused stream */ 195 list_for_each_entry(s, &bus->stream_list, list) { 196 if (s->direction == direction && !s->opened) { 197 hext_stream = stream_to_hdac_ext_stream(s); 198 hda_stream = container_of(hext_stream, 199 struct sof_intel_hda_stream, 200 hext_stream); 201 /* check if the host DMA channel is reserved */ 202 if (hda_stream->host_reserved) 203 continue; 204 205 s->opened = true; 206 break; 207 } 208 } 209 210 spin_unlock_irq(&bus->reg_lock); 211 212 /* stream found ? */ 213 if (!hext_stream) { 214 dev_err(sdev->dev, "error: no free %s streams\n", 215 direction == SNDRV_PCM_STREAM_PLAYBACK ? 216 "playback" : "capture"); 217 return hext_stream; 218 } 219 220 hda_stream->flags = flags; 221 222 /* 223 * Prevent DMI Link L1 entry for streams that don't support it. 224 * Workaround to address a known issue with host DMA that results 225 * in xruns during pause/release in capture scenarios. This is not needed for the ACE IP. 226 */ 227 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && 228 !(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 229 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 230 HDA_VS_INTEL_EM2, 231 HDA_VS_INTEL_EM2_L1SEN, 0); 232 hda->l1_disabled = true; 233 } 234 235 return hext_stream; 236 } 237 238 /* free a stream */ 239 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag) 240 { 241 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 242 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 243 struct hdac_bus *bus = sof_to_bus(sdev); 244 struct sof_intel_hda_stream *hda_stream; 245 struct hdac_ext_stream *hext_stream; 246 struct hdac_stream *s; 247 bool dmi_l1_enable = true; 248 bool found = false; 249 250 spin_lock_irq(&bus->reg_lock); 251 252 /* 253 * close stream matching the stream tag and check if there are any open streams 254 * that are DMI L1 incompatible. 255 */ 256 list_for_each_entry(s, &bus->stream_list, list) { 257 hext_stream = stream_to_hdac_ext_stream(s); 258 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream); 259 260 if (!s->opened) 261 continue; 262 263 if (s->direction == direction && s->stream_tag == stream_tag) { 264 s->opened = false; 265 found = true; 266 } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 267 dmi_l1_enable = false; 268 } 269 } 270 271 spin_unlock_irq(&bus->reg_lock); 272 273 /* Enable DMI L1 if permitted */ 274 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && dmi_l1_enable) { 275 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 276 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN); 277 hda->l1_disabled = false; 278 } 279 280 if (!found) { 281 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n", 282 __func__, stream_tag); 283 return -ENODEV; 284 } 285 286 return 0; 287 } 288 289 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream) 290 { 291 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 292 int timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 293 u32 val; 294 295 /* enter stream reset */ 296 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 297 SOF_STREAM_SD_OFFSET_CRST); 298 do { 299 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 300 if (val & SOF_STREAM_SD_OFFSET_CRST) 301 break; 302 } while (--timeout); 303 if (timeout == 0) { 304 dev_err(sdev->dev, "timeout waiting for stream reset\n"); 305 return -ETIMEDOUT; 306 } 307 308 timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 309 310 /* exit stream reset and wait to read a zero before reading any other register */ 311 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0); 312 313 /* wait for hardware to report that stream is out of reset */ 314 udelay(3); 315 do { 316 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 317 if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0) 318 break; 319 } while (--timeout); 320 if (timeout == 0) { 321 dev_err(sdev->dev, "timeout waiting for stream to exit reset\n"); 322 return -ETIMEDOUT; 323 } 324 325 return 0; 326 } 327 328 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 329 struct hdac_ext_stream *hext_stream, int cmd) 330 { 331 struct hdac_stream *hstream = &hext_stream->hstream; 332 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 333 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 334 int ret = 0; 335 u32 run; 336 337 /* cmd must be for audio stream */ 338 switch (cmd) { 339 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 340 case SNDRV_PCM_TRIGGER_START: 341 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 342 1 << hstream->index, 343 1 << hstream->index); 344 345 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 346 sd_offset, 347 SOF_HDA_SD_CTL_DMA_START | 348 SOF_HDA_CL_DMA_SD_INT_MASK, 349 SOF_HDA_SD_CTL_DMA_START | 350 SOF_HDA_CL_DMA_SD_INT_MASK); 351 352 ret = snd_sof_dsp_read_poll_timeout(sdev, 353 HDA_DSP_HDA_BAR, 354 sd_offset, run, 355 ((run & dma_start) == dma_start), 356 HDA_DSP_REG_POLL_INTERVAL_US, 357 HDA_DSP_STREAM_RUN_TIMEOUT); 358 359 if (ret >= 0) 360 hstream->running = true; 361 362 break; 363 case SNDRV_PCM_TRIGGER_SUSPEND: 364 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 365 case SNDRV_PCM_TRIGGER_STOP: 366 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 367 sd_offset, 368 SOF_HDA_SD_CTL_DMA_START | 369 SOF_HDA_CL_DMA_SD_INT_MASK, 0x0); 370 371 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 372 sd_offset, run, 373 !(run & dma_start), 374 HDA_DSP_REG_POLL_INTERVAL_US, 375 HDA_DSP_STREAM_RUN_TIMEOUT); 376 377 if (ret >= 0) { 378 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 379 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 380 SOF_HDA_CL_DMA_SD_INT_MASK); 381 382 hstream->running = false; 383 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 384 SOF_HDA_INTCTL, 385 1 << hstream->index, 0x0); 386 } 387 break; 388 default: 389 dev_err(sdev->dev, "error: unknown command: %d\n", cmd); 390 return -EINVAL; 391 } 392 393 if (ret < 0) { 394 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 395 396 dev_err(sdev->dev, 397 "%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n", 398 __func__, cmd, stream_name ? stream_name : "unknown stream"); 399 kfree(stream_name); 400 } 401 402 return ret; 403 } 404 405 /* minimal recommended programming for ICCMAX stream */ 406 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 407 struct snd_dma_buffer *dmab, 408 struct snd_pcm_hw_params *params) 409 { 410 struct hdac_stream *hstream = &hext_stream->hstream; 411 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 412 int ret; 413 u32 mask = 0x1 << hstream->index; 414 415 if (!hext_stream) { 416 dev_err(sdev->dev, "error: no stream available\n"); 417 return -ENODEV; 418 } 419 420 if (!dmab) { 421 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 422 return -ENODEV; 423 } 424 425 if (hstream->posbuf) 426 *hstream->posbuf = 0; 427 428 /* reset BDL address */ 429 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 430 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 431 0x0); 432 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 433 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 434 0x0); 435 436 hstream->frags = 0; 437 438 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 439 if (ret < 0) { 440 dev_err(sdev->dev, "error: set up of BDL failed\n"); 441 return ret; 442 } 443 444 /* program BDL address */ 445 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 446 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 447 (u32)hstream->bdl.addr); 448 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 449 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 450 upper_32_bits(hstream->bdl.addr)); 451 452 /* program cyclic buffer length */ 453 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 454 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 455 hstream->bufsize); 456 457 /* program last valid index */ 458 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 459 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 460 0xffff, (hstream->frags - 1)); 461 462 /* decouple host and link DMA, enable DSP features */ 463 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 464 mask, mask); 465 466 /* Follow HW recommendation to set the guardband value to 95us during FW boot */ 467 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP, 468 HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US); 469 470 /* start DMA */ 471 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 472 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START); 473 474 return 0; 475 } 476 477 /* 478 * prepare for common hdac registers settings, for both code loader 479 * and normal stream. 480 */ 481 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 482 struct hdac_ext_stream *hext_stream, 483 struct snd_dma_buffer *dmab, 484 struct snd_pcm_hw_params *params) 485 { 486 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 487 struct hdac_bus *bus = sof_to_bus(sdev); 488 struct hdac_stream *hstream = &hext_stream->hstream; 489 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 490 int ret; 491 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 492 u32 mask; 493 u32 run; 494 495 if (!hext_stream) { 496 dev_err(sdev->dev, "error: no stream available\n"); 497 return -ENODEV; 498 } 499 500 if (!dmab) { 501 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 502 return -ENODEV; 503 } 504 505 /* decouple host and link DMA */ 506 mask = 0x1 << hstream->index; 507 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 508 mask, mask); 509 510 /* clear stream status */ 511 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 512 SOF_HDA_CL_DMA_SD_INT_MASK | 513 SOF_HDA_SD_CTL_DMA_START, 0); 514 515 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 516 sd_offset, run, 517 !(run & dma_start), 518 HDA_DSP_REG_POLL_INTERVAL_US, 519 HDA_DSP_STREAM_RUN_TIMEOUT); 520 521 if (ret < 0) { 522 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 523 524 dev_err(sdev->dev, 525 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 526 __func__, stream_name ? stream_name : "unknown stream"); 527 kfree(stream_name); 528 return ret; 529 } 530 531 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 532 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 533 SOF_HDA_CL_DMA_SD_INT_MASK, 534 SOF_HDA_CL_DMA_SD_INT_MASK); 535 536 /* stream reset */ 537 ret = hda_dsp_stream_reset(sdev, hstream); 538 if (ret < 0) 539 return ret; 540 541 if (hstream->posbuf) 542 *hstream->posbuf = 0; 543 544 /* reset BDL address */ 545 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 546 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 547 0x0); 548 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 549 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 550 0x0); 551 552 /* clear stream status */ 553 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 554 SOF_HDA_CL_DMA_SD_INT_MASK | 555 SOF_HDA_SD_CTL_DMA_START, 0); 556 557 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 558 sd_offset, run, 559 !(run & dma_start), 560 HDA_DSP_REG_POLL_INTERVAL_US, 561 HDA_DSP_STREAM_RUN_TIMEOUT); 562 563 if (ret < 0) { 564 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 565 566 dev_err(sdev->dev, 567 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 568 __func__, stream_name ? stream_name : "unknown stream"); 569 kfree(stream_name); 570 return ret; 571 } 572 573 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 574 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 575 SOF_HDA_CL_DMA_SD_INT_MASK, 576 SOF_HDA_CL_DMA_SD_INT_MASK); 577 578 hstream->frags = 0; 579 580 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 581 if (ret < 0) { 582 dev_err(sdev->dev, "error: set up of BDL failed\n"); 583 return ret; 584 } 585 586 /* program stream tag to set up stream descriptor for DMA */ 587 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 588 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK, 589 hstream->stream_tag << 590 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT); 591 592 /* program cyclic buffer length */ 593 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 594 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 595 hstream->bufsize); 596 597 /* 598 * Recommended hardware programming sequence for HDAudio DMA format 599 * on earlier platforms - this is not needed on newer platforms 600 * 601 * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit 602 * for corresponding stream index before the time of writing 603 * format to SDxFMT register. 604 * 2. Write SDxFMT 605 * 3. Set PPCTL.PROCEN bit for corresponding stream index to 606 * enable decoupled mode 607 */ 608 609 if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) { 610 /* couple host and link DMA, disable DSP features */ 611 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 612 mask, 0); 613 } 614 615 /* program stream format */ 616 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 617 sd_offset + 618 SOF_HDA_ADSP_REG_SD_FORMAT, 619 0xffff, hstream->format_val); 620 621 if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) { 622 /* decouple host and link DMA, enable DSP features */ 623 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 624 mask, mask); 625 } 626 627 /* program last valid index */ 628 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 629 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 630 0xffff, (hstream->frags - 1)); 631 632 /* program BDL address */ 633 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 634 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 635 (u32)hstream->bdl.addr); 636 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 637 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 638 upper_32_bits(hstream->bdl.addr)); 639 640 /* enable position buffer, if needed */ 641 if (bus->use_posbuf && bus->posbuf.addr && 642 !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE) 643 & SOF_HDA_ADSP_DPLBASE_ENABLE)) { 644 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, 645 upper_32_bits(bus->posbuf.addr)); 646 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, 647 (u32)bus->posbuf.addr | 648 SOF_HDA_ADSP_DPLBASE_ENABLE); 649 } 650 651 /* set interrupt enable bits */ 652 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 653 SOF_HDA_CL_DMA_SD_INT_MASK, 654 SOF_HDA_CL_DMA_SD_INT_MASK); 655 656 /* read FIFO size */ 657 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) { 658 hstream->fifo_size = 659 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 660 sd_offset + 661 SOF_HDA_ADSP_REG_SD_FIFOSIZE); 662 hstream->fifo_size &= 0xffff; 663 hstream->fifo_size += 1; 664 } else { 665 hstream->fifo_size = 0; 666 } 667 668 return ret; 669 } 670 671 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 672 struct snd_pcm_substream *substream) 673 { 674 struct hdac_stream *hstream = substream->runtime->private_data; 675 struct hdac_ext_stream *hext_stream = container_of(hstream, 676 struct hdac_ext_stream, 677 hstream); 678 struct hdac_bus *bus = sof_to_bus(sdev); 679 u32 mask = 0x1 << hstream->index; 680 int ret; 681 682 ret = hda_dsp_stream_reset(sdev, hstream); 683 if (ret < 0) 684 return ret; 685 686 spin_lock_irq(&bus->reg_lock); 687 /* couple host and link DMA if link DMA channel is idle */ 688 if (!hext_stream->link_locked) 689 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 690 SOF_HDA_REG_PP_PPCTL, mask, 0); 691 spin_unlock_irq(&bus->reg_lock); 692 693 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); 694 695 hstream->substream = NULL; 696 697 return 0; 698 } 699 700 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev) 701 { 702 struct hdac_bus *bus = sof_to_bus(sdev); 703 bool ret = false; 704 u32 status; 705 706 /* The function can be called at irq thread, so use spin_lock_irq */ 707 spin_lock_irq(&bus->reg_lock); 708 709 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 710 711 trace_sof_intel_hda_dsp_check_stream_irq(sdev, status); 712 713 /* if Register inaccessible, ignore it.*/ 714 if (status != 0xffffffff) 715 ret = true; 716 717 spin_unlock_irq(&bus->reg_lock); 718 719 return ret; 720 } 721 722 static void 723 hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction) 724 { 725 u64 buffer_size = hstream->bufsize; 726 u64 prev_pos, pos, num_bytes; 727 728 div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos); 729 pos = hda_dsp_stream_get_position(hstream, direction, false); 730 731 if (pos < prev_pos) 732 num_bytes = (buffer_size - prev_pos) + pos; 733 else 734 num_bytes = pos - prev_pos; 735 736 hstream->curr_pos += num_bytes; 737 } 738 739 static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status) 740 { 741 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 742 struct hdac_stream *s; 743 bool active = false; 744 u32 sd_status; 745 746 list_for_each_entry(s, &bus->stream_list, list) { 747 if (status & BIT(s->index) && s->opened) { 748 sd_status = readb(s->sd_addr + SOF_HDA_ADSP_REG_SD_STS); 749 750 trace_sof_intel_hda_dsp_stream_status(bus->dev, s, sd_status); 751 752 writeb(sd_status, s->sd_addr + SOF_HDA_ADSP_REG_SD_STS); 753 754 active = true; 755 if ((!s->substream && !s->cstream) || 756 !s->running || 757 (sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0) 758 continue; 759 760 /* Inform ALSA only in case not do that with IPC */ 761 if (s->substream && sof_hda->no_ipc_position) { 762 snd_sof_pcm_period_elapsed(s->substream); 763 } else if (s->cstream) { 764 hda_dsp_compr_bytes_transferred(s, s->cstream->direction); 765 snd_compr_fragment_elapsed(s->cstream); 766 } 767 } 768 } 769 770 return active; 771 } 772 773 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context) 774 { 775 struct snd_sof_dev *sdev = context; 776 struct hdac_bus *bus = sof_to_bus(sdev); 777 bool active; 778 u32 status; 779 int i; 780 781 /* 782 * Loop 10 times to handle missed interrupts caused by 783 * unsolicited responses from the codec 784 */ 785 for (i = 0, active = true; i < 10 && active; i++) { 786 spin_lock_irq(&bus->reg_lock); 787 788 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 789 790 /* check streams */ 791 active = hda_dsp_stream_check(bus, status); 792 793 /* check and clear RIRB interrupt */ 794 if (status & AZX_INT_CTRL_EN) { 795 active |= hda_codec_check_rirb_status(sdev); 796 } 797 spin_unlock_irq(&bus->reg_lock); 798 } 799 800 return IRQ_HANDLED; 801 } 802 803 int hda_dsp_stream_init(struct snd_sof_dev *sdev) 804 { 805 struct hdac_bus *bus = sof_to_bus(sdev); 806 struct hdac_ext_stream *hext_stream; 807 struct hdac_stream *hstream; 808 struct pci_dev *pci = to_pci_dev(sdev->dev); 809 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 810 int sd_offset; 811 int i, num_playback, num_capture, num_total, ret; 812 u32 gcap; 813 814 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP); 815 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap); 816 817 /* get stream count from GCAP */ 818 num_capture = (gcap >> 8) & 0x0f; 819 num_playback = (gcap >> 12) & 0x0f; 820 num_total = num_playback + num_capture; 821 822 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n", 823 num_playback, num_capture); 824 825 if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) { 826 dev_err(sdev->dev, "error: too many playback streams %d\n", 827 num_playback); 828 return -EINVAL; 829 } 830 831 if (num_capture >= SOF_HDA_CAPTURE_STREAMS) { 832 dev_err(sdev->dev, "error: too many capture streams %d\n", 833 num_playback); 834 return -EINVAL; 835 } 836 837 /* 838 * mem alloc for the position buffer 839 * TODO: check position buffer update 840 */ 841 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 842 SOF_HDA_DPIB_ENTRY_SIZE * num_total, 843 &bus->posbuf); 844 if (ret < 0) { 845 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n"); 846 return -ENOMEM; 847 } 848 849 /* 850 * mem alloc for the CORB/RIRB ringbuffers - this will be used only for 851 * HDAudio codecs 852 */ 853 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 854 PAGE_SIZE, &bus->rb); 855 if (ret < 0) { 856 dev_err(sdev->dev, "error: RB alloc failed\n"); 857 return -ENOMEM; 858 } 859 860 /* create capture streams */ 861 for (i = 0; i < num_capture; i++) { 862 struct sof_intel_hda_stream *hda_stream; 863 864 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream), 865 GFP_KERNEL); 866 if (!hda_stream) 867 return -ENOMEM; 868 869 hda_stream->sdev = sdev; 870 871 hext_stream = &hda_stream->hext_stream; 872 873 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 874 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i; 875 876 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 877 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total + 878 SOF_HDA_PPLC_INTERVAL * i; 879 880 hstream = &hext_stream->hstream; 881 882 /* do we support SPIB */ 883 if (sdev->bar[HDA_DSP_SPIB_BAR]) { 884 hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 885 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 886 SOF_HDA_SPIB_SPIB; 887 888 hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 889 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 890 SOF_HDA_SPIB_MAXFIFO; 891 } 892 893 hstream->bus = bus; 894 hstream->sd_int_sta_mask = 1 << i; 895 hstream->index = i; 896 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 897 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset; 898 hstream->stream_tag = i + 1; 899 hstream->opened = false; 900 hstream->running = false; 901 hstream->direction = SNDRV_PCM_STREAM_CAPTURE; 902 903 /* memory alloc for stream BDL */ 904 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 905 HDA_DSP_BDL_SIZE, &hstream->bdl); 906 if (ret < 0) { 907 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n"); 908 return -ENOMEM; 909 } 910 hstream->posbuf = (__le32 *)(bus->posbuf.area + 911 (hstream->index) * 8); 912 913 list_add_tail(&hstream->list, &bus->stream_list); 914 } 915 916 /* create playback streams */ 917 for (i = num_capture; i < num_total; i++) { 918 struct sof_intel_hda_stream *hda_stream; 919 920 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream), 921 GFP_KERNEL); 922 if (!hda_stream) 923 return -ENOMEM; 924 925 hda_stream->sdev = sdev; 926 927 hext_stream = &hda_stream->hext_stream; 928 929 /* we always have DSP support */ 930 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 931 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i; 932 933 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 934 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total + 935 SOF_HDA_PPLC_INTERVAL * i; 936 937 hstream = &hext_stream->hstream; 938 939 /* do we support SPIB */ 940 if (sdev->bar[HDA_DSP_SPIB_BAR]) { 941 hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 942 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 943 SOF_HDA_SPIB_SPIB; 944 945 hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 946 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 947 SOF_HDA_SPIB_MAXFIFO; 948 } 949 950 hstream->bus = bus; 951 hstream->sd_int_sta_mask = 1 << i; 952 hstream->index = i; 953 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 954 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset; 955 hstream->stream_tag = i - num_capture + 1; 956 hstream->opened = false; 957 hstream->running = false; 958 hstream->direction = SNDRV_PCM_STREAM_PLAYBACK; 959 960 /* mem alloc for stream BDL */ 961 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 962 HDA_DSP_BDL_SIZE, &hstream->bdl); 963 if (ret < 0) { 964 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n"); 965 return -ENOMEM; 966 } 967 968 hstream->posbuf = (__le32 *)(bus->posbuf.area + 969 (hstream->index) * 8); 970 971 list_add_tail(&hstream->list, &bus->stream_list); 972 } 973 974 /* store total stream count (playback + capture) from GCAP */ 975 sof_hda->stream_max = num_total; 976 977 return 0; 978 } 979 980 void hda_dsp_stream_free(struct snd_sof_dev *sdev) 981 { 982 struct hdac_bus *bus = sof_to_bus(sdev); 983 struct hdac_stream *s, *_s; 984 struct hdac_ext_stream *hext_stream; 985 struct sof_intel_hda_stream *hda_stream; 986 987 /* free position buffer */ 988 if (bus->posbuf.area) 989 snd_dma_free_pages(&bus->posbuf); 990 991 /* free CORB/RIRB buffer - only used for HDaudio codecs */ 992 if (bus->rb.area) 993 snd_dma_free_pages(&bus->rb); 994 995 list_for_each_entry_safe(s, _s, &bus->stream_list, list) { 996 /* TODO: decouple */ 997 998 /* free bdl buffer */ 999 if (s->bdl.area) 1000 snd_dma_free_pages(&s->bdl); 1001 list_del(&s->list); 1002 hext_stream = stream_to_hdac_ext_stream(s); 1003 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, 1004 hext_stream); 1005 devm_kfree(sdev->dev, hda_stream); 1006 } 1007 } 1008 1009 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 1010 int direction, bool can_sleep) 1011 { 1012 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream); 1013 struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream); 1014 struct snd_sof_dev *sdev = hda_stream->sdev; 1015 snd_pcm_uframes_t pos; 1016 1017 switch (sof_hda_position_quirk) { 1018 case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY: 1019 /* 1020 * This legacy code, inherited from the Skylake driver, 1021 * mixes DPIB registers and DPIB DDR updates and 1022 * does not seem to follow any known hardware recommendations. 1023 * It's not clear e.g. why there is a different flow 1024 * for capture and playback, the only information that matters is 1025 * what traffic class is used, and on all SOF-enabled platforms 1026 * only VC0 is supported so the work-around was likely not necessary 1027 * and quite possibly wrong. 1028 */ 1029 1030 /* DPIB/posbuf position mode: 1031 * For Playback, Use DPIB register from HDA space which 1032 * reflects the actual data transferred. 1033 * For Capture, Use the position buffer for pointer, as DPIB 1034 * is not accurate enough, its update may be completed 1035 * earlier than the data written to DDR. 1036 */ 1037 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1038 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1039 AZX_REG_VS_SDXDPIB_XBASE + 1040 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1041 hstream->index)); 1042 } else { 1043 /* 1044 * For capture stream, we need more workaround to fix the 1045 * position incorrect issue: 1046 * 1047 * 1. Wait at least 20us before reading position buffer after 1048 * the interrupt generated(IOC), to make sure position update 1049 * happens on frame boundary i.e. 20.833uSec for 48KHz. 1050 * 2. Perform a dummy Read to DPIB register to flush DMA 1051 * position value. 1052 * 3. Read the DMA Position from posbuf. Now the readback 1053 * value should be >= period boundary. 1054 */ 1055 if (can_sleep) 1056 usleep_range(20, 21); 1057 1058 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1059 AZX_REG_VS_SDXDPIB_XBASE + 1060 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1061 hstream->index)); 1062 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1063 } 1064 break; 1065 case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS: 1066 /* 1067 * In case VC1 traffic is disabled this is the recommended option 1068 */ 1069 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1070 AZX_REG_VS_SDXDPIB_XBASE + 1071 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1072 hstream->index)); 1073 break; 1074 case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE: 1075 /* 1076 * This is the recommended option when VC1 is enabled. 1077 * While this isn't needed for SOF platforms it's added for 1078 * consistency and debug. 1079 */ 1080 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1081 break; 1082 default: 1083 dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n", 1084 sof_hda_position_quirk); 1085 pos = 0; 1086 break; 1087 } 1088 1089 if (pos >= hstream->bufsize) 1090 pos = 0; 1091 1092 return pos; 1093 } 1094