1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for HDA DSP code loader 16 */ 17 18 #include <linux/firmware.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/sof.h> 21 #include "../ops.h" 22 #include "hda.h" 23 24 #define HDA_FW_BOOT_ATTEMPTS 3 25 26 static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 27 unsigned int size, struct snd_dma_buffer *dmab, 28 int direction) 29 { 30 struct hdac_ext_stream *dsp_stream; 31 struct hdac_stream *hstream; 32 struct pci_dev *pci = to_pci_dev(sdev->dev); 33 int ret; 34 35 if (direction != SNDRV_PCM_STREAM_PLAYBACK) { 36 dev_err(sdev->dev, "error: code loading DMA is playback only\n"); 37 return -EINVAL; 38 } 39 40 dsp_stream = hda_dsp_stream_get(sdev, direction); 41 42 if (!dsp_stream) { 43 dev_err(sdev->dev, "error: no stream available\n"); 44 return -ENODEV; 45 } 46 hstream = &dsp_stream->hstream; 47 hstream->substream = NULL; 48 49 /* allocate DMA buffer */ 50 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); 51 if (ret < 0) { 52 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret); 53 goto error; 54 } 55 56 hstream->period_bytes = 0;/* initialize period_bytes */ 57 hstream->format_val = format; 58 hstream->bufsize = size; 59 60 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL); 61 if (ret < 0) { 62 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret); 63 goto error; 64 } 65 66 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size); 67 68 return hstream->stream_tag; 69 70 error: 71 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 72 snd_dma_free_pages(dmab); 73 return ret; 74 } 75 76 /* 77 * first boot sequence has some extra steps. core 0 waits for power 78 * status on core 1, so power up core 1 also momentarily, keep it in 79 * reset/stall and then turn it off 80 */ 81 static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata, 82 u32 fwsize, int stream_tag) 83 { 84 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 85 const struct sof_intel_dsp_desc *chip = hda->desc; 86 unsigned int status; 87 int ret; 88 int i; 89 90 /* step 1: power up corex */ 91 ret = hda_dsp_core_power_up(sdev, chip->cores_mask); 92 if (ret < 0) { 93 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); 94 goto err; 95 } 96 97 /* DSP is powered up, set all SSPs to slave mode */ 98 for (i = 0; i < chip->ssp_count; i++) { 99 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 100 chip->ssp_base_offset 101 + i * SSP_DEV_MEM_SIZE 102 + SSP_SSC1_OFFSET, 103 SSP_SET_SLAVE, 104 SSP_SET_SLAVE); 105 } 106 107 /* step 2: purge FW request */ 108 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, 109 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW | 110 ((stream_tag - 1) << 9))); 111 112 /* step 3: unset core 0 reset state & unstall/run core 0 */ 113 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0)); 114 if (ret < 0) { 115 dev_err(sdev->dev, "error: dsp core start failed %d\n", ret); 116 ret = -EIO; 117 goto err; 118 } 119 120 /* step 4: wait for IPC DONE bit from ROM */ 121 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 122 chip->ipc_ack, status, 123 ((status & chip->ipc_ack_mask) 124 == chip->ipc_ack_mask), 125 HDA_DSP_REG_POLL_INTERVAL_US, 126 HDA_DSP_INIT_TIMEOUT_US); 127 128 if (ret < 0) { 129 dev_err(sdev->dev, "error: %s: timeout for HIPCIE done\n", 130 __func__); 131 goto err; 132 } 133 134 /* set DONE bit to clear the reply IPC message */ 135 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 136 chip->ipc_ack, 137 chip->ipc_ack_mask, 138 chip->ipc_ack_mask); 139 140 /* step 5: power down corex */ 141 ret = hda_dsp_core_power_down(sdev, 142 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0))); 143 if (ret < 0) { 144 dev_err(sdev->dev, "error: dsp core x power down failed\n"); 145 goto err; 146 } 147 148 /* step 6: enable IPC interrupts */ 149 hda_dsp_ipc_int_enable(sdev); 150 151 /* step 7: wait for ROM init */ 152 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 153 HDA_DSP_SRAM_REG_ROM_STATUS, status, 154 ((status & HDA_DSP_ROM_STS_MASK) 155 == HDA_DSP_ROM_INIT), 156 HDA_DSP_REG_POLL_INTERVAL_US, 157 chip->rom_init_timeout * 158 USEC_PER_MSEC); 159 if (!ret) 160 return 0; 161 162 dev_err(sdev->dev, 163 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 164 __func__); 165 166 err: 167 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 168 hda_dsp_core_reset_power_down(sdev, chip->cores_mask); 169 170 return ret; 171 } 172 173 static int cl_trigger(struct snd_sof_dev *sdev, 174 struct hdac_ext_stream *stream, int cmd) 175 { 176 struct hdac_stream *hstream = &stream->hstream; 177 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 178 179 /* code loader is special case that reuses stream ops */ 180 switch (cmd) { 181 case SNDRV_PCM_TRIGGER_START: 182 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 183 1 << hstream->index, 184 1 << hstream->index); 185 186 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 187 sd_offset, 188 SOF_HDA_SD_CTL_DMA_START | 189 SOF_HDA_CL_DMA_SD_INT_MASK, 190 SOF_HDA_SD_CTL_DMA_START | 191 SOF_HDA_CL_DMA_SD_INT_MASK); 192 193 hstream->running = true; 194 return 0; 195 default: 196 return hda_dsp_stream_trigger(sdev, stream, cmd); 197 } 198 } 199 200 static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev, 201 int tag) 202 { 203 struct hdac_bus *bus = sof_to_bus(sdev); 204 struct hdac_stream *s; 205 206 /* get stream with tag */ 207 list_for_each_entry(s, &bus->stream_list, list) { 208 if (s->direction == SNDRV_PCM_STREAM_PLAYBACK && 209 s->stream_tag == tag) { 210 return stream_to_hdac_ext_stream(s); 211 } 212 } 213 214 return NULL; 215 } 216 217 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 218 struct hdac_ext_stream *stream) 219 { 220 struct hdac_stream *hstream = &stream->hstream; 221 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 222 int ret; 223 224 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0); 225 226 hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK, 227 hstream->stream_tag); 228 hstream->running = 0; 229 hstream->substream = NULL; 230 231 /* reset BDL address */ 232 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 233 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); 234 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 235 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); 236 237 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 238 snd_dma_free_pages(dmab); 239 dmab->area = NULL; 240 hstream->bufsize = 0; 241 hstream->format_val = 0; 242 243 return ret; 244 } 245 246 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream) 247 { 248 unsigned int reg; 249 int ret, status; 250 251 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START); 252 if (ret < 0) { 253 dev_err(sdev->dev, "error: DMA trigger start failed\n"); 254 return ret; 255 } 256 257 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 258 HDA_DSP_SRAM_REG_ROM_STATUS, reg, 259 ((reg & HDA_DSP_ROM_STS_MASK) 260 == HDA_DSP_ROM_FW_ENTERED), 261 HDA_DSP_REG_POLL_INTERVAL_US, 262 HDA_DSP_BASEFW_TIMEOUT_US); 263 264 /* 265 * even in case of errors we still need to stop the DMAs, 266 * but we return the initial error should the DMA stop also fail 267 */ 268 269 if (status < 0) { 270 dev_err(sdev->dev, 271 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 272 __func__); 273 } 274 275 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP); 276 if (ret < 0) { 277 dev_err(sdev->dev, "error: DMA trigger stop failed\n"); 278 if (!status) 279 status = ret; 280 } 281 282 return status; 283 } 284 285 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 286 { 287 struct snd_sof_pdata *plat_data = sdev->pdata; 288 const struct sof_dev_desc *desc = plat_data->desc; 289 const struct sof_intel_dsp_desc *chip_info; 290 struct hdac_ext_stream *stream; 291 struct firmware stripped_firmware; 292 int ret, ret1, tag, i; 293 294 chip_info = desc->chip_info; 295 296 stripped_firmware.data = plat_data->fw->data; 297 stripped_firmware.size = plat_data->fw->size; 298 299 /* init for booting wait */ 300 init_waitqueue_head(&sdev->boot_wait); 301 302 /* prepare DMA for code loader stream */ 303 tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size, 304 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK); 305 306 if (tag < 0) { 307 dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n", 308 tag); 309 return tag; 310 } 311 312 /* get stream with tag */ 313 stream = get_stream_with_tag(sdev, tag); 314 if (!stream) { 315 dev_err(sdev->dev, 316 "error: could not get stream with stream tag %d\n", 317 tag); 318 ret = -ENODEV; 319 goto err; 320 } 321 322 memcpy(sdev->dmab.area, stripped_firmware.data, 323 stripped_firmware.size); 324 325 /* try ROM init a few times before giving up */ 326 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { 327 ret = cl_dsp_init(sdev, stripped_firmware.data, 328 stripped_firmware.size, tag); 329 330 /* don't retry anymore if successful */ 331 if (!ret) 332 break; 333 334 dev_dbg(sdev->dev, "iteration %d of Core En/ROM load failed: %d\n", 335 i, ret); 336 dev_dbg(sdev->dev, "Error code=0x%x: FW status=0x%x\n", 337 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 338 HDA_DSP_SRAM_REG_ROM_ERROR), 339 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 340 HDA_DSP_SRAM_REG_ROM_STATUS)); 341 } 342 343 if (i == HDA_FW_BOOT_ATTEMPTS) { 344 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", 345 i, ret); 346 goto cleanup; 347 } 348 349 /* 350 * When a SoundWire link is in clock stop state, a Slave 351 * device may trigger in-band wakes for events such as jack 352 * insertion or acoustic event detection. This event will lead 353 * to a WAKEEN interrupt, handled by the PCI device and routed 354 * to PME if the PCI device is in D3. The resume function in 355 * audio PCI driver will be invoked by ACPI for PME event and 356 * initialize the device and process WAKEEN interrupt. 357 * 358 * The WAKEEN interrupt should be processed ASAP to prevent an 359 * interrupt flood, otherwise other interrupts, such IPC, 360 * cannot work normally. The WAKEEN is handled after the ROM 361 * is initialized successfully, which ensures power rails are 362 * enabled before accessing the SoundWire SHIM registers 363 */ 364 if (!sdev->first_boot) 365 hda_sdw_process_wakeen(sdev); 366 367 /* 368 * at this point DSP ROM has been initialized and 369 * should be ready for code loading and firmware boot 370 */ 371 ret = cl_copy_fw(sdev, stream); 372 if (!ret) 373 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 374 else 375 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret); 376 377 cleanup: 378 /* 379 * Perform codeloader stream cleanup. 380 * This should be done even if firmware loading fails. 381 * If the cleanup also fails, we return the initial error 382 */ 383 ret1 = cl_cleanup(sdev, &sdev->dmab, stream); 384 if (ret1 < 0) { 385 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); 386 387 /* set return value to indicate cleanup failure */ 388 if (!ret) 389 ret = ret1; 390 } 391 392 /* 393 * return master core id if both fw copy 394 * and stream clean up are successful 395 */ 396 if (!ret) 397 return chip_info->init_core_mask; 398 399 /* dump dsp registers and disable DSP upon error */ 400 err: 401 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 402 403 /* disable DSP */ 404 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 405 SOF_HDA_REG_PP_PPCTL, 406 SOF_HDA_PPCTL_GPROCEN, 0); 407 return ret; 408 } 409 410 /* pre fw run operations */ 411 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) 412 { 413 /* disable clock gating and power gating */ 414 return hda_dsp_ctrl_clock_power_gating(sdev, false); 415 } 416 417 /* post fw run operations */ 418 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) 419 { 420 int ret; 421 422 if (sdev->first_boot) { 423 ret = hda_sdw_startup(sdev); 424 if (ret < 0) { 425 dev_err(sdev->dev, 426 "error: could not startup SoundWire links\n"); 427 return ret; 428 } 429 } 430 431 hda_sdw_int_enable(sdev, true); 432 433 /* re-enable clock gating and power gating */ 434 return hda_dsp_ctrl_clock_power_gating(sdev, true); 435 } 436