1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for HDA DSP code loader 16 */ 17 18 #include <linux/firmware.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/sof.h> 21 #include "../ops.h" 22 #include "hda.h" 23 24 #define HDA_FW_BOOT_ATTEMPTS 3 25 26 static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 27 unsigned int size, struct snd_dma_buffer *dmab, 28 int direction) 29 { 30 struct hdac_ext_stream *dsp_stream; 31 struct hdac_stream *hstream; 32 struct pci_dev *pci = to_pci_dev(sdev->dev); 33 int ret; 34 35 if (direction != SNDRV_PCM_STREAM_PLAYBACK) { 36 dev_err(sdev->dev, "error: code loading DMA is playback only\n"); 37 return -EINVAL; 38 } 39 40 dsp_stream = hda_dsp_stream_get(sdev, direction); 41 42 if (!dsp_stream) { 43 dev_err(sdev->dev, "error: no stream available\n"); 44 return -ENODEV; 45 } 46 hstream = &dsp_stream->hstream; 47 48 /* allocate DMA buffer */ 49 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); 50 if (ret < 0) { 51 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret); 52 goto error; 53 } 54 55 hstream->period_bytes = 0;/* initialize period_bytes */ 56 hstream->format_val = format; 57 hstream->bufsize = size; 58 59 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL); 60 if (ret < 0) { 61 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret); 62 goto error; 63 } 64 65 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size); 66 67 return hstream->stream_tag; 68 69 error: 70 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 71 snd_dma_free_pages(dmab); 72 return ret; 73 } 74 75 /* 76 * first boot sequence has some extra steps. core 0 waits for power 77 * status on core 1, so power up core 1 also momentarily, keep it in 78 * reset/stall and then turn it off 79 */ 80 static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata, 81 u32 fwsize, int stream_tag) 82 { 83 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 84 const struct sof_intel_dsp_desc *chip = hda->desc; 85 unsigned int status; 86 int ret; 87 int i; 88 89 /* step 1: power up corex */ 90 ret = hda_dsp_core_power_up(sdev, chip->cores_mask); 91 if (ret < 0) { 92 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); 93 goto err; 94 } 95 96 /* DSP is powered up, set all SSPs to slave mode */ 97 for (i = 0; i < chip->ssp_count; i++) { 98 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 99 chip->ssp_base_offset 100 + i * SSP_DEV_MEM_SIZE 101 + SSP_SSC1_OFFSET, 102 SSP_SET_SLAVE, 103 SSP_SET_SLAVE); 104 } 105 106 /* step 2: purge FW request */ 107 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, 108 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW | 109 ((stream_tag - 1) << 9))); 110 111 /* step 3: unset core 0 reset state & unstall/run core 0 */ 112 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0)); 113 if (ret < 0) { 114 dev_err(sdev->dev, "error: dsp core start failed %d\n", ret); 115 ret = -EIO; 116 goto err; 117 } 118 119 /* step 4: wait for IPC DONE bit from ROM */ 120 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 121 chip->ipc_ack, status, 122 ((status & chip->ipc_ack_mask) 123 == chip->ipc_ack_mask), 124 HDA_DSP_REG_POLL_INTERVAL_US, 125 HDA_DSP_INIT_TIMEOUT_US); 126 127 if (ret < 0) { 128 dev_err(sdev->dev, "error: waiting for HIPCIE done\n"); 129 goto err; 130 } 131 132 /* step 5: power down corex */ 133 ret = hda_dsp_core_power_down(sdev, 134 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0))); 135 if (ret < 0) { 136 dev_err(sdev->dev, "error: dsp core x power down failed\n"); 137 goto err; 138 } 139 140 /* step 6: enable IPC interrupts */ 141 hda_dsp_ipc_int_enable(sdev); 142 143 /* step 7: wait for ROM init */ 144 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 145 HDA_DSP_SRAM_REG_ROM_STATUS, status, 146 ((status & HDA_DSP_ROM_STS_MASK) 147 == HDA_DSP_ROM_INIT), 148 HDA_DSP_REG_POLL_INTERVAL_US, 149 chip->rom_init_timeout * 150 USEC_PER_MSEC); 151 if (!ret) 152 return 0; 153 154 err: 155 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 156 hda_dsp_core_reset_power_down(sdev, chip->cores_mask); 157 158 return ret; 159 } 160 161 static int cl_trigger(struct snd_sof_dev *sdev, 162 struct hdac_ext_stream *stream, int cmd) 163 { 164 struct hdac_stream *hstream = &stream->hstream; 165 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 166 167 /* code loader is special case that reuses stream ops */ 168 switch (cmd) { 169 case SNDRV_PCM_TRIGGER_START: 170 wait_event_timeout(sdev->waitq, !sdev->code_loading, 171 HDA_DSP_CL_TRIGGER_TIMEOUT); 172 173 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 174 1 << hstream->index, 175 1 << hstream->index); 176 177 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 178 sd_offset, 179 SOF_HDA_SD_CTL_DMA_START | 180 SOF_HDA_CL_DMA_SD_INT_MASK, 181 SOF_HDA_SD_CTL_DMA_START | 182 SOF_HDA_CL_DMA_SD_INT_MASK); 183 184 hstream->running = true; 185 return 0; 186 default: 187 return hda_dsp_stream_trigger(sdev, stream, cmd); 188 } 189 } 190 191 static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev, 192 int tag) 193 { 194 struct hdac_bus *bus = sof_to_bus(sdev); 195 struct hdac_stream *s; 196 197 /* get stream with tag */ 198 list_for_each_entry(s, &bus->stream_list, list) { 199 if (s->direction == SNDRV_PCM_STREAM_PLAYBACK && 200 s->stream_tag == tag) { 201 return stream_to_hdac_ext_stream(s); 202 } 203 } 204 205 return NULL; 206 } 207 208 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 209 struct hdac_ext_stream *stream) 210 { 211 struct hdac_stream *hstream = &stream->hstream; 212 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 213 int ret; 214 215 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0); 216 217 hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK, 218 hstream->stream_tag); 219 hstream->running = 0; 220 hstream->substream = NULL; 221 222 /* reset BDL address */ 223 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 224 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); 225 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 226 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); 227 228 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 229 snd_dma_free_pages(dmab); 230 dmab->area = NULL; 231 hstream->bufsize = 0; 232 hstream->format_val = 0; 233 234 return ret; 235 } 236 237 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream) 238 { 239 unsigned int reg; 240 int ret, status; 241 242 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START); 243 if (ret < 0) { 244 dev_err(sdev->dev, "error: DMA trigger start failed\n"); 245 return ret; 246 } 247 248 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 249 HDA_DSP_SRAM_REG_ROM_STATUS, reg, 250 ((reg & HDA_DSP_ROM_STS_MASK) 251 == HDA_DSP_ROM_FW_ENTERED), 252 HDA_DSP_REG_POLL_INTERVAL_US, 253 HDA_DSP_BASEFW_TIMEOUT_US); 254 255 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP); 256 if (ret < 0) { 257 dev_err(sdev->dev, "error: DMA trigger stop failed\n"); 258 return ret; 259 } 260 261 return status; 262 } 263 264 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 265 { 266 struct snd_sof_pdata *plat_data = sdev->pdata; 267 const struct sof_dev_desc *desc = plat_data->desc; 268 const struct sof_intel_dsp_desc *chip_info; 269 struct hdac_ext_stream *stream; 270 struct firmware stripped_firmware; 271 int ret, ret1, tag, i; 272 273 chip_info = desc->chip_info; 274 275 stripped_firmware.data = plat_data->fw->data; 276 stripped_firmware.size = plat_data->fw->size; 277 278 /* init for booting wait */ 279 init_waitqueue_head(&sdev->boot_wait); 280 sdev->boot_complete = false; 281 282 /* prepare DMA for code loader stream */ 283 tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size, 284 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK); 285 286 if (tag < 0) { 287 dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n", 288 tag); 289 return tag; 290 } 291 292 /* get stream with tag */ 293 stream = get_stream_with_tag(sdev, tag); 294 if (!stream) { 295 dev_err(sdev->dev, 296 "error: could not get stream with stream tag %d\n", 297 tag); 298 ret = -ENODEV; 299 goto err; 300 } 301 302 memcpy(sdev->dmab.area, stripped_firmware.data, 303 stripped_firmware.size); 304 305 /* try ROM init a few times before giving up */ 306 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { 307 ret = cl_dsp_init(sdev, stripped_firmware.data, 308 stripped_firmware.size, tag); 309 310 /* don't retry anymore if successful */ 311 if (!ret) 312 break; 313 314 dev_err(sdev->dev, "error: Error code=0x%x: FW status=0x%x\n", 315 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 316 HDA_DSP_SRAM_REG_ROM_ERROR), 317 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 318 HDA_DSP_SRAM_REG_ROM_STATUS)); 319 dev_err(sdev->dev, "error: iteration %d of Core En/ROM load failed: %d\n", 320 i, ret); 321 } 322 323 if (i == HDA_FW_BOOT_ATTEMPTS) { 324 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", 325 i, ret); 326 goto cleanup; 327 } 328 329 /* 330 * at this point DSP ROM has been initialized and 331 * should be ready for code loading and firmware boot 332 */ 333 ret = cl_copy_fw(sdev, stream); 334 if (!ret) 335 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 336 else 337 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret); 338 339 cleanup: 340 /* 341 * Perform codeloader stream cleanup. 342 * This should be done even if firmware loading fails. 343 */ 344 ret1 = cl_cleanup(sdev, &sdev->dmab, stream); 345 if (ret1 < 0) { 346 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); 347 348 /* set return value to indicate cleanup failure */ 349 ret = ret1; 350 } 351 352 /* 353 * return master core id if both fw copy 354 * and stream clean up are successful 355 */ 356 if (!ret) 357 return chip_info->init_core_mask; 358 359 /* dump dsp registers and disable DSP upon error */ 360 err: 361 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 362 363 /* disable DSP */ 364 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 365 SOF_HDA_REG_PP_PPCTL, 366 SOF_HDA_PPCTL_GPROCEN, 0); 367 return ret; 368 } 369 370 /* pre fw run operations */ 371 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) 372 { 373 /* disable clock gating and power gating */ 374 return hda_dsp_ctrl_clock_power_gating(sdev, false); 375 } 376 377 /* post fw run operations */ 378 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) 379 { 380 /* re-enable clock gating and power gating */ 381 return hda_dsp_ctrl_clock_power_gating(sdev, true); 382 } 383