1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for HDA DSP code loader 16 */ 17 18 #include <linux/firmware.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <sound/sof.h> 22 #include "../ops.h" 23 #include "hda.h" 24 25 #define HDA_FW_BOOT_ATTEMPTS 3 26 #define HDA_CL_STREAM_FORMAT 0x40 27 28 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 29 unsigned int size, struct snd_dma_buffer *dmab, 30 int direction) 31 { 32 struct hdac_ext_stream *dsp_stream; 33 struct hdac_stream *hstream; 34 struct pci_dev *pci = to_pci_dev(sdev->dev); 35 int ret; 36 37 dsp_stream = hda_dsp_stream_get(sdev, direction); 38 39 if (!dsp_stream) { 40 dev_err(sdev->dev, "error: no stream available\n"); 41 return ERR_PTR(-ENODEV); 42 } 43 hstream = &dsp_stream->hstream; 44 hstream->substream = NULL; 45 46 /* allocate DMA buffer */ 47 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); 48 if (ret < 0) { 49 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret); 50 goto error; 51 } 52 53 hstream->period_bytes = 0;/* initialize period_bytes */ 54 hstream->format_val = format; 55 hstream->bufsize = size; 56 57 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 58 ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL); 59 if (ret < 0) { 60 dev_err(sdev->dev, "error: iccmax stream prepare failed: %x\n", ret); 61 goto error; 62 } 63 } else { 64 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL); 65 if (ret < 0) { 66 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret); 67 goto error; 68 } 69 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size); 70 } 71 72 return dsp_stream; 73 74 error: 75 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 76 snd_dma_free_pages(dmab); 77 return ERR_PTR(ret); 78 } 79 80 /* 81 * first boot sequence has some extra steps. core 0 waits for power 82 * status on core 1, so power up core 1 also momentarily, keep it in 83 * reset/stall and then turn it off 84 */ 85 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration) 86 { 87 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 88 const struct sof_intel_dsp_desc *chip = hda->desc; 89 unsigned int status; 90 int ret; 91 int i; 92 93 /* step 1: power up corex */ 94 ret = hda_dsp_core_power_up(sdev, chip->cores_mask); 95 if (ret < 0) { 96 if (iteration == HDA_FW_BOOT_ATTEMPTS) 97 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); 98 goto err; 99 } 100 101 /* DSP is powered up, set all SSPs to slave mode */ 102 for (i = 0; i < chip->ssp_count; i++) { 103 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 104 chip->ssp_base_offset 105 + i * SSP_DEV_MEM_SIZE 106 + SSP_SSC1_OFFSET, 107 SSP_SET_SLAVE, 108 SSP_SET_SLAVE); 109 } 110 111 /* step 2: purge FW request */ 112 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, 113 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW | 114 ((stream_tag - 1) << 9))); 115 116 /* step 3: unset core 0 reset state & unstall/run core 0 */ 117 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0)); 118 if (ret < 0) { 119 if (iteration == HDA_FW_BOOT_ATTEMPTS) 120 dev_err(sdev->dev, 121 "error: dsp core start failed %d\n", ret); 122 ret = -EIO; 123 goto err; 124 } 125 126 /* step 4: wait for IPC DONE bit from ROM */ 127 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 128 chip->ipc_ack, status, 129 ((status & chip->ipc_ack_mask) 130 == chip->ipc_ack_mask), 131 HDA_DSP_REG_POLL_INTERVAL_US, 132 HDA_DSP_INIT_TIMEOUT_US); 133 134 if (ret < 0) { 135 if (iteration == HDA_FW_BOOT_ATTEMPTS) 136 dev_err(sdev->dev, 137 "error: %s: timeout for HIPCIE done\n", 138 __func__); 139 goto err; 140 } 141 142 /* set DONE bit to clear the reply IPC message */ 143 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 144 chip->ipc_ack, 145 chip->ipc_ack_mask, 146 chip->ipc_ack_mask); 147 148 /* step 5: power down corex */ 149 ret = hda_dsp_core_power_down(sdev, 150 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0))); 151 if (ret < 0) { 152 if (iteration == HDA_FW_BOOT_ATTEMPTS) 153 dev_err(sdev->dev, 154 "error: dsp core x power down failed\n"); 155 goto err; 156 } 157 158 /* step 6: enable IPC interrupts */ 159 hda_dsp_ipc_int_enable(sdev); 160 161 /* step 7: wait for ROM init */ 162 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 163 HDA_DSP_SRAM_REG_ROM_STATUS, status, 164 ((status & HDA_DSP_ROM_STS_MASK) 165 == HDA_DSP_ROM_INIT), 166 HDA_DSP_REG_POLL_INTERVAL_US, 167 chip->rom_init_timeout * 168 USEC_PER_MSEC); 169 if (!ret) 170 return 0; 171 172 if (iteration == HDA_FW_BOOT_ATTEMPTS) 173 dev_err(sdev->dev, 174 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 175 __func__); 176 177 err: 178 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 179 hda_dsp_core_reset_power_down(sdev, chip->cores_mask); 180 181 return ret; 182 } 183 184 static int cl_trigger(struct snd_sof_dev *sdev, 185 struct hdac_ext_stream *stream, int cmd) 186 { 187 struct hdac_stream *hstream = &stream->hstream; 188 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 189 190 /* code loader is special case that reuses stream ops */ 191 switch (cmd) { 192 case SNDRV_PCM_TRIGGER_START: 193 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 194 1 << hstream->index, 195 1 << hstream->index); 196 197 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 198 sd_offset, 199 SOF_HDA_SD_CTL_DMA_START | 200 SOF_HDA_CL_DMA_SD_INT_MASK, 201 SOF_HDA_SD_CTL_DMA_START | 202 SOF_HDA_CL_DMA_SD_INT_MASK); 203 204 hstream->running = true; 205 return 0; 206 default: 207 return hda_dsp_stream_trigger(sdev, stream, cmd); 208 } 209 } 210 211 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 212 struct hdac_ext_stream *stream) 213 { 214 struct hdac_stream *hstream = &stream->hstream; 215 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 216 int ret = 0; 217 218 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 219 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0); 220 else 221 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 222 SOF_HDA_SD_CTL_DMA_START, 0); 223 224 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag); 225 hstream->running = 0; 226 hstream->substream = NULL; 227 228 /* reset BDL address */ 229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 230 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); 231 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 232 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); 233 234 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 235 snd_dma_free_pages(dmab); 236 dmab->area = NULL; 237 hstream->bufsize = 0; 238 hstream->format_val = 0; 239 240 return ret; 241 } 242 243 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream) 244 { 245 unsigned int reg; 246 int ret, status; 247 248 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START); 249 if (ret < 0) { 250 dev_err(sdev->dev, "error: DMA trigger start failed\n"); 251 return ret; 252 } 253 254 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 255 HDA_DSP_SRAM_REG_ROM_STATUS, reg, 256 ((reg & HDA_DSP_ROM_STS_MASK) 257 == HDA_DSP_ROM_FW_ENTERED), 258 HDA_DSP_REG_POLL_INTERVAL_US, 259 HDA_DSP_BASEFW_TIMEOUT_US); 260 261 /* 262 * even in case of errors we still need to stop the DMAs, 263 * but we return the initial error should the DMA stop also fail 264 */ 265 266 if (status < 0) { 267 dev_err(sdev->dev, 268 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 269 __func__); 270 } 271 272 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP); 273 if (ret < 0) { 274 dev_err(sdev->dev, "error: DMA trigger stop failed\n"); 275 if (!status) 276 status = ret; 277 } 278 279 return status; 280 } 281 282 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) 283 { 284 struct snd_sof_pdata *plat_data = sdev->pdata; 285 struct hdac_ext_stream *iccmax_stream; 286 struct hdac_bus *bus = sof_to_bus(sdev); 287 struct firmware stripped_firmware; 288 int ret, ret1; 289 u8 original_gb; 290 291 /* save the original LTRP guardband value */ 292 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK; 293 294 if (plat_data->fw->size <= plat_data->fw_offset) { 295 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 296 return -EINVAL; 297 } 298 299 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 300 301 /* prepare capture stream for ICCMAX */ 302 iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 303 &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE); 304 if (IS_ERR(iccmax_stream)) { 305 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n"); 306 return PTR_ERR(iccmax_stream); 307 } 308 309 ret = hda_dsp_cl_boot_firmware(sdev); 310 311 /* 312 * Perform iccmax stream cleanup. This should be done even if firmware loading fails. 313 * If the cleanup also fails, we return the initial error 314 */ 315 ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream); 316 if (ret1 < 0) { 317 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n"); 318 319 /* set return value to indicate cleanup failure */ 320 if (!ret) 321 ret = ret1; 322 } 323 324 /* restore the original guardband value after FW boot */ 325 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb); 326 327 return ret; 328 } 329 330 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 331 { 332 struct snd_sof_pdata *plat_data = sdev->pdata; 333 const struct sof_dev_desc *desc = plat_data->desc; 334 const struct sof_intel_dsp_desc *chip_info; 335 struct hdac_ext_stream *stream; 336 struct firmware stripped_firmware; 337 int ret, ret1, i; 338 339 chip_info = desc->chip_info; 340 341 if (plat_data->fw->size <= plat_data->fw_offset) { 342 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 343 return -EINVAL; 344 } 345 346 stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset; 347 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 348 349 /* init for booting wait */ 350 init_waitqueue_head(&sdev->boot_wait); 351 352 /* prepare DMA for code loader stream */ 353 stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 354 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK); 355 if (IS_ERR(stream)) { 356 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n"); 357 return PTR_ERR(stream); 358 } 359 360 memcpy(sdev->dmab.area, stripped_firmware.data, 361 stripped_firmware.size); 362 363 /* try ROM init a few times before giving up */ 364 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { 365 dev_dbg(sdev->dev, 366 "Attempting iteration %d of Core En/ROM load...\n", i); 367 368 ret = cl_dsp_init(sdev, stream->hstream.stream_tag, i + 1); 369 370 /* don't retry anymore if successful */ 371 if (!ret) 372 break; 373 } 374 375 if (i == HDA_FW_BOOT_ATTEMPTS) { 376 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", 377 i, ret); 378 dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n", 379 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 380 HDA_DSP_SRAM_REG_ROM_ERROR), 381 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 382 HDA_DSP_SRAM_REG_ROM_STATUS)); 383 goto cleanup; 384 } 385 386 /* 387 * When a SoundWire link is in clock stop state, a Slave 388 * device may trigger in-band wakes for events such as jack 389 * insertion or acoustic event detection. This event will lead 390 * to a WAKEEN interrupt, handled by the PCI device and routed 391 * to PME if the PCI device is in D3. The resume function in 392 * audio PCI driver will be invoked by ACPI for PME event and 393 * initialize the device and process WAKEEN interrupt. 394 * 395 * The WAKEEN interrupt should be processed ASAP to prevent an 396 * interrupt flood, otherwise other interrupts, such IPC, 397 * cannot work normally. The WAKEEN is handled after the ROM 398 * is initialized successfully, which ensures power rails are 399 * enabled before accessing the SoundWire SHIM registers 400 */ 401 if (!sdev->first_boot) 402 hda_sdw_process_wakeen(sdev); 403 404 /* 405 * at this point DSP ROM has been initialized and 406 * should be ready for code loading and firmware boot 407 */ 408 ret = cl_copy_fw(sdev, stream); 409 if (!ret) 410 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 411 else 412 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret); 413 414 cleanup: 415 /* 416 * Perform codeloader stream cleanup. 417 * This should be done even if firmware loading fails. 418 * If the cleanup also fails, we return the initial error 419 */ 420 ret1 = cl_cleanup(sdev, &sdev->dmab, stream); 421 if (ret1 < 0) { 422 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); 423 424 /* set return value to indicate cleanup failure */ 425 if (!ret) 426 ret = ret1; 427 } 428 429 /* 430 * return master core id if both fw copy 431 * and stream clean up are successful 432 */ 433 if (!ret) 434 return chip_info->init_core_mask; 435 436 /* dump dsp registers and disable DSP upon error */ 437 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); 438 439 /* disable DSP */ 440 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 441 SOF_HDA_REG_PP_PPCTL, 442 SOF_HDA_PPCTL_GPROCEN, 0); 443 return ret; 444 } 445 446 /* pre fw run operations */ 447 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) 448 { 449 /* disable clock gating and power gating */ 450 return hda_dsp_ctrl_clock_power_gating(sdev, false); 451 } 452 453 /* post fw run operations */ 454 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) 455 { 456 int ret; 457 458 if (sdev->first_boot) { 459 ret = hda_sdw_startup(sdev); 460 if (ret < 0) { 461 dev_err(sdev->dev, 462 "error: could not startup SoundWire links\n"); 463 return ret; 464 } 465 } 466 467 hda_sdw_int_enable(sdev, true); 468 469 /* re-enable clock gating and power gating */ 470 return hda_dsp_ctrl_clock_power_gating(sdev, true); 471 } 472