1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018-2022 Intel Corporation. All rights reserved. 7 // 8 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/fs.h> 14 #include <linux/interrupt.h> 15 #include <linux/mm.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <sound/hdaudio_ext.h> 21 #include <sound/sof.h> 22 #include <sound/pcm_params.h> 23 24 #include "../sof-priv.h" 25 #include "../ops.h" 26 #include "hda.h" 27 28 #define HDA_SKL_WAIT_TIMEOUT 500 /* 500 msec */ 29 #define HDA_SKL_CLDMA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 30 31 /* Stream Reset */ 32 #define HDA_CL_SD_CTL_SRST_SHIFT 0 33 #define HDA_CL_SD_CTL_SRST(x) (((x) & 0x1) << \ 34 HDA_CL_SD_CTL_SRST_SHIFT) 35 36 /* Stream Run */ 37 #define HDA_CL_SD_CTL_RUN_SHIFT 1 38 #define HDA_CL_SD_CTL_RUN(x) (((x) & 0x1) << \ 39 HDA_CL_SD_CTL_RUN_SHIFT) 40 41 /* Interrupt On Completion Enable */ 42 #define HDA_CL_SD_CTL_IOCE_SHIFT 2 43 #define HDA_CL_SD_CTL_IOCE(x) (((x) & 0x1) << \ 44 HDA_CL_SD_CTL_IOCE_SHIFT) 45 46 /* FIFO Error Interrupt Enable */ 47 #define HDA_CL_SD_CTL_FEIE_SHIFT 3 48 #define HDA_CL_SD_CTL_FEIE(x) (((x) & 0x1) << \ 49 HDA_CL_SD_CTL_FEIE_SHIFT) 50 51 /* Descriptor Error Interrupt Enable */ 52 #define HDA_CL_SD_CTL_DEIE_SHIFT 4 53 #define HDA_CL_SD_CTL_DEIE(x) (((x) & 0x1) << \ 54 HDA_CL_SD_CTL_DEIE_SHIFT) 55 56 /* FIFO Limit Change */ 57 #define HDA_CL_SD_CTL_FIFOLC_SHIFT 5 58 #define HDA_CL_SD_CTL_FIFOLC(x) (((x) & 0x1) << \ 59 HDA_CL_SD_CTL_FIFOLC_SHIFT) 60 61 /* Stripe Control */ 62 #define HDA_CL_SD_CTL_STRIPE_SHIFT 16 63 #define HDA_CL_SD_CTL_STRIPE(x) (((x) & 0x3) << \ 64 HDA_CL_SD_CTL_STRIPE_SHIFT) 65 66 /* Traffic Priority */ 67 #define HDA_CL_SD_CTL_TP_SHIFT 18 68 #define HDA_CL_SD_CTL_TP(x) (((x) & 0x1) << \ 69 HDA_CL_SD_CTL_TP_SHIFT) 70 71 /* Bidirectional Direction Control */ 72 #define HDA_CL_SD_CTL_DIR_SHIFT 19 73 #define HDA_CL_SD_CTL_DIR(x) (((x) & 0x1) << \ 74 HDA_CL_SD_CTL_DIR_SHIFT) 75 76 /* Stream Number */ 77 #define HDA_CL_SD_CTL_STRM_SHIFT 20 78 #define HDA_CL_SD_CTL_STRM(x) (((x) & 0xf) << \ 79 HDA_CL_SD_CTL_STRM_SHIFT) 80 81 #define HDA_CL_SD_CTL_INT(x) \ 82 (HDA_CL_SD_CTL_IOCE(x) | \ 83 HDA_CL_SD_CTL_FEIE(x) | \ 84 HDA_CL_SD_CTL_DEIE(x)) 85 86 #define HDA_CL_SD_CTL_INT_MASK \ 87 (HDA_CL_SD_CTL_IOCE(1) | \ 88 HDA_CL_SD_CTL_FEIE(1) | \ 89 HDA_CL_SD_CTL_DEIE(1)) 90 91 #define DMA_ADDRESS_128_BITS_ALIGNMENT 7 92 #define BDL_ALIGN(x) ((x) >> DMA_ADDRESS_128_BITS_ALIGNMENT) 93 94 /* Buffer Descriptor List Lower Base Address */ 95 #define HDA_CL_SD_BDLPLBA_SHIFT 7 96 #define HDA_CL_SD_BDLPLBA_MASK GENMASK(31, 7) 97 #define HDA_CL_SD_BDLPLBA(x) \ 98 ((BDL_ALIGN(lower_32_bits(x)) << HDA_CL_SD_BDLPLBA_SHIFT) & \ 99 HDA_CL_SD_BDLPLBA_MASK) 100 101 /* Buffer Descriptor List Upper Base Address */ 102 #define HDA_CL_SD_BDLPUBA(x) \ 103 (upper_32_bits(x)) 104 105 /* Software Position in Buffer Enable */ 106 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0 107 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK \ 108 (1 << HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) 109 110 #define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(x) \ 111 (((x) << HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & \ 112 HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK) 113 114 #define HDA_CL_DMA_SD_INT_COMPLETE 0x4 115 116 static int cl_skl_cldma_setup_bdle(struct snd_sof_dev *sdev, 117 struct snd_dma_buffer *dmab_data, 118 __le32 **bdlp, int size, int with_ioc) 119 { 120 phys_addr_t addr = virt_to_phys(dmab_data->area); 121 __le32 *bdl = *bdlp; 122 123 /* 124 * This code is simplified by using one fragment of physical memory and assuming 125 * all the code fits. This could be improved with scatter-gather but the firmware 126 * size is limited by DSP memory anyways 127 */ 128 bdl[0] = cpu_to_le32(lower_32_bits(addr)); 129 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 130 bdl[2] = cpu_to_le32(size); 131 bdl[3] = (!with_ioc) ? 0 : cpu_to_le32(0x01); 132 133 return 1; /* one fragment */ 134 } 135 136 static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable) 137 { 138 int sd_offset = SOF_HDA_ADSP_LOADER_BASE; 139 unsigned char val; 140 int retries; 141 u32 run = enable ? 0x1 : 0; 142 143 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 144 sd_offset + SOF_HDA_ADSP_REG_SD_CTL, 145 HDA_CL_SD_CTL_RUN(1), HDA_CL_SD_CTL_RUN(run)); 146 147 retries = 300; 148 do { 149 udelay(3); 150 151 /* waiting for hardware to report the stream Run bit set */ 152 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 153 sd_offset + SOF_HDA_ADSP_REG_SD_CTL); 154 val &= HDA_CL_SD_CTL_RUN(1); 155 if (enable && val) 156 break; 157 else if (!enable && !val) 158 break; 159 } while (--retries); 160 161 if (retries == 0) 162 dev_err(sdev->dev, "%s: failed to set Run bit=%d enable=%d\n", 163 __func__, val, enable); 164 } 165 166 static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev) 167 { 168 int sd_offset = SOF_HDA_ADSP_LOADER_BASE; 169 170 /* make sure Run bit is cleared before setting stream register */ 171 cl_skl_cldma_stream_run(sdev, 0); 172 173 /* Disable the Interrupt On Completion, FIFO Error Interrupt, 174 * Descriptor Error Interrupt and set the cldma stream number to 0. 175 */ 176 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 177 sd_offset + SOF_HDA_ADSP_REG_SD_CTL, 178 HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(0)); 179 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 180 sd_offset + SOF_HDA_ADSP_REG_SD_CTL, 181 HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(0)); 182 183 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 184 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, HDA_CL_SD_BDLPLBA(0)); 185 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 186 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0); 187 188 /* Set the Cyclic Buffer Length to 0. */ 189 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 190 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 0); 191 /* Set the Last Valid Index. */ 192 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 193 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 0); 194 } 195 196 static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev, 197 unsigned int size, bool enable) 198 { 199 int sd_offset = SOF_DSP_REG_CL_SPBFIFO; 200 201 if (enable) 202 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 203 sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, 204 HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, 205 HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(1)); 206 207 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 208 sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB, size); 209 } 210 211 static void cl_skl_cldma_set_intr(struct snd_sof_dev *sdev, bool enable) 212 { 213 u32 val = enable ? HDA_DSP_ADSPIC_CL_DMA : 0; 214 215 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 216 HDA_DSP_ADSPIC_CL_DMA, val); 217 } 218 219 static void cl_skl_cldma_cleanup_spb(struct snd_sof_dev *sdev) 220 { 221 int sd_offset = SOF_DSP_REG_CL_SPBFIFO; 222 223 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 224 sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, 225 HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, 226 HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(0)); 227 228 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 229 sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB, 0); 230 } 231 232 static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev, 233 struct snd_dma_buffer *dmab_bdl, 234 unsigned int max_size, u32 count) 235 { 236 int sd_offset = SOF_HDA_ADSP_LOADER_BASE; 237 238 /* Clear the stream first and then set it. */ 239 cl_skl_cldma_stream_clear(sdev); 240 241 /* setting the stream register */ 242 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 243 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 244 HDA_CL_SD_BDLPLBA(dmab_bdl->addr)); 245 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 246 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 247 HDA_CL_SD_BDLPUBA(dmab_bdl->addr)); 248 249 /* Set the Cyclic Buffer Length. */ 250 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 251 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, max_size); 252 /* Set the Last Valid Index. */ 253 snd_sof_dsp_write(sdev, HDA_DSP_BAR, 254 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, count - 1); 255 256 /* Set the Interrupt On Completion, FIFO Error Interrupt, 257 * Descriptor Error Interrupt and the cldma stream number. 258 */ 259 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 260 sd_offset + SOF_HDA_ADSP_REG_SD_CTL, 261 HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(1)); 262 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 263 sd_offset + SOF_HDA_ADSP_REG_SD_CTL, 264 HDA_CL_SD_CTL_STRM(0xf), 265 HDA_CL_SD_CTL_STRM(1)); 266 } 267 268 static int cl_stream_prepare_skl(struct snd_sof_dev *sdev, 269 struct snd_dma_buffer *dmab, 270 struct snd_dma_buffer *dmab_bdl) 271 272 { 273 unsigned int bufsize = HDA_SKL_CLDMA_MAX_BUFFER_SIZE; 274 __le32 *bdl; 275 int frags; 276 int ret; 277 278 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, sdev->dev, bufsize, dmab); 279 if (ret < 0) { 280 dev_err(sdev->dev, "%s: failed to alloc fw buffer: %x\n", __func__, ret); 281 return ret; 282 } 283 284 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, sdev->dev, bufsize, dmab_bdl); 285 if (ret < 0) { 286 dev_err(sdev->dev, "%s: failed to alloc blde: %x\n", __func__, ret); 287 snd_dma_free_pages(dmab); 288 return ret; 289 } 290 291 bdl = (__le32 *)dmab_bdl->area; 292 frags = cl_skl_cldma_setup_bdle(sdev, dmab, &bdl, bufsize, 1); 293 cl_skl_cldma_setup_controller(sdev, dmab_bdl, bufsize, frags); 294 295 return ret; 296 } 297 298 static void cl_cleanup_skl(struct snd_sof_dev *sdev, 299 struct snd_dma_buffer *dmab, 300 struct snd_dma_buffer *dmab_bdl) 301 { 302 cl_skl_cldma_cleanup_spb(sdev); 303 cl_skl_cldma_stream_clear(sdev); 304 snd_dma_free_pages(dmab); 305 snd_dma_free_pages(dmab_bdl); 306 } 307 308 static int cl_dsp_init_skl(struct snd_sof_dev *sdev, 309 struct snd_dma_buffer *dmab, 310 struct snd_dma_buffer *dmab_bdl) 311 { 312 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 313 const struct sof_intel_dsp_desc *chip = hda->desc; 314 unsigned int status; 315 u32 flags; 316 int ret; 317 318 /* check if the init_core is already enabled, if yes, reset and make it run, 319 * if not, powerdown and enable it again. 320 */ 321 if (hda_dsp_core_is_enabled(sdev, chip->init_core_mask)) { 322 /* if enabled, reset it, and run the init_core. */ 323 ret = hda_dsp_core_stall_reset(sdev, chip->init_core_mask); 324 if (ret < 0) 325 goto err; 326 327 ret = hda_dsp_core_run(sdev, chip->init_core_mask); 328 if (ret < 0) { 329 dev_err(sdev->dev, "%s: dsp core start failed %d\n", __func__, ret); 330 goto err; 331 } 332 } else { 333 /* if not enabled, power down it first and then powerup and run 334 * the init_core. 335 */ 336 ret = hda_dsp_core_reset_power_down(sdev, chip->init_core_mask); 337 if (ret < 0) { 338 dev_err(sdev->dev, "%s: dsp core0 disable fail: %d\n", __func__, ret); 339 goto err; 340 } 341 ret = hda_dsp_enable_core(sdev, chip->init_core_mask); 342 if (ret < 0) { 343 dev_err(sdev->dev, "%s: dsp core0 enable fail: %d\n", __func__, ret); 344 goto err; 345 } 346 } 347 348 /* prepare DMA for code loader stream */ 349 ret = cl_stream_prepare_skl(sdev, dmab, dmab_bdl); 350 if (ret < 0) { 351 dev_err(sdev->dev, "%s: dma prepare fw loading err: %x\n", __func__, ret); 352 return ret; 353 } 354 355 /* enable the interrupt */ 356 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 357 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 358 359 /* enable IPC DONE interrupt */ 360 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 361 HDA_DSP_REG_HIPCCTL_DONE, 362 HDA_DSP_REG_HIPCCTL_DONE); 363 364 /* enable IPC BUSY interrupt */ 365 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 366 HDA_DSP_REG_HIPCCTL_BUSY, 367 HDA_DSP_REG_HIPCCTL_BUSY); 368 369 /* polling the ROM init status information. */ 370 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 371 chip->rom_status_reg, status, 372 (FSR_TO_STATE_CODE(status) 373 == FSR_STATE_INIT_DONE), 374 HDA_DSP_REG_POLL_INTERVAL_US, 375 chip->rom_init_timeout * 376 USEC_PER_MSEC); 377 if (ret < 0) 378 goto err; 379 380 return ret; 381 382 err: 383 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX; 384 385 snd_sof_dsp_dbg_dump(sdev, "Boot failed\n", flags); 386 cl_cleanup_skl(sdev, dmab, dmab_bdl); 387 hda_dsp_core_reset_power_down(sdev, chip->init_core_mask); 388 return ret; 389 } 390 391 static void cl_skl_cldma_fill_buffer(struct snd_sof_dev *sdev, 392 struct snd_dma_buffer *dmab, 393 unsigned int bufsize, 394 unsigned int copysize, 395 const void *curr_pos, 396 bool intr_enable) 397 { 398 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 399 400 /* copy the image into the buffer with the maximum buffer size. */ 401 unsigned int size = (bufsize == copysize) ? bufsize : copysize; 402 403 memcpy(dmab->area, curr_pos, size); 404 405 /* Set the wait condition for every load. */ 406 hda->code_loading = 1; 407 408 /* Set the interrupt. */ 409 if (intr_enable) 410 cl_skl_cldma_set_intr(sdev, true); 411 412 /* Set the SPB. */ 413 cl_skl_cldma_setup_spb(sdev, size, true); 414 415 /* Trigger the code loading stream. */ 416 cl_skl_cldma_stream_run(sdev, true); 417 } 418 419 static int cl_skl_cldma_wait_interruptible(struct snd_sof_dev *sdev, 420 bool intr_wait) 421 { 422 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 423 const struct sof_intel_dsp_desc *chip = hda->desc; 424 int sd_offset = SOF_HDA_ADSP_LOADER_BASE; 425 u8 cl_dma_intr_status; 426 427 /* 428 * Wait for CLDMA interrupt to inform the binary segment transfer is 429 * complete. 430 */ 431 if (!wait_event_timeout(hda->waitq, !hda->code_loading, 432 msecs_to_jiffies(HDA_SKL_WAIT_TIMEOUT))) { 433 dev_err(sdev->dev, "cldma copy timeout\n"); 434 dev_err(sdev->dev, "ROM code=%#x: FW status=%#x\n", 435 snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_ROM_ERROR), 436 snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg)); 437 return -EIO; 438 } 439 440 /* now check DMA interrupt status */ 441 cl_dma_intr_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 442 sd_offset + SOF_HDA_ADSP_REG_SD_STS); 443 444 if (!(cl_dma_intr_status & HDA_CL_DMA_SD_INT_COMPLETE)) { 445 dev_err(sdev->dev, "cldma copy failed\n"); 446 return -EIO; 447 } 448 449 dev_dbg(sdev->dev, "cldma buffer copy complete\n"); 450 return 0; 451 } 452 453 static int 454 cl_skl_cldma_copy_to_buf(struct snd_sof_dev *sdev, 455 struct snd_dma_buffer *dmab, 456 const void *bin, 457 u32 total_size, u32 bufsize) 458 { 459 unsigned int bytes_left = total_size; 460 const void *curr_pos = bin; 461 int ret; 462 463 if (total_size <= 0) 464 return -EINVAL; 465 466 while (bytes_left > 0) { 467 if (bytes_left > bufsize) { 468 dev_dbg(sdev->dev, "cldma copy %#x bytes\n", bufsize); 469 470 cl_skl_cldma_fill_buffer(sdev, dmab, bufsize, bufsize, curr_pos, true); 471 472 ret = cl_skl_cldma_wait_interruptible(sdev, false); 473 if (ret < 0) { 474 dev_err(sdev->dev, "%s: fw failed to load. %#x bytes remaining\n", 475 __func__, bytes_left); 476 return ret; 477 } 478 479 bytes_left -= bufsize; 480 curr_pos += bufsize; 481 } else { 482 dev_dbg(sdev->dev, "cldma copy %#x bytes\n", bytes_left); 483 484 cl_skl_cldma_set_intr(sdev, false); 485 cl_skl_cldma_fill_buffer(sdev, dmab, bufsize, bytes_left, curr_pos, false); 486 return 0; 487 } 488 } 489 490 return bytes_left; 491 } 492 493 static int cl_copy_fw_skl(struct snd_sof_dev *sdev, 494 struct snd_dma_buffer *dmab) 495 496 { 497 const struct firmware *fw = sdev->basefw.fw; 498 struct firmware stripped_firmware; 499 unsigned int bufsize = HDA_SKL_CLDMA_MAX_BUFFER_SIZE; 500 int ret; 501 502 stripped_firmware.data = fw->data + sdev->basefw.payload_offset; 503 stripped_firmware.size = fw->size - sdev->basefw.payload_offset; 504 505 dev_dbg(sdev->dev, "firmware size: %#zx buffer size %#x\n", fw->size, bufsize); 506 507 ret = cl_skl_cldma_copy_to_buf(sdev, dmab, stripped_firmware.data, 508 stripped_firmware.size, bufsize); 509 if (ret < 0) 510 dev_err(sdev->dev, "%s: fw copy failed %d\n", __func__, ret); 511 512 return ret; 513 } 514 515 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev) 516 { 517 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 518 const struct sof_intel_dsp_desc *chip = hda->desc; 519 struct snd_dma_buffer dmab_bdl; 520 struct snd_dma_buffer dmab; 521 unsigned int reg; 522 u32 flags; 523 int ret; 524 525 ret = cl_dsp_init_skl(sdev, &dmab, &dmab_bdl); 526 527 /* retry enabling core and ROM load. seemed to help */ 528 if (ret < 0) { 529 ret = cl_dsp_init_skl(sdev, &dmab, &dmab_bdl); 530 if (ret < 0) { 531 dev_err(sdev->dev, "Error code=%#x: FW status=%#x\n", 532 snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_ROM_ERROR), 533 snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg)); 534 dev_err(sdev->dev, "Core En/ROM load fail:%d\n", ret); 535 return ret; 536 } 537 } 538 539 dev_dbg(sdev->dev, "ROM init successful\n"); 540 541 /* at this point DSP ROM has been initialized and should be ready for 542 * code loading and firmware boot 543 */ 544 ret = cl_copy_fw_skl(sdev, &dmab); 545 if (ret < 0) { 546 dev_err(sdev->dev, "%s: load firmware failed : %d\n", __func__, ret); 547 goto err; 548 } 549 550 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 551 chip->rom_status_reg, reg, 552 (FSR_TO_STATE_CODE(reg) 553 == FSR_STATE_ROM_BASEFW_ENTERED), 554 HDA_DSP_REG_POLL_INTERVAL_US, 555 HDA_DSP_BASEFW_TIMEOUT_US); 556 557 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 558 559 cl_skl_cldma_stream_run(sdev, false); 560 cl_cleanup_skl(sdev, &dmab, &dmab_bdl); 561 562 if (!ret) 563 return chip->init_core_mask; 564 565 return ret; 566 567 err: 568 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX; 569 570 snd_sof_dsp_dbg_dump(sdev, "Boot failed\n", flags); 571 572 /* power down DSP */ 573 hda_dsp_core_reset_power_down(sdev, chip->init_core_mask); 574 cl_skl_cldma_stream_run(sdev, false); 575 cl_cleanup_skl(sdev, &dmab, &dmab_bdl); 576 577 dev_err(sdev->dev, "%s: load fw failed err: %d\n", __func__, ret); 578 return ret; 579 } 580