1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <trace/events/sof_intel.h> 22 #include "../sof-audio.h" 23 #include "../ops.h" 24 #include "hda.h" 25 #include "hda-ipc.h" 26 27 static bool hda_enable_trace_D0I3_S0; 28 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 29 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 30 MODULE_PARM_DESC(enable_trace_D0I3_S0, 31 "SOF HDA enable trace when the DSP is in D0I3 in S0"); 32 #endif 33 34 /* 35 * DSP Core control. 36 */ 37 38 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 39 { 40 u32 adspcs; 41 u32 reset; 42 int ret; 43 44 /* set reset bits for cores */ 45 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 46 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 47 HDA_DSP_REG_ADSPCS, 48 reset, reset); 49 50 /* poll with timeout to check if operation successful */ 51 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 52 HDA_DSP_REG_ADSPCS, adspcs, 53 ((adspcs & reset) == reset), 54 HDA_DSP_REG_POLL_INTERVAL_US, 55 HDA_DSP_RESET_TIMEOUT_US); 56 if (ret < 0) { 57 dev_err(sdev->dev, 58 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 59 __func__); 60 return ret; 61 } 62 63 /* has core entered reset ? */ 64 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 65 HDA_DSP_REG_ADSPCS); 66 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 67 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 68 dev_err(sdev->dev, 69 "error: reset enter failed: core_mask %x adspcs 0x%x\n", 70 core_mask, adspcs); 71 ret = -EIO; 72 } 73 74 return ret; 75 } 76 77 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 78 { 79 unsigned int crst; 80 u32 adspcs; 81 int ret; 82 83 /* clear reset bits for cores */ 84 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 85 HDA_DSP_REG_ADSPCS, 86 HDA_DSP_ADSPCS_CRST_MASK(core_mask), 87 0); 88 89 /* poll with timeout to check if operation successful */ 90 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 91 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 92 HDA_DSP_REG_ADSPCS, adspcs, 93 !(adspcs & crst), 94 HDA_DSP_REG_POLL_INTERVAL_US, 95 HDA_DSP_RESET_TIMEOUT_US); 96 97 if (ret < 0) { 98 dev_err(sdev->dev, 99 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 100 __func__); 101 return ret; 102 } 103 104 /* has core left reset ? */ 105 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 106 HDA_DSP_REG_ADSPCS); 107 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 108 dev_err(sdev->dev, 109 "error: reset leave failed: core_mask %x adspcs 0x%x\n", 110 core_mask, adspcs); 111 ret = -EIO; 112 } 113 114 return ret; 115 } 116 117 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 118 { 119 /* stall core */ 120 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 121 HDA_DSP_REG_ADSPCS, 122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 123 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 124 125 /* set reset state */ 126 return hda_dsp_core_reset_enter(sdev, core_mask); 127 } 128 129 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask) 130 { 131 int val; 132 bool is_enable; 133 134 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 135 136 #define MASK_IS_EQUAL(v, m, field) ({ \ 137 u32 _m = field(m); \ 138 ((v) & _m) == _m; \ 139 }) 140 141 is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) && 142 MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) && 143 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 144 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 145 146 #undef MASK_IS_EQUAL 147 148 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 149 is_enable, core_mask); 150 151 return is_enable; 152 } 153 154 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 155 { 156 int ret; 157 158 /* leave reset state */ 159 ret = hda_dsp_core_reset_leave(sdev, core_mask); 160 if (ret < 0) 161 return ret; 162 163 /* run core */ 164 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 165 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 166 HDA_DSP_REG_ADSPCS, 167 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 168 0); 169 170 /* is core now running ? */ 171 if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 172 hda_dsp_core_stall_reset(sdev, core_mask); 173 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 174 core_mask); 175 ret = -EIO; 176 } 177 178 return ret; 179 } 180 181 /* 182 * Power Management. 183 */ 184 185 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 186 { 187 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 188 const struct sof_intel_dsp_desc *chip = hda->desc; 189 unsigned int cpa; 190 u32 adspcs; 191 int ret; 192 193 /* restrict core_mask to host managed cores mask */ 194 core_mask &= chip->host_managed_cores_mask; 195 /* return if core_mask is not valid */ 196 if (!core_mask) 197 return 0; 198 199 /* update bits */ 200 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 201 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 202 HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 203 204 /* poll with timeout to check if operation successful */ 205 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 206 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 207 HDA_DSP_REG_ADSPCS, adspcs, 208 (adspcs & cpa) == cpa, 209 HDA_DSP_REG_POLL_INTERVAL_US, 210 HDA_DSP_RESET_TIMEOUT_US); 211 if (ret < 0) { 212 dev_err(sdev->dev, 213 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 214 __func__); 215 return ret; 216 } 217 218 /* did core power up ? */ 219 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 220 HDA_DSP_REG_ADSPCS); 221 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 222 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 223 dev_err(sdev->dev, 224 "error: power up core failed core_mask %xadspcs 0x%x\n", 225 core_mask, adspcs); 226 ret = -EIO; 227 } 228 229 return ret; 230 } 231 232 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 233 { 234 u32 adspcs; 235 int ret; 236 237 /* update bits */ 238 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 239 HDA_DSP_REG_ADSPCS, 240 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 241 242 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 243 HDA_DSP_REG_ADSPCS, adspcs, 244 !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)), 245 HDA_DSP_REG_POLL_INTERVAL_US, 246 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 247 if (ret < 0) 248 dev_err(sdev->dev, 249 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 250 __func__); 251 252 return ret; 253 } 254 255 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 256 { 257 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 258 const struct sof_intel_dsp_desc *chip = hda->desc; 259 int ret; 260 261 /* restrict core_mask to host managed cores mask */ 262 core_mask &= chip->host_managed_cores_mask; 263 264 /* return if core_mask is not valid or cores are already enabled */ 265 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask)) 266 return 0; 267 268 /* power up */ 269 ret = hda_dsp_core_power_up(sdev, core_mask); 270 if (ret < 0) { 271 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 272 core_mask); 273 return ret; 274 } 275 276 return hda_dsp_core_run(sdev, core_mask); 277 } 278 279 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 280 unsigned int core_mask) 281 { 282 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 283 const struct sof_intel_dsp_desc *chip = hda->desc; 284 int ret; 285 286 /* restrict core_mask to host managed cores mask */ 287 core_mask &= chip->host_managed_cores_mask; 288 289 /* return if core_mask is not valid */ 290 if (!core_mask) 291 return 0; 292 293 /* place core in reset prior to power down */ 294 ret = hda_dsp_core_stall_reset(sdev, core_mask); 295 if (ret < 0) { 296 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 297 core_mask); 298 return ret; 299 } 300 301 /* power down core */ 302 ret = hda_dsp_core_power_down(sdev, core_mask); 303 if (ret < 0) { 304 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 305 core_mask, ret); 306 return ret; 307 } 308 309 /* make sure we are in OFF state */ 310 if (hda_dsp_core_is_enabled(sdev, core_mask)) { 311 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 312 core_mask, ret); 313 ret = -EIO; 314 } 315 316 return ret; 317 } 318 319 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 320 { 321 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 322 const struct sof_intel_dsp_desc *chip = hda->desc; 323 324 /* enable IPC DONE and BUSY interrupts */ 325 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 326 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 327 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 328 329 /* enable IPC interrupt */ 330 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 331 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 332 } 333 334 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 335 { 336 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 337 const struct sof_intel_dsp_desc *chip = hda->desc; 338 339 /* disable IPC interrupt */ 340 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 341 HDA_DSP_ADSPIC_IPC, 0); 342 343 /* disable IPC BUSY and DONE interrupt */ 344 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 345 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 346 } 347 348 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 349 { 350 int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 351 struct snd_sof_pdata *pdata = sdev->pdata; 352 const struct sof_intel_dsp_desc *chip; 353 354 chip = get_chip_info(pdata); 355 while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) & 356 SOF_HDA_VS_D0I3C_CIP) { 357 if (!retry--) 358 return -ETIMEDOUT; 359 usleep_range(10, 15); 360 } 361 362 return 0; 363 } 364 365 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 366 { 367 const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm); 368 369 if (pm_ops && pm_ops->set_pm_gate) 370 return pm_ops->set_pm_gate(sdev, flags); 371 372 return 0; 373 } 374 375 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 376 { 377 struct snd_sof_pdata *pdata = sdev->pdata; 378 const struct sof_intel_dsp_desc *chip; 379 int ret; 380 u8 reg; 381 382 chip = get_chip_info(pdata); 383 384 /* Write to D0I3C after Command-In-Progress bit is cleared */ 385 ret = hda_dsp_wait_d0i3c_done(sdev); 386 if (ret < 0) { 387 dev_err(sdev->dev, "CIP timeout before D0I3C update!\n"); 388 return ret; 389 } 390 391 /* Update D0I3C register */ 392 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset, 393 SOF_HDA_VS_D0I3C_I3, value); 394 395 /* Wait for cmd in progress to be cleared before exiting the function */ 396 ret = hda_dsp_wait_d0i3c_done(sdev); 397 if (ret < 0) { 398 dev_err(sdev->dev, "CIP timeout after D0I3C update!\n"); 399 return ret; 400 } 401 402 reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset); 403 trace_sof_intel_D0I3C_updated(sdev, reg); 404 405 return 0; 406 } 407 408 /* 409 * d0i3 streaming is enabled if all the active streams can 410 * work in d0i3 state and playback is enabled 411 */ 412 static bool hda_dsp_d0i3_streaming_applicable(struct snd_sof_dev *sdev) 413 { 414 struct snd_pcm_substream *substream; 415 struct snd_sof_pcm *spcm; 416 bool playback_active = false; 417 int dir; 418 419 list_for_each_entry(spcm, &sdev->pcm_list, list) { 420 for_each_pcm_streams(dir) { 421 substream = spcm->stream[dir].substream; 422 if (!substream || !substream->runtime) 423 continue; 424 425 if (!spcm->stream[dir].d0i3_compatible) 426 return false; 427 428 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 429 playback_active = true; 430 } 431 } 432 433 return playback_active; 434 } 435 436 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 437 const struct sof_dsp_power_state *target_state) 438 { 439 u32 flags = 0; 440 int ret; 441 u8 value = 0; 442 443 /* 444 * Sanity check for illegal state transitions 445 * The only allowed transitions are: 446 * 1. D3 -> D0I0 447 * 2. D0I0 -> D0I3 448 * 3. D0I3 -> D0I0 449 */ 450 switch (sdev->dsp_power_state.state) { 451 case SOF_DSP_PM_D0: 452 /* Follow the sequence below for D0 substate transitions */ 453 break; 454 case SOF_DSP_PM_D3: 455 /* Follow regular flow for D3 -> D0 transition */ 456 return 0; 457 default: 458 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 459 sdev->dsp_power_state.state, target_state->state); 460 return -EINVAL; 461 } 462 463 /* Set flags and register value for D0 target substate */ 464 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 465 value = SOF_HDA_VS_D0I3C_I3; 466 467 /* 468 * Trace DMA need to be disabled when the DSP enters 469 * D0I3 for S0Ix suspend, but it can be kept enabled 470 * when the DSP enters D0I3 while the system is in S0 471 * for debug purpose. 472 */ 473 if (!sdev->fw_trace_is_supported || 474 !hda_enable_trace_D0I3_S0 || 475 sdev->system_suspend_target != SOF_SUSPEND_NONE) 476 flags = HDA_PM_NO_DMA_TRACE; 477 478 if (hda_dsp_d0i3_streaming_applicable(sdev)) 479 flags |= HDA_PM_PG_STREAMING; 480 } else { 481 /* prevent power gating in D0I0 */ 482 flags = HDA_PM_PPG; 483 } 484 485 /* update D0I3C register */ 486 ret = hda_dsp_update_d0i3c_register(sdev, value); 487 if (ret < 0) 488 return ret; 489 490 /* 491 * Notify the DSP of the state change. 492 * If this IPC fails, revert the D0I3C register update in order 493 * to prevent partial state change. 494 */ 495 ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 496 if (ret < 0) { 497 dev_err(sdev->dev, 498 "error: PM_GATE ipc error %d\n", ret); 499 goto revert; 500 } 501 502 return ret; 503 504 revert: 505 /* fallback to the previous register value */ 506 value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 507 508 /* 509 * This can fail but return the IPC error to signal that 510 * the state change failed. 511 */ 512 hda_dsp_update_d0i3c_register(sdev, value); 513 514 return ret; 515 } 516 517 /* helper to log DSP state */ 518 static void hda_dsp_state_log(struct snd_sof_dev *sdev) 519 { 520 switch (sdev->dsp_power_state.state) { 521 case SOF_DSP_PM_D0: 522 switch (sdev->dsp_power_state.substate) { 523 case SOF_HDA_DSP_PM_D0I0: 524 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); 525 break; 526 case SOF_HDA_DSP_PM_D0I3: 527 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); 528 break; 529 default: 530 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", 531 sdev->dsp_power_state.substate); 532 break; 533 } 534 break; 535 case SOF_DSP_PM_D1: 536 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); 537 break; 538 case SOF_DSP_PM_D2: 539 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); 540 break; 541 case SOF_DSP_PM_D3: 542 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); 543 break; 544 default: 545 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", 546 sdev->dsp_power_state.state); 547 break; 548 } 549 } 550 551 /* 552 * All DSP power state transitions are initiated by the driver. 553 * If the requested state change fails, the error is simply returned. 554 * Further state transitions are attempted only when the set_power_save() op 555 * is called again either because of a new IPC sent to the DSP or 556 * during system suspend/resume. 557 */ 558 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 559 const struct sof_dsp_power_state *target_state) 560 { 561 int ret = 0; 562 563 /* 564 * When the DSP is already in D0I3 and the target state is D0I3, 565 * it could be the case that the DSP is in D0I3 during S0 566 * and the system is suspending to S0Ix. Therefore, 567 * hda_dsp_set_D0_state() must be called to disable trace DMA 568 * by sending the PM_GATE IPC to the FW. 569 */ 570 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 571 sdev->system_suspend_target == SOF_SUSPEND_S0IX) 572 goto set_state; 573 574 /* 575 * For all other cases, return without doing anything if 576 * the DSP is already in the target state. 577 */ 578 if (target_state->state == sdev->dsp_power_state.state && 579 target_state->substate == sdev->dsp_power_state.substate) 580 return 0; 581 582 set_state: 583 switch (target_state->state) { 584 case SOF_DSP_PM_D0: 585 ret = hda_dsp_set_D0_state(sdev, target_state); 586 break; 587 case SOF_DSP_PM_D3: 588 /* The only allowed transition is: D0I0 -> D3 */ 589 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 590 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 591 break; 592 593 dev_err(sdev->dev, 594 "error: transition from %d to %d not allowed\n", 595 sdev->dsp_power_state.state, target_state->state); 596 return -EINVAL; 597 default: 598 dev_err(sdev->dev, "error: target state unsupported %d\n", 599 target_state->state); 600 return -EINVAL; 601 } 602 if (ret < 0) { 603 dev_err(sdev->dev, 604 "failed to set requested target DSP state %d substate %d\n", 605 target_state->state, target_state->substate); 606 return ret; 607 } 608 609 sdev->dsp_power_state = *target_state; 610 hda_dsp_state_log(sdev); 611 return ret; 612 } 613 614 /* 615 * Audio DSP states may transform as below:- 616 * 617 * Opportunistic D0I3 in S0 618 * Runtime +---------------------+ Delayed D0i3 work timeout 619 * suspend | +--------------------+ 620 * +------------+ D0I0(active) | | 621 * | | <---------------+ | 622 * | +--------> | New IPC | | 623 * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 624 * | |resume | | | | | | 625 * | | | | | | | | 626 * | | System| | | | | | 627 * | | resume| | S3/S0IX | | | | 628 * | | | | suspend | | S0IX | | 629 * | | | | | |suspend | | 630 * | | | | | | | | 631 * | | | | | | | | 632 * +-v---+-----------+--v-------+ | | +------+----v----+ 633 * | | | +-----------> | 634 * | D3 (suspended) | | | D0I3 | 635 * | | +--------------+ | 636 * | | System resume | | 637 * +----------------------------+ +----------------+ 638 * 639 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 640 * ignored the suspend trigger. Otherwise the DSP 641 * is in D3. 642 */ 643 644 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 645 { 646 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 647 const struct sof_intel_dsp_desc *chip = hda->desc; 648 struct hdac_bus *bus = sof_to_bus(sdev); 649 int ret, j; 650 651 /* 652 * The memory used for IMR boot loses its content in deeper than S3 state 653 * We must not try IMR boot on next power up (as it will fail). 654 * 655 * In case of firmware crash or boot failure set the skip_imr_boot to true 656 * as well in order to try to re-load the firmware to do a 'cold' boot. 657 */ 658 if (sdev->system_suspend_target > SOF_SUSPEND_S3 || 659 sdev->fw_state == SOF_FW_CRASHED || 660 sdev->fw_state == SOF_FW_BOOT_FAILED) 661 hda->skip_imr_boot = true; 662 663 ret = chip->disable_interrupts(sdev); 664 if (ret < 0) 665 return ret; 666 667 hda_codec_jack_wake_enable(sdev, runtime_suspend); 668 669 /* power down all hda links */ 670 hda_bus_ml_suspend(bus); 671 672 ret = chip->power_down_dsp(sdev); 673 if (ret < 0) { 674 dev_err(sdev->dev, "failed to power down DSP during suspend\n"); 675 return ret; 676 } 677 678 /* reset ref counts for all cores */ 679 for (j = 0; j < chip->cores_num; j++) 680 sdev->dsp_core_ref_count[j] = 0; 681 682 /* disable ppcap interrupt */ 683 hda_dsp_ctrl_ppcap_enable(sdev, false); 684 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 685 686 /* disable hda bus irq and streams */ 687 hda_dsp_ctrl_stop_chip(sdev); 688 689 /* disable LP retention mode */ 690 snd_sof_pci_update_bits(sdev, PCI_PGCTL, 691 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 692 693 /* reset controller */ 694 ret = hda_dsp_ctrl_link_reset(sdev, true); 695 if (ret < 0) { 696 dev_err(sdev->dev, 697 "error: failed to reset controller during suspend\n"); 698 return ret; 699 } 700 701 /* display codec can powered off after link reset */ 702 hda_codec_i915_display_power(sdev, false); 703 704 return 0; 705 } 706 707 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 708 { 709 int ret; 710 711 /* display codec must be powered before link reset */ 712 hda_codec_i915_display_power(sdev, true); 713 714 /* 715 * clear TCSEL to clear playback on some HD Audio 716 * codecs. PCI TCSEL is defined in the Intel manuals. 717 */ 718 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 719 720 /* reset and start hda controller */ 721 ret = hda_dsp_ctrl_init_chip(sdev); 722 if (ret < 0) { 723 dev_err(sdev->dev, 724 "error: failed to start controller after resume\n"); 725 goto cleanup; 726 } 727 728 /* check jack status */ 729 if (runtime_resume) { 730 hda_codec_jack_wake_enable(sdev, false); 731 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) 732 hda_codec_jack_check(sdev); 733 } 734 735 /* enable ppcap interrupt */ 736 hda_dsp_ctrl_ppcap_enable(sdev, true); 737 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 738 739 cleanup: 740 /* display codec can powered off after controller init */ 741 hda_codec_i915_display_power(sdev, false); 742 743 return 0; 744 } 745 746 int hda_dsp_resume(struct snd_sof_dev *sdev) 747 { 748 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 749 struct hdac_bus *bus = sof_to_bus(sdev); 750 struct pci_dev *pci = to_pci_dev(sdev->dev); 751 const struct sof_dsp_power_state target_state = { 752 .state = SOF_DSP_PM_D0, 753 .substate = SOF_HDA_DSP_PM_D0I0, 754 }; 755 int ret; 756 757 /* resume from D0I3 */ 758 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 759 ret = hda_bus_ml_resume(bus); 760 if (ret < 0) { 761 dev_err(sdev->dev, 762 "error %d in %s: failed to power up links", 763 ret, __func__); 764 return ret; 765 } 766 767 /* set up CORB/RIRB buffers if was on before suspend */ 768 hda_codec_resume_cmd_io(sdev); 769 770 /* Set DSP power state */ 771 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 772 if (ret < 0) { 773 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 774 target_state.state, target_state.substate); 775 return ret; 776 } 777 778 /* restore L1SEN bit */ 779 if (hda->l1_support_changed) 780 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 781 HDA_VS_INTEL_EM2, 782 HDA_VS_INTEL_EM2_L1SEN, 0); 783 784 /* restore and disable the system wakeup */ 785 pci_restore_state(pci); 786 disable_irq_wake(pci->irq); 787 return 0; 788 } 789 790 /* init hda controller. DSP cores will be powered up during fw boot */ 791 ret = hda_resume(sdev, false); 792 if (ret < 0) 793 return ret; 794 795 return snd_sof_dsp_set_power_state(sdev, &target_state); 796 } 797 798 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 799 { 800 const struct sof_dsp_power_state target_state = { 801 .state = SOF_DSP_PM_D0, 802 }; 803 int ret; 804 805 /* init hda controller. DSP cores will be powered up during fw boot */ 806 ret = hda_resume(sdev, true); 807 if (ret < 0) 808 return ret; 809 810 return snd_sof_dsp_set_power_state(sdev, &target_state); 811 } 812 813 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 814 { 815 struct hdac_bus *hbus = sof_to_bus(sdev); 816 817 if (hbus->codec_powered) { 818 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 819 (unsigned int)hbus->codec_powered); 820 return -EBUSY; 821 } 822 823 return 0; 824 } 825 826 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 827 { 828 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 829 const struct sof_dsp_power_state target_state = { 830 .state = SOF_DSP_PM_D3, 831 }; 832 int ret; 833 834 /* cancel any attempt for DSP D0I3 */ 835 cancel_delayed_work_sync(&hda->d0i3_work); 836 837 /* stop hda controller and power dsp off */ 838 ret = hda_suspend(sdev, true); 839 if (ret < 0) 840 return ret; 841 842 return snd_sof_dsp_set_power_state(sdev, &target_state); 843 } 844 845 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 846 { 847 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 848 struct hdac_bus *bus = sof_to_bus(sdev); 849 struct pci_dev *pci = to_pci_dev(sdev->dev); 850 const struct sof_dsp_power_state target_dsp_state = { 851 .state = target_state, 852 .substate = target_state == SOF_DSP_PM_D0 ? 853 SOF_HDA_DSP_PM_D0I3 : 0, 854 }; 855 int ret; 856 857 /* cancel any attempt for DSP D0I3 */ 858 cancel_delayed_work_sync(&hda->d0i3_work); 859 860 if (target_state == SOF_DSP_PM_D0) { 861 /* Set DSP power state */ 862 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 863 if (ret < 0) { 864 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 865 target_dsp_state.state, 866 target_dsp_state.substate); 867 return ret; 868 } 869 870 /* enable L1SEN to make sure the system can enter S0Ix */ 871 hda->l1_support_changed = 872 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 873 HDA_VS_INTEL_EM2, 874 HDA_VS_INTEL_EM2_L1SEN, 875 HDA_VS_INTEL_EM2_L1SEN); 876 877 /* stop the CORB/RIRB DMA if it is On */ 878 hda_codec_suspend_cmd_io(sdev); 879 880 /* no link can be powered in s0ix state */ 881 ret = hda_bus_ml_suspend(bus); 882 if (ret < 0) { 883 dev_err(sdev->dev, 884 "error %d in %s: failed to power down links", 885 ret, __func__); 886 return ret; 887 } 888 889 /* enable the system waking up via IPC IRQ */ 890 enable_irq_wake(pci->irq); 891 pci_save_state(pci); 892 return 0; 893 } 894 895 /* stop hda controller and power dsp off */ 896 ret = hda_suspend(sdev, false); 897 if (ret < 0) { 898 dev_err(bus->dev, "error: suspending dsp\n"); 899 return ret; 900 } 901 902 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 903 } 904 905 static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev) 906 { 907 struct hdac_bus *bus = sof_to_bus(sdev); 908 struct hdac_stream *s; 909 unsigned int active_streams = 0; 910 int sd_offset; 911 u32 val; 912 913 list_for_each_entry(s, &bus->stream_list, list) { 914 sd_offset = SOF_STREAM_SD_OFFSET(s); 915 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 916 sd_offset); 917 if (val & SOF_HDA_SD_CTL_DMA_START) 918 active_streams |= BIT(s->index); 919 } 920 921 return active_streams; 922 } 923 924 static int hda_dsp_s5_quirk(struct snd_sof_dev *sdev) 925 { 926 int ret; 927 928 /* 929 * Do not assume a certain timing between the prior 930 * suspend flow, and running of this quirk function. 931 * This is needed if the controller was just put 932 * to reset before calling this function. 933 */ 934 usleep_range(500, 1000); 935 936 /* 937 * Take controller out of reset to flush DMA 938 * transactions. 939 */ 940 ret = hda_dsp_ctrl_link_reset(sdev, false); 941 if (ret < 0) 942 return ret; 943 944 usleep_range(500, 1000); 945 946 /* Restore state for shutdown, back to reset */ 947 ret = hda_dsp_ctrl_link_reset(sdev, true); 948 if (ret < 0) 949 return ret; 950 951 return ret; 952 } 953 954 int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev) 955 { 956 unsigned int active_streams; 957 int ret, ret2; 958 959 /* check if DMA cleanup has been successful */ 960 active_streams = hda_dsp_check_for_dma_streams(sdev); 961 962 sdev->system_suspend_target = SOF_SUSPEND_S3; 963 ret = snd_sof_suspend(sdev->dev); 964 965 if (active_streams) { 966 dev_warn(sdev->dev, 967 "There were active DSP streams (%#x) at shutdown, trying to recover\n", 968 active_streams); 969 ret2 = hda_dsp_s5_quirk(sdev); 970 if (ret2 < 0) 971 dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2); 972 } 973 974 return ret; 975 } 976 977 int hda_dsp_shutdown(struct snd_sof_dev *sdev) 978 { 979 sdev->system_suspend_target = SOF_SUSPEND_S3; 980 return snd_sof_suspend(sdev->dev); 981 } 982 983 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 984 { 985 int ret; 986 987 /* make sure all DAI resources are freed */ 988 ret = hda_dsp_dais_suspend(sdev); 989 if (ret < 0) 990 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__); 991 992 return ret; 993 } 994 995 void hda_dsp_d0i3_work(struct work_struct *work) 996 { 997 struct sof_intel_hda_dev *hdev = container_of(work, 998 struct sof_intel_hda_dev, 999 d0i3_work.work); 1000 struct hdac_bus *bus = &hdev->hbus.core; 1001 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 1002 struct sof_dsp_power_state target_state = { 1003 .state = SOF_DSP_PM_D0, 1004 .substate = SOF_HDA_DSP_PM_D0I3, 1005 }; 1006 int ret; 1007 1008 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 1009 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 1010 /* remain in D0I0 */ 1011 return; 1012 1013 /* This can fail but error cannot be propagated */ 1014 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 1015 if (ret < 0) 1016 dev_err_ratelimited(sdev->dev, 1017 "error: failed to set DSP state %d substate %d\n", 1018 target_state.state, target_state.substate); 1019 } 1020 1021 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core) 1022 { 1023 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 1024 int ret, ret1; 1025 1026 /* power up core */ 1027 ret = hda_dsp_enable_core(sdev, BIT(core)); 1028 if (ret < 0) { 1029 dev_err(sdev->dev, "failed to power up core %d with err: %d\n", 1030 core, ret); 1031 return ret; 1032 } 1033 1034 /* No need to send IPC for primary core or if FW boot is not complete */ 1035 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE) 1036 return 0; 1037 1038 /* No need to continue the set_core_state ops is not available */ 1039 if (!pm_ops->set_core_state) 1040 return 0; 1041 1042 /* Now notify DSP for secondary cores */ 1043 ret = pm_ops->set_core_state(sdev, core, true); 1044 if (ret < 0) { 1045 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n", 1046 core, ret); 1047 goto power_down; 1048 } 1049 1050 return ret; 1051 1052 power_down: 1053 /* power down core if it is host managed and return the original error if this fails too */ 1054 ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core)); 1055 if (ret1 < 0) 1056 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1); 1057 1058 return ret; 1059 } 1060 1061 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev) 1062 { 1063 hda_sdw_int_enable(sdev, false); 1064 hda_dsp_ipc_int_disable(sdev); 1065 1066 return 0; 1067 } 1068