1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include "../sof-audio.h" 22 #include "../ops.h" 23 #include "hda.h" 24 #include "hda-ipc.h" 25 26 static bool hda_enable_trace_D0I3_S0; 27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 29 MODULE_PARM_DESC(enable_trace_D0I3_S0, 30 "SOF HDA enable trace when the DSP is in D0I3 in S0"); 31 #endif 32 33 /* 34 * DSP Core control. 35 */ 36 37 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 38 { 39 u32 adspcs; 40 u32 reset; 41 int ret; 42 43 /* set reset bits for cores */ 44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 46 HDA_DSP_REG_ADSPCS, 47 reset, reset), 48 49 /* poll with timeout to check if operation successful */ 50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 51 HDA_DSP_REG_ADSPCS, adspcs, 52 ((adspcs & reset) == reset), 53 HDA_DSP_REG_POLL_INTERVAL_US, 54 HDA_DSP_RESET_TIMEOUT_US); 55 if (ret < 0) { 56 dev_err(sdev->dev, 57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 58 __func__); 59 return ret; 60 } 61 62 /* has core entered reset ? */ 63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 64 HDA_DSP_REG_ADSPCS); 65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 67 dev_err(sdev->dev, 68 "error: reset enter failed: core_mask %x adspcs 0x%x\n", 69 core_mask, adspcs); 70 ret = -EIO; 71 } 72 73 return ret; 74 } 75 76 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 77 { 78 unsigned int crst; 79 u32 adspcs; 80 int ret; 81 82 /* clear reset bits for cores */ 83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 84 HDA_DSP_REG_ADSPCS, 85 HDA_DSP_ADSPCS_CRST_MASK(core_mask), 86 0); 87 88 /* poll with timeout to check if operation successful */ 89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 91 HDA_DSP_REG_ADSPCS, adspcs, 92 !(adspcs & crst), 93 HDA_DSP_REG_POLL_INTERVAL_US, 94 HDA_DSP_RESET_TIMEOUT_US); 95 96 if (ret < 0) { 97 dev_err(sdev->dev, 98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 99 __func__); 100 return ret; 101 } 102 103 /* has core left reset ? */ 104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 105 HDA_DSP_REG_ADSPCS); 106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 107 dev_err(sdev->dev, 108 "error: reset leave failed: core_mask %x adspcs 0x%x\n", 109 core_mask, adspcs); 110 ret = -EIO; 111 } 112 113 return ret; 114 } 115 116 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 117 { 118 /* stall core */ 119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 120 HDA_DSP_REG_ADSPCS, 121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 123 124 /* set reset state */ 125 return hda_dsp_core_reset_enter(sdev, core_mask); 126 } 127 128 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 129 { 130 int ret; 131 132 /* leave reset state */ 133 ret = hda_dsp_core_reset_leave(sdev, core_mask); 134 if (ret < 0) 135 return ret; 136 137 /* run core */ 138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 140 HDA_DSP_REG_ADSPCS, 141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 142 0); 143 144 /* is core now running ? */ 145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 146 hda_dsp_core_stall_reset(sdev, core_mask); 147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 148 core_mask); 149 ret = -EIO; 150 } 151 152 return ret; 153 } 154 155 /* 156 * Power Management. 157 */ 158 159 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 160 { 161 unsigned int cpa; 162 u32 adspcs; 163 int ret; 164 165 /* update bits */ 166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 167 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 168 HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 169 170 /* poll with timeout to check if operation successful */ 171 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 173 HDA_DSP_REG_ADSPCS, adspcs, 174 (adspcs & cpa) == cpa, 175 HDA_DSP_REG_POLL_INTERVAL_US, 176 HDA_DSP_RESET_TIMEOUT_US); 177 if (ret < 0) { 178 dev_err(sdev->dev, 179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 180 __func__); 181 return ret; 182 } 183 184 /* did core power up ? */ 185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 186 HDA_DSP_REG_ADSPCS); 187 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 188 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 189 dev_err(sdev->dev, 190 "error: power up core failed core_mask %xadspcs 0x%x\n", 191 core_mask, adspcs); 192 ret = -EIO; 193 } 194 195 return ret; 196 } 197 198 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 199 { 200 u32 adspcs; 201 int ret; 202 203 /* update bits */ 204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 205 HDA_DSP_REG_ADSPCS, 206 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 207 208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 209 HDA_DSP_REG_ADSPCS, adspcs, 210 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)), 211 HDA_DSP_REG_POLL_INTERVAL_US, 212 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 213 if (ret < 0) 214 dev_err(sdev->dev, 215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 216 __func__); 217 218 return ret; 219 } 220 221 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 222 unsigned int core_mask) 223 { 224 int val; 225 bool is_enable; 226 227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 228 229 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) && 230 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) && 231 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 232 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask))); 233 234 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 235 is_enable, core_mask); 236 237 return is_enable; 238 } 239 240 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 241 { 242 int ret; 243 244 /* return if core is already enabled */ 245 if (hda_dsp_core_is_enabled(sdev, core_mask)) 246 return 0; 247 248 /* power up */ 249 ret = hda_dsp_core_power_up(sdev, core_mask); 250 if (ret < 0) { 251 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 252 core_mask); 253 return ret; 254 } 255 256 return hda_dsp_core_run(sdev, core_mask); 257 } 258 259 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 260 unsigned int core_mask) 261 { 262 int ret; 263 264 /* place core in reset prior to power down */ 265 ret = hda_dsp_core_stall_reset(sdev, core_mask); 266 if (ret < 0) { 267 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 268 core_mask); 269 return ret; 270 } 271 272 /* power down core */ 273 ret = hda_dsp_core_power_down(sdev, core_mask); 274 if (ret < 0) { 275 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 276 core_mask, ret); 277 return ret; 278 } 279 280 /* make sure we are in OFF state */ 281 if (hda_dsp_core_is_enabled(sdev, core_mask)) { 282 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 283 core_mask, ret); 284 ret = -EIO; 285 } 286 287 return ret; 288 } 289 290 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 291 { 292 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 293 const struct sof_intel_dsp_desc *chip = hda->desc; 294 295 /* enable IPC DONE and BUSY interrupts */ 296 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 297 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 298 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 299 300 /* enable IPC interrupt */ 301 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 302 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 303 } 304 305 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 306 { 307 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 308 const struct sof_intel_dsp_desc *chip = hda->desc; 309 310 /* disable IPC interrupt */ 311 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 312 HDA_DSP_ADSPIC_IPC, 0); 313 314 /* disable IPC BUSY and DONE interrupt */ 315 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 316 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 317 } 318 319 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 320 { 321 struct hdac_bus *bus = sof_to_bus(sdev); 322 int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 323 324 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) { 325 if (!retry--) 326 return -ETIMEDOUT; 327 usleep_range(10, 15); 328 } 329 330 return 0; 331 } 332 333 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 334 { 335 struct sof_ipc_pm_gate pm_gate; 336 struct sof_ipc_reply reply; 337 338 memset(&pm_gate, 0, sizeof(pm_gate)); 339 340 /* configure pm_gate ipc message */ 341 pm_gate.hdr.size = sizeof(pm_gate); 342 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE; 343 pm_gate.flags = flags; 344 345 /* send pm_gate ipc to dsp */ 346 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd, 347 &pm_gate, sizeof(pm_gate), &reply, 348 sizeof(reply)); 349 } 350 351 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 352 { 353 struct hdac_bus *bus = sof_to_bus(sdev); 354 int ret; 355 356 /* Write to D0I3C after Command-In-Progress bit is cleared */ 357 ret = hda_dsp_wait_d0i3c_done(sdev); 358 if (ret < 0) { 359 dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); 360 return ret; 361 } 362 363 /* Update D0I3C register */ 364 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); 365 366 /* Wait for cmd in progress to be cleared before exiting the function */ 367 ret = hda_dsp_wait_d0i3c_done(sdev); 368 if (ret < 0) { 369 dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); 370 return ret; 371 } 372 373 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n", 374 snd_hdac_chip_readb(bus, VS_D0I3C)); 375 376 return 0; 377 } 378 379 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 380 const struct sof_dsp_power_state *target_state) 381 { 382 u32 flags = 0; 383 int ret; 384 u8 value = 0; 385 386 /* 387 * Sanity check for illegal state transitions 388 * The only allowed transitions are: 389 * 1. D3 -> D0I0 390 * 2. D0I0 -> D0I3 391 * 3. D0I3 -> D0I0 392 */ 393 switch (sdev->dsp_power_state.state) { 394 case SOF_DSP_PM_D0: 395 /* Follow the sequence below for D0 substate transitions */ 396 break; 397 case SOF_DSP_PM_D3: 398 /* Follow regular flow for D3 -> D0 transition */ 399 return 0; 400 default: 401 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 402 sdev->dsp_power_state.state, target_state->state); 403 return -EINVAL; 404 } 405 406 /* Set flags and register value for D0 target substate */ 407 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 408 value = SOF_HDA_VS_D0I3C_I3; 409 410 /* 411 * Trace DMA is disabled by default when the DSP enters D0I3. 412 * But it can be kept enabled when the DSP enters D0I3 while the 413 * system is in S0 for debug. 414 */ 415 if (hda_enable_trace_D0I3_S0 && 416 sdev->system_suspend_target != SOF_SUSPEND_NONE) 417 flags = HDA_PM_NO_DMA_TRACE; 418 } else { 419 /* prevent power gating in D0I0 */ 420 flags = HDA_PM_PPG; 421 } 422 423 /* update D0I3C register */ 424 ret = hda_dsp_update_d0i3c_register(sdev, value); 425 if (ret < 0) 426 return ret; 427 428 /* 429 * Notify the DSP of the state change. 430 * If this IPC fails, revert the D0I3C register update in order 431 * to prevent partial state change. 432 */ 433 ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 434 if (ret < 0) { 435 dev_err(sdev->dev, 436 "error: PM_GATE ipc error %d\n", ret); 437 goto revert; 438 } 439 440 return ret; 441 442 revert: 443 /* fallback to the previous register value */ 444 value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 445 446 /* 447 * This can fail but return the IPC error to signal that 448 * the state change failed. 449 */ 450 hda_dsp_update_d0i3c_register(sdev, value); 451 452 return ret; 453 } 454 455 /* helper to log DSP state */ 456 static void hda_dsp_state_log(struct snd_sof_dev *sdev) 457 { 458 switch (sdev->dsp_power_state.state) { 459 case SOF_DSP_PM_D0: 460 switch (sdev->dsp_power_state.substate) { 461 case SOF_HDA_DSP_PM_D0I0: 462 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); 463 break; 464 case SOF_HDA_DSP_PM_D0I3: 465 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); 466 break; 467 default: 468 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", 469 sdev->dsp_power_state.substate); 470 break; 471 } 472 break; 473 case SOF_DSP_PM_D1: 474 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); 475 break; 476 case SOF_DSP_PM_D2: 477 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); 478 break; 479 case SOF_DSP_PM_D3_HOT: 480 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n"); 481 break; 482 case SOF_DSP_PM_D3: 483 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); 484 break; 485 case SOF_DSP_PM_D3_COLD: 486 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n"); 487 break; 488 default: 489 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", 490 sdev->dsp_power_state.state); 491 break; 492 } 493 } 494 495 /* 496 * All DSP power state transitions are initiated by the driver. 497 * If the requested state change fails, the error is simply returned. 498 * Further state transitions are attempted only when the set_power_save() op 499 * is called again either because of a new IPC sent to the DSP or 500 * during system suspend/resume. 501 */ 502 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 503 const struct sof_dsp_power_state *target_state) 504 { 505 int ret = 0; 506 507 /* 508 * When the DSP is already in D0I3 and the target state is D0I3, 509 * it could be the case that the DSP is in D0I3 during S0 510 * and the system is suspending to S0Ix. Therefore, 511 * hda_dsp_set_D0_state() must be called to disable trace DMA 512 * by sending the PM_GATE IPC to the FW. 513 */ 514 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 515 sdev->system_suspend_target == SOF_SUSPEND_S0IX) 516 goto set_state; 517 518 /* 519 * For all other cases, return without doing anything if 520 * the DSP is already in the target state. 521 */ 522 if (target_state->state == sdev->dsp_power_state.state && 523 target_state->substate == sdev->dsp_power_state.substate) 524 return 0; 525 526 set_state: 527 switch (target_state->state) { 528 case SOF_DSP_PM_D0: 529 ret = hda_dsp_set_D0_state(sdev, target_state); 530 break; 531 case SOF_DSP_PM_D3: 532 /* The only allowed transition is: D0I0 -> D3 */ 533 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 534 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 535 break; 536 537 dev_err(sdev->dev, 538 "error: transition from %d to %d not allowed\n", 539 sdev->dsp_power_state.state, target_state->state); 540 return -EINVAL; 541 default: 542 dev_err(sdev->dev, "error: target state unsupported %d\n", 543 target_state->state); 544 return -EINVAL; 545 } 546 if (ret < 0) { 547 dev_err(sdev->dev, 548 "failed to set requested target DSP state %d substate %d\n", 549 target_state->state, target_state->substate); 550 return ret; 551 } 552 553 sdev->dsp_power_state = *target_state; 554 hda_dsp_state_log(sdev); 555 return ret; 556 } 557 558 /* 559 * Audio DSP states may transform as below:- 560 * 561 * Opportunistic D0I3 in S0 562 * Runtime +---------------------+ Delayed D0i3 work timeout 563 * suspend | +--------------------+ 564 * +------------+ D0I0(active) | | 565 * | | <---------------+ | 566 * | +--------> | New IPC | | 567 * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 568 * | |resume | | | | | | 569 * | | | | | | | | 570 * | | System| | | | | | 571 * | | resume| | S3/S0IX | | | | 572 * | | | | suspend | | S0IX | | 573 * | | | | | |suspend | | 574 * | | | | | | | | 575 * | | | | | | | | 576 * +-v---+-----------+--v-------+ | | +------+----v----+ 577 * | | | +-----------> | 578 * | D3 (suspended) | | | D0I3 | 579 * | | +--------------+ | 580 * | | System resume | | 581 * +----------------------------+ +----------------+ 582 * 583 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 584 * ignored the suspend trigger. Otherwise the DSP 585 * is in D3. 586 */ 587 588 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 589 { 590 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 591 const struct sof_intel_dsp_desc *chip = hda->desc; 592 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 593 struct hdac_bus *bus = sof_to_bus(sdev); 594 #endif 595 int ret; 596 597 /* disable IPC interrupts */ 598 hda_dsp_ipc_int_disable(sdev); 599 600 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 601 if (runtime_suspend) 602 hda_codec_jack_wake_enable(sdev); 603 604 /* power down all hda link */ 605 snd_hdac_ext_bus_link_power_down_all(bus); 606 #endif 607 608 /* power down DSP */ 609 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask); 610 if (ret < 0) { 611 dev_err(sdev->dev, 612 "error: failed to power down core during suspend\n"); 613 return ret; 614 } 615 616 /* disable ppcap interrupt */ 617 hda_dsp_ctrl_ppcap_enable(sdev, false); 618 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 619 620 /* disable hda bus irq and streams */ 621 hda_dsp_ctrl_stop_chip(sdev); 622 623 /* disable LP retention mode */ 624 snd_sof_pci_update_bits(sdev, PCI_PGCTL, 625 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 626 627 /* reset controller */ 628 ret = hda_dsp_ctrl_link_reset(sdev, true); 629 if (ret < 0) { 630 dev_err(sdev->dev, 631 "error: failed to reset controller during suspend\n"); 632 return ret; 633 } 634 635 /* display codec can powered off after link reset */ 636 hda_codec_i915_display_power(sdev, false); 637 638 return 0; 639 } 640 641 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 642 { 643 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 644 struct hdac_bus *bus = sof_to_bus(sdev); 645 struct hdac_ext_link *hlink = NULL; 646 #endif 647 int ret; 648 649 /* display codec must be powered before link reset */ 650 hda_codec_i915_display_power(sdev, true); 651 652 /* 653 * clear TCSEL to clear playback on some HD Audio 654 * codecs. PCI TCSEL is defined in the Intel manuals. 655 */ 656 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 657 658 /* reset and start hda controller */ 659 ret = hda_dsp_ctrl_init_chip(sdev, true); 660 if (ret < 0) { 661 dev_err(sdev->dev, 662 "error: failed to start controller after resume\n"); 663 return ret; 664 } 665 666 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 667 /* check jack status */ 668 if (runtime_resume) 669 hda_codec_jack_check(sdev); 670 671 /* turn off the links that were off before suspend */ 672 list_for_each_entry(hlink, &bus->hlink_list, list) { 673 if (!hlink->ref_count) 674 snd_hdac_ext_bus_link_power_down(hlink); 675 } 676 677 /* check dma status and clean up CORB/RIRB buffers */ 678 if (!bus->cmd_dma_state) 679 snd_hdac_bus_stop_cmd_io(bus); 680 #endif 681 682 /* enable ppcap interrupt */ 683 hda_dsp_ctrl_ppcap_enable(sdev, true); 684 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 685 686 return 0; 687 } 688 689 int hda_dsp_resume(struct snd_sof_dev *sdev) 690 { 691 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 692 struct pci_dev *pci = to_pci_dev(sdev->dev); 693 const struct sof_dsp_power_state target_state = { 694 .state = SOF_DSP_PM_D0, 695 .substate = SOF_HDA_DSP_PM_D0I0, 696 }; 697 int ret; 698 699 /* resume from D0I3 */ 700 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 701 hda_codec_i915_display_power(sdev, true); 702 703 /* Set DSP power state */ 704 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 705 if (ret < 0) { 706 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 707 target_state.state, target_state.substate); 708 return ret; 709 } 710 711 /* restore L1SEN bit */ 712 if (hda->l1_support_changed) 713 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 714 HDA_VS_INTEL_EM2, 715 HDA_VS_INTEL_EM2_L1SEN, 0); 716 717 /* restore and disable the system wakeup */ 718 pci_restore_state(pci); 719 disable_irq_wake(pci->irq); 720 return 0; 721 } 722 723 /* init hda controller. DSP cores will be powered up during fw boot */ 724 ret = hda_resume(sdev, false); 725 if (ret < 0) 726 return ret; 727 728 return snd_sof_dsp_set_power_state(sdev, &target_state); 729 } 730 731 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 732 { 733 const struct sof_dsp_power_state target_state = { 734 .state = SOF_DSP_PM_D0, 735 }; 736 int ret; 737 738 /* init hda controller. DSP cores will be powered up during fw boot */ 739 ret = hda_resume(sdev, true); 740 if (ret < 0) 741 return ret; 742 743 return snd_sof_dsp_set_power_state(sdev, &target_state); 744 } 745 746 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 747 { 748 struct hdac_bus *hbus = sof_to_bus(sdev); 749 750 if (hbus->codec_powered) { 751 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 752 (unsigned int)hbus->codec_powered); 753 return -EBUSY; 754 } 755 756 return 0; 757 } 758 759 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 760 { 761 const struct sof_dsp_power_state target_state = { 762 .state = SOF_DSP_PM_D3, 763 }; 764 int ret; 765 766 /* stop hda controller and power dsp off */ 767 ret = hda_suspend(sdev, true); 768 if (ret < 0) 769 return ret; 770 771 return snd_sof_dsp_set_power_state(sdev, &target_state); 772 } 773 774 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 775 { 776 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 777 struct hdac_bus *bus = sof_to_bus(sdev); 778 struct pci_dev *pci = to_pci_dev(sdev->dev); 779 const struct sof_dsp_power_state target_dsp_state = { 780 .state = target_state, 781 .substate = target_state == SOF_DSP_PM_D0 ? 782 SOF_HDA_DSP_PM_D0I3 : 0, 783 }; 784 int ret; 785 786 /* cancel any attempt for DSP D0I3 */ 787 cancel_delayed_work_sync(&hda->d0i3_work); 788 789 if (target_state == SOF_DSP_PM_D0) { 790 /* we can't keep a wakeref to display driver at suspend */ 791 hda_codec_i915_display_power(sdev, false); 792 793 /* Set DSP power state */ 794 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 795 if (ret < 0) { 796 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 797 target_dsp_state.state, 798 target_dsp_state.substate); 799 return ret; 800 } 801 802 /* enable L1SEN to make sure the system can enter S0Ix */ 803 hda->l1_support_changed = 804 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 805 HDA_VS_INTEL_EM2, 806 HDA_VS_INTEL_EM2_L1SEN, 807 HDA_VS_INTEL_EM2_L1SEN); 808 809 /* enable the system waking up via IPC IRQ */ 810 enable_irq_wake(pci->irq); 811 pci_save_state(pci); 812 return 0; 813 } 814 815 /* stop hda controller and power dsp off */ 816 ret = hda_suspend(sdev, false); 817 if (ret < 0) { 818 dev_err(bus->dev, "error: suspending dsp\n"); 819 return ret; 820 } 821 822 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 823 } 824 825 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 826 { 827 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 828 struct hdac_bus *bus = sof_to_bus(sdev); 829 struct snd_soc_pcm_runtime *rtd; 830 struct hdac_ext_stream *stream; 831 struct hdac_ext_link *link; 832 struct hdac_stream *s; 833 const char *name; 834 int stream_tag; 835 836 /* set internal flag for BE */ 837 list_for_each_entry(s, &bus->stream_list, list) { 838 stream = stream_to_hdac_ext_stream(s); 839 840 /* 841 * clear stream. This should already be taken care for running 842 * streams when the SUSPEND trigger is called. But paused 843 * streams do not get suspended, so this needs to be done 844 * explicitly during suspend. 845 */ 846 if (stream->link_substream) { 847 rtd = snd_pcm_substream_chip(stream->link_substream); 848 name = rtd->codec_dai->component->name; 849 link = snd_hdac_ext_bus_get_link(bus, name); 850 if (!link) 851 return -EINVAL; 852 853 stream->link_prepared = 0; 854 855 if (hdac_stream(stream)->direction == 856 SNDRV_PCM_STREAM_CAPTURE) 857 continue; 858 859 stream_tag = hdac_stream(stream)->stream_tag; 860 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 861 } 862 } 863 #endif 864 return 0; 865 } 866 867 void hda_dsp_d0i3_work(struct work_struct *work) 868 { 869 struct sof_intel_hda_dev *hdev = container_of(work, 870 struct sof_intel_hda_dev, 871 d0i3_work.work); 872 struct hdac_bus *bus = &hdev->hbus.core; 873 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 874 struct sof_dsp_power_state target_state; 875 int ret; 876 877 target_state.state = SOF_DSP_PM_D0; 878 879 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 880 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 881 target_state.substate = SOF_HDA_DSP_PM_D0I3; 882 else 883 target_state.substate = SOF_HDA_DSP_PM_D0I0; 884 885 /* remain in D0I0 */ 886 if (target_state.substate == SOF_HDA_DSP_PM_D0I0) 887 return; 888 889 /* This can fail but error cannot be propagated */ 890 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 891 if (ret < 0) 892 dev_err_ratelimited(sdev->dev, 893 "error: failed to set DSP state %d substate %d\n", 894 target_state.state, target_state.substate); 895 } 896