xref: /openbmc/linux/sound/soc/sof/intel/hda-dsp.c (revision 519b58bb)
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license.  When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 //	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 //	    Rander Wang <rander.wang@intel.com>
11 //          Keyon Jie <yang.jie@linux.intel.com>
12 //
13 
14 /*
15  * Hardware interface for generic Intel audio DSP HDA IP
16  */
17 
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include <trace/events/sof_intel.h>
22 #include "../sof-audio.h"
23 #include "../ops.h"
24 #include "hda.h"
25 #include "hda-ipc.h"
26 
27 static bool hda_enable_trace_D0I3_S0;
28 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
29 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
30 MODULE_PARM_DESC(enable_trace_D0I3_S0,
31 		 "SOF HDA enable trace when the DSP is in D0I3 in S0");
32 #endif
33 
34 /*
35  * DSP Core control.
36  */
37 
38 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
39 {
40 	u32 adspcs;
41 	u32 reset;
42 	int ret;
43 
44 	/* set reset bits for cores */
45 	reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
46 	snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
47 					 HDA_DSP_REG_ADSPCS,
48 					 reset, reset);
49 
50 	/* poll with timeout to check if operation successful */
51 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
52 					HDA_DSP_REG_ADSPCS, adspcs,
53 					((adspcs & reset) == reset),
54 					HDA_DSP_REG_POLL_INTERVAL_US,
55 					HDA_DSP_RESET_TIMEOUT_US);
56 	if (ret < 0) {
57 		dev_err(sdev->dev,
58 			"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
59 			__func__);
60 		return ret;
61 	}
62 
63 	/* has core entered reset ? */
64 	adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
65 				  HDA_DSP_REG_ADSPCS);
66 	if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
67 		HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
68 		dev_err(sdev->dev,
69 			"error: reset enter failed: core_mask %x adspcs 0x%x\n",
70 			core_mask, adspcs);
71 		ret = -EIO;
72 	}
73 
74 	return ret;
75 }
76 
77 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
78 {
79 	unsigned int crst;
80 	u32 adspcs;
81 	int ret;
82 
83 	/* clear reset bits for cores */
84 	snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
85 					 HDA_DSP_REG_ADSPCS,
86 					 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
87 					 0);
88 
89 	/* poll with timeout to check if operation successful */
90 	crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
91 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
92 					    HDA_DSP_REG_ADSPCS, adspcs,
93 					    !(adspcs & crst),
94 					    HDA_DSP_REG_POLL_INTERVAL_US,
95 					    HDA_DSP_RESET_TIMEOUT_US);
96 
97 	if (ret < 0) {
98 		dev_err(sdev->dev,
99 			"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
100 			__func__);
101 		return ret;
102 	}
103 
104 	/* has core left reset ? */
105 	adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
106 				  HDA_DSP_REG_ADSPCS);
107 	if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
108 		dev_err(sdev->dev,
109 			"error: reset leave failed: core_mask %x adspcs 0x%x\n",
110 			core_mask, adspcs);
111 		ret = -EIO;
112 	}
113 
114 	return ret;
115 }
116 
117 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
118 {
119 	/* stall core */
120 	snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
121 					 HDA_DSP_REG_ADSPCS,
122 					 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
123 					 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
124 
125 	/* set reset state */
126 	return hda_dsp_core_reset_enter(sdev, core_mask);
127 }
128 
129 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
130 {
131 	int val;
132 	bool is_enable;
133 
134 	val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
135 
136 #define MASK_IS_EQUAL(v, m, field) ({	\
137 	u32 _m = field(m);		\
138 	((v) & _m) == _m;		\
139 })
140 
141 	is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
142 		MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
143 		!(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
144 		!(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
145 
146 #undef MASK_IS_EQUAL
147 
148 	dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
149 		is_enable, core_mask);
150 
151 	return is_enable;
152 }
153 
154 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
155 {
156 	int ret;
157 
158 	/* leave reset state */
159 	ret = hda_dsp_core_reset_leave(sdev, core_mask);
160 	if (ret < 0)
161 		return ret;
162 
163 	/* run core */
164 	dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
165 	snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
166 					 HDA_DSP_REG_ADSPCS,
167 					 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
168 					 0);
169 
170 	/* is core now running ? */
171 	if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
172 		hda_dsp_core_stall_reset(sdev, core_mask);
173 		dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
174 			core_mask);
175 		ret = -EIO;
176 	}
177 
178 	return ret;
179 }
180 
181 /*
182  * Power Management.
183  */
184 
185 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
186 {
187 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
188 	const struct sof_intel_dsp_desc *chip = hda->desc;
189 	unsigned int cpa;
190 	u32 adspcs;
191 	int ret;
192 
193 	/* restrict core_mask to host managed cores mask */
194 	core_mask &= chip->host_managed_cores_mask;
195 	/* return if core_mask is not valid */
196 	if (!core_mask)
197 		return 0;
198 
199 	/* update bits */
200 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
201 				HDA_DSP_ADSPCS_SPA_MASK(core_mask),
202 				HDA_DSP_ADSPCS_SPA_MASK(core_mask));
203 
204 	/* poll with timeout to check if operation successful */
205 	cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
206 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
207 					    HDA_DSP_REG_ADSPCS, adspcs,
208 					    (adspcs & cpa) == cpa,
209 					    HDA_DSP_REG_POLL_INTERVAL_US,
210 					    HDA_DSP_RESET_TIMEOUT_US);
211 	if (ret < 0) {
212 		dev_err(sdev->dev,
213 			"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
214 			__func__);
215 		return ret;
216 	}
217 
218 	/* did core power up ? */
219 	adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
220 				  HDA_DSP_REG_ADSPCS);
221 	if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
222 		HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
223 		dev_err(sdev->dev,
224 			"error: power up core failed core_mask %xadspcs 0x%x\n",
225 			core_mask, adspcs);
226 		ret = -EIO;
227 	}
228 
229 	return ret;
230 }
231 
232 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
233 {
234 	u32 adspcs;
235 	int ret;
236 
237 	/* update bits */
238 	snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
239 					 HDA_DSP_REG_ADSPCS,
240 					 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
241 
242 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
243 				HDA_DSP_REG_ADSPCS, adspcs,
244 				!(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
245 				HDA_DSP_REG_POLL_INTERVAL_US,
246 				HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
247 	if (ret < 0)
248 		dev_err(sdev->dev,
249 			"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
250 			__func__);
251 
252 	return ret;
253 }
254 
255 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
256 {
257 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
258 	const struct sof_intel_dsp_desc *chip = hda->desc;
259 	int ret;
260 
261 	/* restrict core_mask to host managed cores mask */
262 	core_mask &= chip->host_managed_cores_mask;
263 
264 	/* return if core_mask is not valid or cores are already enabled */
265 	if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
266 		return 0;
267 
268 	/* power up */
269 	ret = hda_dsp_core_power_up(sdev, core_mask);
270 	if (ret < 0) {
271 		dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
272 			core_mask);
273 		return ret;
274 	}
275 
276 	return hda_dsp_core_run(sdev, core_mask);
277 }
278 
279 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
280 				  unsigned int core_mask)
281 {
282 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
283 	const struct sof_intel_dsp_desc *chip = hda->desc;
284 	int ret;
285 
286 	/* restrict core_mask to host managed cores mask */
287 	core_mask &= chip->host_managed_cores_mask;
288 
289 	/* return if core_mask is not valid */
290 	if (!core_mask)
291 		return 0;
292 
293 	/* place core in reset prior to power down */
294 	ret = hda_dsp_core_stall_reset(sdev, core_mask);
295 	if (ret < 0) {
296 		dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
297 			core_mask);
298 		return ret;
299 	}
300 
301 	/* power down core */
302 	ret = hda_dsp_core_power_down(sdev, core_mask);
303 	if (ret < 0) {
304 		dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
305 			core_mask, ret);
306 		return ret;
307 	}
308 
309 	/* make sure we are in OFF state */
310 	if (hda_dsp_core_is_enabled(sdev, core_mask)) {
311 		dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
312 			core_mask, ret);
313 		ret = -EIO;
314 	}
315 
316 	return ret;
317 }
318 
319 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
320 {
321 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
322 	const struct sof_intel_dsp_desc *chip = hda->desc;
323 
324 	/* enable IPC DONE and BUSY interrupts */
325 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
326 			HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
327 			HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
328 
329 	/* enable IPC interrupt */
330 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
331 				HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
332 }
333 
334 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
335 {
336 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
337 	const struct sof_intel_dsp_desc *chip = hda->desc;
338 
339 	/* disable IPC interrupt */
340 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
341 				HDA_DSP_ADSPIC_IPC, 0);
342 
343 	/* disable IPC BUSY and DONE interrupt */
344 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
345 			HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
346 }
347 
348 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
349 {
350 	struct hdac_bus *bus = sof_to_bus(sdev);
351 	int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
352 
353 	while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
354 		if (!retry--)
355 			return -ETIMEDOUT;
356 		usleep_range(10, 15);
357 	}
358 
359 	return 0;
360 }
361 
362 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
363 {
364 	struct sof_ipc_pm_gate pm_gate;
365 	struct sof_ipc_reply reply;
366 
367 	memset(&pm_gate, 0, sizeof(pm_gate));
368 
369 	/* configure pm_gate ipc message */
370 	pm_gate.hdr.size = sizeof(pm_gate);
371 	pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
372 	pm_gate.flags = flags;
373 
374 	/* send pm_gate ipc to dsp */
375 	return sof_ipc_tx_message_no_pm(sdev->ipc, &pm_gate, sizeof(pm_gate),
376 					&reply, sizeof(reply));
377 }
378 
379 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
380 {
381 	struct hdac_bus *bus = sof_to_bus(sdev);
382 	int ret;
383 
384 	/* Write to D0I3C after Command-In-Progress bit is cleared */
385 	ret = hda_dsp_wait_d0i3c_done(sdev);
386 	if (ret < 0) {
387 		dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
388 		return ret;
389 	}
390 
391 	/* Update D0I3C register */
392 	snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
393 
394 	/* Wait for cmd in progress to be cleared before exiting the function */
395 	ret = hda_dsp_wait_d0i3c_done(sdev);
396 	if (ret < 0) {
397 		dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
398 		return ret;
399 	}
400 
401 	trace_sof_intel_D0I3C_updated(sdev, snd_hdac_chip_readb(bus, VS_D0I3C));
402 
403 	return 0;
404 }
405 
406 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
407 				const struct sof_dsp_power_state *target_state)
408 {
409 	u32 flags = 0;
410 	int ret;
411 	u8 value = 0;
412 
413 	/*
414 	 * Sanity check for illegal state transitions
415 	 * The only allowed transitions are:
416 	 * 1. D3 -> D0I0
417 	 * 2. D0I0 -> D0I3
418 	 * 3. D0I3 -> D0I0
419 	 */
420 	switch (sdev->dsp_power_state.state) {
421 	case SOF_DSP_PM_D0:
422 		/* Follow the sequence below for D0 substate transitions */
423 		break;
424 	case SOF_DSP_PM_D3:
425 		/* Follow regular flow for D3 -> D0 transition */
426 		return 0;
427 	default:
428 		dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
429 			sdev->dsp_power_state.state, target_state->state);
430 		return -EINVAL;
431 	}
432 
433 	/* Set flags and register value for D0 target substate */
434 	if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
435 		value = SOF_HDA_VS_D0I3C_I3;
436 
437 		/*
438 		 * Trace DMA need to be disabled when the DSP enters
439 		 * D0I3 for S0Ix suspend, but it can be kept enabled
440 		 * when the DSP enters D0I3 while the system is in S0
441 		 * for debug purpose.
442 		 */
443 		if (!sdev->fw_trace_is_supported ||
444 		    !hda_enable_trace_D0I3_S0 ||
445 		    sdev->system_suspend_target != SOF_SUSPEND_NONE)
446 			flags = HDA_PM_NO_DMA_TRACE;
447 	} else {
448 		/* prevent power gating in D0I0 */
449 		flags = HDA_PM_PPG;
450 	}
451 
452 	/* update D0I3C register */
453 	ret = hda_dsp_update_d0i3c_register(sdev, value);
454 	if (ret < 0)
455 		return ret;
456 
457 	/*
458 	 * Notify the DSP of the state change.
459 	 * If this IPC fails, revert the D0I3C register update in order
460 	 * to prevent partial state change.
461 	 */
462 	ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
463 	if (ret < 0) {
464 		dev_err(sdev->dev,
465 			"error: PM_GATE ipc error %d\n", ret);
466 		goto revert;
467 	}
468 
469 	return ret;
470 
471 revert:
472 	/* fallback to the previous register value */
473 	value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
474 
475 	/*
476 	 * This can fail but return the IPC error to signal that
477 	 * the state change failed.
478 	 */
479 	hda_dsp_update_d0i3c_register(sdev, value);
480 
481 	return ret;
482 }
483 
484 /* helper to log DSP state */
485 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
486 {
487 	switch (sdev->dsp_power_state.state) {
488 	case SOF_DSP_PM_D0:
489 		switch (sdev->dsp_power_state.substate) {
490 		case SOF_HDA_DSP_PM_D0I0:
491 			dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
492 			break;
493 		case SOF_HDA_DSP_PM_D0I3:
494 			dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
495 			break;
496 		default:
497 			dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
498 				sdev->dsp_power_state.substate);
499 			break;
500 		}
501 		break;
502 	case SOF_DSP_PM_D1:
503 		dev_dbg(sdev->dev, "Current DSP power state: D1\n");
504 		break;
505 	case SOF_DSP_PM_D2:
506 		dev_dbg(sdev->dev, "Current DSP power state: D2\n");
507 		break;
508 	case SOF_DSP_PM_D3:
509 		dev_dbg(sdev->dev, "Current DSP power state: D3\n");
510 		break;
511 	default:
512 		dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
513 			sdev->dsp_power_state.state);
514 		break;
515 	}
516 }
517 
518 /*
519  * All DSP power state transitions are initiated by the driver.
520  * If the requested state change fails, the error is simply returned.
521  * Further state transitions are attempted only when the set_power_save() op
522  * is called again either because of a new IPC sent to the DSP or
523  * during system suspend/resume.
524  */
525 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
526 			    const struct sof_dsp_power_state *target_state)
527 {
528 	int ret = 0;
529 
530 	/*
531 	 * When the DSP is already in D0I3 and the target state is D0I3,
532 	 * it could be the case that the DSP is in D0I3 during S0
533 	 * and the system is suspending to S0Ix. Therefore,
534 	 * hda_dsp_set_D0_state() must be called to disable trace DMA
535 	 * by sending the PM_GATE IPC to the FW.
536 	 */
537 	if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
538 	    sdev->system_suspend_target == SOF_SUSPEND_S0IX)
539 		goto set_state;
540 
541 	/*
542 	 * For all other cases, return without doing anything if
543 	 * the DSP is already in the target state.
544 	 */
545 	if (target_state->state == sdev->dsp_power_state.state &&
546 	    target_state->substate == sdev->dsp_power_state.substate)
547 		return 0;
548 
549 set_state:
550 	switch (target_state->state) {
551 	case SOF_DSP_PM_D0:
552 		ret = hda_dsp_set_D0_state(sdev, target_state);
553 		break;
554 	case SOF_DSP_PM_D3:
555 		/* The only allowed transition is: D0I0 -> D3 */
556 		if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
557 		    sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
558 			break;
559 
560 		dev_err(sdev->dev,
561 			"error: transition from %d to %d not allowed\n",
562 			sdev->dsp_power_state.state, target_state->state);
563 		return -EINVAL;
564 	default:
565 		dev_err(sdev->dev, "error: target state unsupported %d\n",
566 			target_state->state);
567 		return -EINVAL;
568 	}
569 	if (ret < 0) {
570 		dev_err(sdev->dev,
571 			"failed to set requested target DSP state %d substate %d\n",
572 			target_state->state, target_state->substate);
573 		return ret;
574 	}
575 
576 	sdev->dsp_power_state = *target_state;
577 	hda_dsp_state_log(sdev);
578 	return ret;
579 }
580 
581 /*
582  * Audio DSP states may transform as below:-
583  *
584  *                                         Opportunistic D0I3 in S0
585  *     Runtime    +---------------------+  Delayed D0i3 work timeout
586  *     suspend    |                     +--------------------+
587  *   +------------+       D0I0(active)  |                    |
588  *   |            |                     <---------------+    |
589  *   |   +-------->                     |    New IPC	|    |
590  *   |   |Runtime +--^--+---------^--+--+ (via mailbox)	|    |
591  *   |   |resume     |  |         |  |			|    |
592  *   |   |           |  |         |  |			|    |
593  *   |   |     System|  |         |  |			|    |
594  *   |   |     resume|  | S3/S0IX |  |                  |    |
595  *   |   |	     |  | suspend |  | S0IX             |    |
596  *   |   |           |  |         |  |suspend           |    |
597  *   |   |           |  |         |  |                  |    |
598  *   |   |           |  |         |  |                  |    |
599  * +-v---+-----------+--v-------+ |  |           +------+----v----+
600  * |                            | |  +----------->                |
601  * |       D3 (suspended)       | |              |      D0I3      |
602  * |                            | +--------------+                |
603  * |                            |  System resume |                |
604  * +----------------------------+		 +----------------+
605  *
606  * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
607  *		 ignored the suspend trigger. Otherwise the DSP
608  *		 is in D3.
609  */
610 
611 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
612 {
613 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
614 	const struct sof_intel_dsp_desc *chip = hda->desc;
615 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
616 	struct hdac_bus *bus = sof_to_bus(sdev);
617 #endif
618 	int ret, j;
619 
620 	/*
621 	 * The memory used for IMR boot loses its content in deeper than S3 state
622 	 * We must not try IMR boot on next power up (as it will fail).
623 	 *
624 	 * In case of firmware crash or boot failure set the skip_imr_boot to true
625 	 * as well in order to try to re-load the firmware to do a 'cold' boot.
626 	 */
627 	if (sdev->system_suspend_target > SOF_SUSPEND_S3 ||
628 	    sdev->fw_state == SOF_FW_CRASHED ||
629 	    sdev->fw_state == SOF_FW_BOOT_FAILED)
630 		hda->skip_imr_boot = true;
631 
632 	ret = chip->disable_interrupts(sdev);
633 	if (ret < 0)
634 		return ret;
635 
636 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
637 	hda_codec_jack_wake_enable(sdev, runtime_suspend);
638 
639 	/* power down all hda link */
640 	snd_hdac_ext_bus_link_power_down_all(bus);
641 #endif
642 
643 	ret = chip->power_down_dsp(sdev);
644 	if (ret < 0) {
645 		dev_err(sdev->dev, "failed to power down DSP during suspend\n");
646 		return ret;
647 	}
648 
649 	/* reset ref counts for all cores */
650 	for (j = 0; j < chip->cores_num; j++)
651 		sdev->dsp_core_ref_count[j] = 0;
652 
653 	/* disable ppcap interrupt */
654 	hda_dsp_ctrl_ppcap_enable(sdev, false);
655 	hda_dsp_ctrl_ppcap_int_enable(sdev, false);
656 
657 	/* disable hda bus irq and streams */
658 	hda_dsp_ctrl_stop_chip(sdev);
659 
660 	/* disable LP retention mode */
661 	snd_sof_pci_update_bits(sdev, PCI_PGCTL,
662 				PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
663 
664 	/* reset controller */
665 	ret = hda_dsp_ctrl_link_reset(sdev, true);
666 	if (ret < 0) {
667 		dev_err(sdev->dev,
668 			"error: failed to reset controller during suspend\n");
669 		return ret;
670 	}
671 
672 	/* display codec can powered off after link reset */
673 	hda_codec_i915_display_power(sdev, false);
674 
675 	return 0;
676 }
677 
678 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
679 {
680 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
681 	struct hdac_bus *bus = sof_to_bus(sdev);
682 	struct hdac_ext_link *hlink = NULL;
683 #endif
684 	int ret;
685 
686 	/* display codec must be powered before link reset */
687 	hda_codec_i915_display_power(sdev, true);
688 
689 	/*
690 	 * clear TCSEL to clear playback on some HD Audio
691 	 * codecs. PCI TCSEL is defined in the Intel manuals.
692 	 */
693 	snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
694 
695 	/* reset and start hda controller */
696 	ret = hda_dsp_ctrl_init_chip(sdev, true);
697 	if (ret < 0) {
698 		dev_err(sdev->dev,
699 			"error: failed to start controller after resume\n");
700 		goto cleanup;
701 	}
702 
703 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
704 	/* check jack status */
705 	if (runtime_resume) {
706 		hda_codec_jack_wake_enable(sdev, false);
707 		if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
708 			hda_codec_jack_check(sdev);
709 	}
710 
711 	/* turn off the links that were off before suspend */
712 	list_for_each_entry(hlink, &bus->hlink_list, list) {
713 		if (!hlink->ref_count)
714 			snd_hdac_ext_bus_link_power_down(hlink);
715 	}
716 
717 	/* check dma status and clean up CORB/RIRB buffers */
718 	if (!bus->cmd_dma_state)
719 		snd_hdac_bus_stop_cmd_io(bus);
720 #endif
721 
722 	/* enable ppcap interrupt */
723 	hda_dsp_ctrl_ppcap_enable(sdev, true);
724 	hda_dsp_ctrl_ppcap_int_enable(sdev, true);
725 
726 cleanup:
727 	/* display codec can powered off after controller init */
728 	hda_codec_i915_display_power(sdev, false);
729 
730 	return 0;
731 }
732 
733 int hda_dsp_resume(struct snd_sof_dev *sdev)
734 {
735 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
736 	struct pci_dev *pci = to_pci_dev(sdev->dev);
737 	const struct sof_dsp_power_state target_state = {
738 		.state = SOF_DSP_PM_D0,
739 		.substate = SOF_HDA_DSP_PM_D0I0,
740 	};
741 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
742 	struct hdac_bus *bus = sof_to_bus(sdev);
743 	struct hdac_ext_link *hlink = NULL;
744 #endif
745 	int ret;
746 
747 	/* resume from D0I3 */
748 	if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
749 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
750 		/* power up links that were active before suspend */
751 		list_for_each_entry(hlink, &bus->hlink_list, list) {
752 			if (hlink->ref_count) {
753 				ret = snd_hdac_ext_bus_link_power_up(hlink);
754 				if (ret < 0) {
755 					dev_err(sdev->dev,
756 						"error %d in %s: failed to power up links",
757 						ret, __func__);
758 					return ret;
759 				}
760 			}
761 		}
762 
763 		/* set up CORB/RIRB buffers if was on before suspend */
764 		if (bus->cmd_dma_state)
765 			snd_hdac_bus_init_cmd_io(bus);
766 #endif
767 
768 		/* Set DSP power state */
769 		ret = snd_sof_dsp_set_power_state(sdev, &target_state);
770 		if (ret < 0) {
771 			dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
772 				target_state.state, target_state.substate);
773 			return ret;
774 		}
775 
776 		/* restore L1SEN bit */
777 		if (hda->l1_support_changed)
778 			snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
779 						HDA_VS_INTEL_EM2,
780 						HDA_VS_INTEL_EM2_L1SEN, 0);
781 
782 		/* restore and disable the system wakeup */
783 		pci_restore_state(pci);
784 		disable_irq_wake(pci->irq);
785 		return 0;
786 	}
787 
788 	/* init hda controller. DSP cores will be powered up during fw boot */
789 	ret = hda_resume(sdev, false);
790 	if (ret < 0)
791 		return ret;
792 
793 	return snd_sof_dsp_set_power_state(sdev, &target_state);
794 }
795 
796 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
797 {
798 	const struct sof_dsp_power_state target_state = {
799 		.state = SOF_DSP_PM_D0,
800 	};
801 	int ret;
802 
803 	/* init hda controller. DSP cores will be powered up during fw boot */
804 	ret = hda_resume(sdev, true);
805 	if (ret < 0)
806 		return ret;
807 
808 	return snd_sof_dsp_set_power_state(sdev, &target_state);
809 }
810 
811 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
812 {
813 	struct hdac_bus *hbus = sof_to_bus(sdev);
814 
815 	if (hbus->codec_powered) {
816 		dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
817 			(unsigned int)hbus->codec_powered);
818 		return -EBUSY;
819 	}
820 
821 	return 0;
822 }
823 
824 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
825 {
826 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
827 	const struct sof_dsp_power_state target_state = {
828 		.state = SOF_DSP_PM_D3,
829 	};
830 	int ret;
831 
832 	/* cancel any attempt for DSP D0I3 */
833 	cancel_delayed_work_sync(&hda->d0i3_work);
834 
835 	/* stop hda controller and power dsp off */
836 	ret = hda_suspend(sdev, true);
837 	if (ret < 0)
838 		return ret;
839 
840 	return snd_sof_dsp_set_power_state(sdev, &target_state);
841 }
842 
843 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
844 {
845 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
846 	struct hdac_bus *bus = sof_to_bus(sdev);
847 	struct pci_dev *pci = to_pci_dev(sdev->dev);
848 	const struct sof_dsp_power_state target_dsp_state = {
849 		.state = target_state,
850 		.substate = target_state == SOF_DSP_PM_D0 ?
851 				SOF_HDA_DSP_PM_D0I3 : 0,
852 	};
853 	int ret;
854 
855 	/* cancel any attempt for DSP D0I3 */
856 	cancel_delayed_work_sync(&hda->d0i3_work);
857 
858 	if (target_state == SOF_DSP_PM_D0) {
859 		/* Set DSP power state */
860 		ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
861 		if (ret < 0) {
862 			dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
863 				target_dsp_state.state,
864 				target_dsp_state.substate);
865 			return ret;
866 		}
867 
868 		/* enable L1SEN to make sure the system can enter S0Ix */
869 		hda->l1_support_changed =
870 			snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
871 						HDA_VS_INTEL_EM2,
872 						HDA_VS_INTEL_EM2_L1SEN,
873 						HDA_VS_INTEL_EM2_L1SEN);
874 
875 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
876 		/* stop the CORB/RIRB DMA if it is On */
877 		if (bus->cmd_dma_state)
878 			snd_hdac_bus_stop_cmd_io(bus);
879 
880 		/* no link can be powered in s0ix state */
881 		ret = snd_hdac_ext_bus_link_power_down_all(bus);
882 		if (ret < 0) {
883 			dev_err(sdev->dev,
884 				"error %d in %s: failed to power down links",
885 				ret, __func__);
886 			return ret;
887 		}
888 #endif
889 
890 		/* enable the system waking up via IPC IRQ */
891 		enable_irq_wake(pci->irq);
892 		pci_save_state(pci);
893 		return 0;
894 	}
895 
896 	/* stop hda controller and power dsp off */
897 	ret = hda_suspend(sdev, false);
898 	if (ret < 0) {
899 		dev_err(bus->dev, "error: suspending dsp\n");
900 		return ret;
901 	}
902 
903 	return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
904 }
905 
906 int hda_dsp_shutdown(struct snd_sof_dev *sdev)
907 {
908 	sdev->system_suspend_target = SOF_SUSPEND_S3;
909 	return snd_sof_suspend(sdev->dev);
910 }
911 
912 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
913 {
914 	int ret;
915 
916 	/* make sure all DAI resources are freed */
917 	ret = hda_dsp_dais_suspend(sdev);
918 	if (ret < 0)
919 		dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__);
920 
921 	return ret;
922 }
923 
924 void hda_dsp_d0i3_work(struct work_struct *work)
925 {
926 	struct sof_intel_hda_dev *hdev = container_of(work,
927 						      struct sof_intel_hda_dev,
928 						      d0i3_work.work);
929 	struct hdac_bus *bus = &hdev->hbus.core;
930 	struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
931 	struct sof_dsp_power_state target_state = {
932 		.state = SOF_DSP_PM_D0,
933 		.substate = SOF_HDA_DSP_PM_D0I3,
934 	};
935 	int ret;
936 
937 	/* DSP can enter D0I3 iff only D0I3-compatible streams are active */
938 	if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
939 		/* remain in D0I0 */
940 		return;
941 
942 	/* This can fail but error cannot be propagated */
943 	ret = snd_sof_dsp_set_power_state(sdev, &target_state);
944 	if (ret < 0)
945 		dev_err_ratelimited(sdev->dev,
946 				    "error: failed to set DSP state %d substate %d\n",
947 				    target_state.state, target_state.substate);
948 }
949 
950 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
951 {
952 	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
953 	int ret, ret1;
954 
955 	/* power up core */
956 	ret = hda_dsp_enable_core(sdev, BIT(core));
957 	if (ret < 0) {
958 		dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
959 			core, ret);
960 		return ret;
961 	}
962 
963 	/* No need to send IPC for primary core or if FW boot is not complete */
964 	if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
965 		return 0;
966 
967 	/* No need to continue the set_core_state ops is not available */
968 	if (!pm_ops->set_core_state)
969 		return 0;
970 
971 	/* Now notify DSP for secondary cores */
972 	ret = pm_ops->set_core_state(sdev, core, true);
973 	if (ret < 0) {
974 		dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
975 			core, ret);
976 		goto power_down;
977 	}
978 
979 	return ret;
980 
981 power_down:
982 	/* power down core if it is host managed and return the original error if this fails too */
983 	ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
984 	if (ret1 < 0)
985 		dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
986 
987 	return ret;
988 }
989 
990 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
991 {
992 	hda_sdw_int_enable(sdev, false);
993 	hda_dsp_ipc_int_disable(sdev);
994 
995 	return 0;
996 }
997