1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include "../sof-audio.h" 22 #include "../ops.h" 23 #include "hda.h" 24 #include "hda-ipc.h" 25 26 static bool hda_enable_trace_D0I3_S0; 27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 29 MODULE_PARM_DESC(enable_trace_D0I3_S0, 30 "SOF HDA enable trace when the DSP is in D0I3 in S0"); 31 #endif 32 33 /* 34 * DSP Core control. 35 */ 36 37 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 38 { 39 u32 adspcs; 40 u32 reset; 41 int ret; 42 43 /* set reset bits for cores */ 44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 46 HDA_DSP_REG_ADSPCS, 47 reset, reset), 48 49 /* poll with timeout to check if operation successful */ 50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 51 HDA_DSP_REG_ADSPCS, adspcs, 52 ((adspcs & reset) == reset), 53 HDA_DSP_REG_POLL_INTERVAL_US, 54 HDA_DSP_RESET_TIMEOUT_US); 55 if (ret < 0) { 56 dev_err(sdev->dev, 57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 58 __func__); 59 return ret; 60 } 61 62 /* has core entered reset ? */ 63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 64 HDA_DSP_REG_ADSPCS); 65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 67 dev_err(sdev->dev, 68 "error: reset enter failed: core_mask %x adspcs 0x%x\n", 69 core_mask, adspcs); 70 ret = -EIO; 71 } 72 73 return ret; 74 } 75 76 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 77 { 78 unsigned int crst; 79 u32 adspcs; 80 int ret; 81 82 /* clear reset bits for cores */ 83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 84 HDA_DSP_REG_ADSPCS, 85 HDA_DSP_ADSPCS_CRST_MASK(core_mask), 86 0); 87 88 /* poll with timeout to check if operation successful */ 89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 91 HDA_DSP_REG_ADSPCS, adspcs, 92 !(adspcs & crst), 93 HDA_DSP_REG_POLL_INTERVAL_US, 94 HDA_DSP_RESET_TIMEOUT_US); 95 96 if (ret < 0) { 97 dev_err(sdev->dev, 98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 99 __func__); 100 return ret; 101 } 102 103 /* has core left reset ? */ 104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 105 HDA_DSP_REG_ADSPCS); 106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 107 dev_err(sdev->dev, 108 "error: reset leave failed: core_mask %x adspcs 0x%x\n", 109 core_mask, adspcs); 110 ret = -EIO; 111 } 112 113 return ret; 114 } 115 116 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 117 { 118 /* stall core */ 119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 120 HDA_DSP_REG_ADSPCS, 121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 123 124 /* set reset state */ 125 return hda_dsp_core_reset_enter(sdev, core_mask); 126 } 127 128 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 129 { 130 int ret; 131 132 /* leave reset state */ 133 ret = hda_dsp_core_reset_leave(sdev, core_mask); 134 if (ret < 0) 135 return ret; 136 137 /* run core */ 138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 140 HDA_DSP_REG_ADSPCS, 141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 142 0); 143 144 /* is core now running ? */ 145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 146 hda_dsp_core_stall_reset(sdev, core_mask); 147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 148 core_mask); 149 ret = -EIO; 150 } 151 152 return ret; 153 } 154 155 /* 156 * Power Management. 157 */ 158 159 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 160 { 161 unsigned int cpa; 162 u32 adspcs; 163 int ret; 164 165 /* update bits */ 166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 167 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 168 HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 169 170 /* poll with timeout to check if operation successful */ 171 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 173 HDA_DSP_REG_ADSPCS, adspcs, 174 (adspcs & cpa) == cpa, 175 HDA_DSP_REG_POLL_INTERVAL_US, 176 HDA_DSP_RESET_TIMEOUT_US); 177 if (ret < 0) { 178 dev_err(sdev->dev, 179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 180 __func__); 181 return ret; 182 } 183 184 /* did core power up ? */ 185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 186 HDA_DSP_REG_ADSPCS); 187 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 188 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 189 dev_err(sdev->dev, 190 "error: power up core failed core_mask %xadspcs 0x%x\n", 191 core_mask, adspcs); 192 ret = -EIO; 193 } 194 195 return ret; 196 } 197 198 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 199 { 200 u32 adspcs; 201 int ret; 202 203 /* update bits */ 204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 205 HDA_DSP_REG_ADSPCS, 206 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 207 208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 209 HDA_DSP_REG_ADSPCS, adspcs, 210 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)), 211 HDA_DSP_REG_POLL_INTERVAL_US, 212 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 213 if (ret < 0) 214 dev_err(sdev->dev, 215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 216 __func__); 217 218 return ret; 219 } 220 221 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 222 unsigned int core_mask) 223 { 224 int val; 225 bool is_enable; 226 227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 228 229 is_enable = (val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) && 230 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) && 231 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 232 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 233 234 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 235 is_enable, core_mask); 236 237 return is_enable; 238 } 239 240 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 241 { 242 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 243 const struct sof_intel_dsp_desc *chip = hda->desc; 244 int ret; 245 246 /* restrict core_mask to host managed cores mask */ 247 core_mask &= chip->host_managed_cores_mask; 248 249 /* return if core_mask is not valid or cores are already enabled */ 250 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask)) 251 return 0; 252 253 /* power up */ 254 ret = hda_dsp_core_power_up(sdev, core_mask); 255 if (ret < 0) { 256 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 257 core_mask); 258 return ret; 259 } 260 261 return hda_dsp_core_run(sdev, core_mask); 262 } 263 264 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 265 unsigned int core_mask) 266 { 267 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 268 const struct sof_intel_dsp_desc *chip = hda->desc; 269 int ret; 270 271 /* restrict core_mask to host managed cores mask */ 272 core_mask &= chip->host_managed_cores_mask; 273 274 /* return if core_mask is not valid */ 275 if (!core_mask) 276 return 0; 277 278 /* place core in reset prior to power down */ 279 ret = hda_dsp_core_stall_reset(sdev, core_mask); 280 if (ret < 0) { 281 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 282 core_mask); 283 return ret; 284 } 285 286 /* power down core */ 287 ret = hda_dsp_core_power_down(sdev, core_mask); 288 if (ret < 0) { 289 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 290 core_mask, ret); 291 return ret; 292 } 293 294 /* make sure we are in OFF state */ 295 if (hda_dsp_core_is_enabled(sdev, core_mask)) { 296 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 297 core_mask, ret); 298 ret = -EIO; 299 } 300 301 return ret; 302 } 303 304 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 305 { 306 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 307 const struct sof_intel_dsp_desc *chip = hda->desc; 308 309 /* enable IPC DONE and BUSY interrupts */ 310 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 311 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 312 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 313 314 /* enable IPC interrupt */ 315 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 316 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 317 } 318 319 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 320 { 321 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 322 const struct sof_intel_dsp_desc *chip = hda->desc; 323 324 /* disable IPC interrupt */ 325 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 326 HDA_DSP_ADSPIC_IPC, 0); 327 328 /* disable IPC BUSY and DONE interrupt */ 329 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 330 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 331 } 332 333 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 334 { 335 struct hdac_bus *bus = sof_to_bus(sdev); 336 int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 337 338 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) { 339 if (!retry--) 340 return -ETIMEDOUT; 341 usleep_range(10, 15); 342 } 343 344 return 0; 345 } 346 347 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 348 { 349 struct sof_ipc_pm_gate pm_gate; 350 struct sof_ipc_reply reply; 351 352 memset(&pm_gate, 0, sizeof(pm_gate)); 353 354 /* configure pm_gate ipc message */ 355 pm_gate.hdr.size = sizeof(pm_gate); 356 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE; 357 pm_gate.flags = flags; 358 359 /* send pm_gate ipc to dsp */ 360 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd, 361 &pm_gate, sizeof(pm_gate), &reply, 362 sizeof(reply)); 363 } 364 365 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 366 { 367 struct hdac_bus *bus = sof_to_bus(sdev); 368 int ret; 369 370 /* Write to D0I3C after Command-In-Progress bit is cleared */ 371 ret = hda_dsp_wait_d0i3c_done(sdev); 372 if (ret < 0) { 373 dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); 374 return ret; 375 } 376 377 /* Update D0I3C register */ 378 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); 379 380 /* Wait for cmd in progress to be cleared before exiting the function */ 381 ret = hda_dsp_wait_d0i3c_done(sdev); 382 if (ret < 0) { 383 dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); 384 return ret; 385 } 386 387 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n", 388 snd_hdac_chip_readb(bus, VS_D0I3C)); 389 390 return 0; 391 } 392 393 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 394 const struct sof_dsp_power_state *target_state) 395 { 396 u32 flags = 0; 397 int ret; 398 u8 value = 0; 399 400 /* 401 * Sanity check for illegal state transitions 402 * The only allowed transitions are: 403 * 1. D3 -> D0I0 404 * 2. D0I0 -> D0I3 405 * 3. D0I3 -> D0I0 406 */ 407 switch (sdev->dsp_power_state.state) { 408 case SOF_DSP_PM_D0: 409 /* Follow the sequence below for D0 substate transitions */ 410 break; 411 case SOF_DSP_PM_D3: 412 /* Follow regular flow for D3 -> D0 transition */ 413 return 0; 414 default: 415 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 416 sdev->dsp_power_state.state, target_state->state); 417 return -EINVAL; 418 } 419 420 /* Set flags and register value for D0 target substate */ 421 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 422 value = SOF_HDA_VS_D0I3C_I3; 423 424 /* 425 * Trace DMA need to be disabled when the DSP enters 426 * D0I3 for S0Ix suspend, but it can be kept enabled 427 * when the DSP enters D0I3 while the system is in S0 428 * for debug purpose. 429 */ 430 if (!sdev->dtrace_is_supported || 431 !hda_enable_trace_D0I3_S0 || 432 sdev->system_suspend_target != SOF_SUSPEND_NONE) 433 flags = HDA_PM_NO_DMA_TRACE; 434 } else { 435 /* prevent power gating in D0I0 */ 436 flags = HDA_PM_PPG; 437 } 438 439 /* update D0I3C register */ 440 ret = hda_dsp_update_d0i3c_register(sdev, value); 441 if (ret < 0) 442 return ret; 443 444 /* 445 * Notify the DSP of the state change. 446 * If this IPC fails, revert the D0I3C register update in order 447 * to prevent partial state change. 448 */ 449 ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 450 if (ret < 0) { 451 dev_err(sdev->dev, 452 "error: PM_GATE ipc error %d\n", ret); 453 goto revert; 454 } 455 456 return ret; 457 458 revert: 459 /* fallback to the previous register value */ 460 value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 461 462 /* 463 * This can fail but return the IPC error to signal that 464 * the state change failed. 465 */ 466 hda_dsp_update_d0i3c_register(sdev, value); 467 468 return ret; 469 } 470 471 /* helper to log DSP state */ 472 static void hda_dsp_state_log(struct snd_sof_dev *sdev) 473 { 474 switch (sdev->dsp_power_state.state) { 475 case SOF_DSP_PM_D0: 476 switch (sdev->dsp_power_state.substate) { 477 case SOF_HDA_DSP_PM_D0I0: 478 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); 479 break; 480 case SOF_HDA_DSP_PM_D0I3: 481 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); 482 break; 483 default: 484 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", 485 sdev->dsp_power_state.substate); 486 break; 487 } 488 break; 489 case SOF_DSP_PM_D1: 490 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); 491 break; 492 case SOF_DSP_PM_D2: 493 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); 494 break; 495 case SOF_DSP_PM_D3_HOT: 496 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n"); 497 break; 498 case SOF_DSP_PM_D3: 499 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); 500 break; 501 case SOF_DSP_PM_D3_COLD: 502 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n"); 503 break; 504 default: 505 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", 506 sdev->dsp_power_state.state); 507 break; 508 } 509 } 510 511 /* 512 * All DSP power state transitions are initiated by the driver. 513 * If the requested state change fails, the error is simply returned. 514 * Further state transitions are attempted only when the set_power_save() op 515 * is called again either because of a new IPC sent to the DSP or 516 * during system suspend/resume. 517 */ 518 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 519 const struct sof_dsp_power_state *target_state) 520 { 521 int ret = 0; 522 523 /* 524 * When the DSP is already in D0I3 and the target state is D0I3, 525 * it could be the case that the DSP is in D0I3 during S0 526 * and the system is suspending to S0Ix. Therefore, 527 * hda_dsp_set_D0_state() must be called to disable trace DMA 528 * by sending the PM_GATE IPC to the FW. 529 */ 530 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 531 sdev->system_suspend_target == SOF_SUSPEND_S0IX) 532 goto set_state; 533 534 /* 535 * For all other cases, return without doing anything if 536 * the DSP is already in the target state. 537 */ 538 if (target_state->state == sdev->dsp_power_state.state && 539 target_state->substate == sdev->dsp_power_state.substate) 540 return 0; 541 542 set_state: 543 switch (target_state->state) { 544 case SOF_DSP_PM_D0: 545 ret = hda_dsp_set_D0_state(sdev, target_state); 546 break; 547 case SOF_DSP_PM_D3: 548 /* The only allowed transition is: D0I0 -> D3 */ 549 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 550 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 551 break; 552 553 dev_err(sdev->dev, 554 "error: transition from %d to %d not allowed\n", 555 sdev->dsp_power_state.state, target_state->state); 556 return -EINVAL; 557 default: 558 dev_err(sdev->dev, "error: target state unsupported %d\n", 559 target_state->state); 560 return -EINVAL; 561 } 562 if (ret < 0) { 563 dev_err(sdev->dev, 564 "failed to set requested target DSP state %d substate %d\n", 565 target_state->state, target_state->substate); 566 return ret; 567 } 568 569 sdev->dsp_power_state = *target_state; 570 hda_dsp_state_log(sdev); 571 return ret; 572 } 573 574 /* 575 * Audio DSP states may transform as below:- 576 * 577 * Opportunistic D0I3 in S0 578 * Runtime +---------------------+ Delayed D0i3 work timeout 579 * suspend | +--------------------+ 580 * +------------+ D0I0(active) | | 581 * | | <---------------+ | 582 * | +--------> | New IPC | | 583 * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 584 * | |resume | | | | | | 585 * | | | | | | | | 586 * | | System| | | | | | 587 * | | resume| | S3/S0IX | | | | 588 * | | | | suspend | | S0IX | | 589 * | | | | | |suspend | | 590 * | | | | | | | | 591 * | | | | | | | | 592 * +-v---+-----------+--v-------+ | | +------+----v----+ 593 * | | | +-----------> | 594 * | D3 (suspended) | | | D0I3 | 595 * | | +--------------+ | 596 * | | System resume | | 597 * +----------------------------+ +----------------+ 598 * 599 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 600 * ignored the suspend trigger. Otherwise the DSP 601 * is in D3. 602 */ 603 604 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 605 { 606 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 607 const struct sof_intel_dsp_desc *chip = hda->desc; 608 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 609 struct hdac_bus *bus = sof_to_bus(sdev); 610 #endif 611 int ret; 612 613 hda_sdw_int_enable(sdev, false); 614 615 /* disable IPC interrupts */ 616 hda_dsp_ipc_int_disable(sdev); 617 618 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 619 if (runtime_suspend) 620 hda_codec_jack_wake_enable(sdev); 621 622 /* power down all hda link */ 623 snd_hdac_ext_bus_link_power_down_all(bus); 624 #endif 625 626 /* power down DSP */ 627 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 628 if (ret < 0) { 629 dev_err(sdev->dev, 630 "error: failed to power down core during suspend\n"); 631 return ret; 632 } 633 634 /* disable ppcap interrupt */ 635 hda_dsp_ctrl_ppcap_enable(sdev, false); 636 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 637 638 /* disable hda bus irq and streams */ 639 hda_dsp_ctrl_stop_chip(sdev); 640 641 /* disable LP retention mode */ 642 snd_sof_pci_update_bits(sdev, PCI_PGCTL, 643 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 644 645 /* reset controller */ 646 ret = hda_dsp_ctrl_link_reset(sdev, true); 647 if (ret < 0) { 648 dev_err(sdev->dev, 649 "error: failed to reset controller during suspend\n"); 650 return ret; 651 } 652 653 /* display codec can powered off after link reset */ 654 hda_codec_i915_display_power(sdev, false); 655 656 return 0; 657 } 658 659 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 660 { 661 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 662 struct hdac_bus *bus = sof_to_bus(sdev); 663 struct hdac_ext_link *hlink = NULL; 664 #endif 665 int ret; 666 667 /* display codec must be powered before link reset */ 668 hda_codec_i915_display_power(sdev, true); 669 670 /* 671 * clear TCSEL to clear playback on some HD Audio 672 * codecs. PCI TCSEL is defined in the Intel manuals. 673 */ 674 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 675 676 /* reset and start hda controller */ 677 ret = hda_dsp_ctrl_init_chip(sdev, true); 678 if (ret < 0) { 679 dev_err(sdev->dev, 680 "error: failed to start controller after resume\n"); 681 return ret; 682 } 683 684 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 685 /* check jack status */ 686 if (runtime_resume) 687 hda_codec_jack_check(sdev); 688 689 /* turn off the links that were off before suspend */ 690 list_for_each_entry(hlink, &bus->hlink_list, list) { 691 if (!hlink->ref_count) 692 snd_hdac_ext_bus_link_power_down(hlink); 693 } 694 695 /* check dma status and clean up CORB/RIRB buffers */ 696 if (!bus->cmd_dma_state) 697 snd_hdac_bus_stop_cmd_io(bus); 698 #endif 699 700 /* enable ppcap interrupt */ 701 hda_dsp_ctrl_ppcap_enable(sdev, true); 702 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 703 704 return 0; 705 } 706 707 int hda_dsp_resume(struct snd_sof_dev *sdev) 708 { 709 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 710 struct pci_dev *pci = to_pci_dev(sdev->dev); 711 const struct sof_dsp_power_state target_state = { 712 .state = SOF_DSP_PM_D0, 713 .substate = SOF_HDA_DSP_PM_D0I0, 714 }; 715 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 716 struct hdac_bus *bus = sof_to_bus(sdev); 717 struct hdac_ext_link *hlink = NULL; 718 #endif 719 int ret; 720 721 /* resume from D0I3 */ 722 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 723 hda_codec_i915_display_power(sdev, true); 724 725 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 726 /* power up links that were active before suspend */ 727 list_for_each_entry(hlink, &bus->hlink_list, list) { 728 if (hlink->ref_count) { 729 ret = snd_hdac_ext_bus_link_power_up(hlink); 730 if (ret < 0) { 731 dev_dbg(sdev->dev, 732 "error %x in %s: failed to power up links", 733 ret, __func__); 734 return ret; 735 } 736 } 737 } 738 739 /* set up CORB/RIRB buffers if was on before suspend */ 740 if (bus->cmd_dma_state) 741 snd_hdac_bus_init_cmd_io(bus); 742 #endif 743 744 /* Set DSP power state */ 745 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 746 if (ret < 0) { 747 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 748 target_state.state, target_state.substate); 749 return ret; 750 } 751 752 /* restore L1SEN bit */ 753 if (hda->l1_support_changed) 754 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 755 HDA_VS_INTEL_EM2, 756 HDA_VS_INTEL_EM2_L1SEN, 0); 757 758 /* restore and disable the system wakeup */ 759 pci_restore_state(pci); 760 disable_irq_wake(pci->irq); 761 return 0; 762 } 763 764 /* init hda controller. DSP cores will be powered up during fw boot */ 765 ret = hda_resume(sdev, false); 766 if (ret < 0) 767 return ret; 768 769 return snd_sof_dsp_set_power_state(sdev, &target_state); 770 } 771 772 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 773 { 774 const struct sof_dsp_power_state target_state = { 775 .state = SOF_DSP_PM_D0, 776 }; 777 int ret; 778 779 /* init hda controller. DSP cores will be powered up during fw boot */ 780 ret = hda_resume(sdev, true); 781 if (ret < 0) 782 return ret; 783 784 return snd_sof_dsp_set_power_state(sdev, &target_state); 785 } 786 787 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 788 { 789 struct hdac_bus *hbus = sof_to_bus(sdev); 790 791 if (hbus->codec_powered) { 792 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 793 (unsigned int)hbus->codec_powered); 794 return -EBUSY; 795 } 796 797 return 0; 798 } 799 800 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 801 { 802 const struct sof_dsp_power_state target_state = { 803 .state = SOF_DSP_PM_D3, 804 }; 805 int ret; 806 807 /* stop hda controller and power dsp off */ 808 ret = hda_suspend(sdev, true); 809 if (ret < 0) 810 return ret; 811 812 return snd_sof_dsp_set_power_state(sdev, &target_state); 813 } 814 815 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 816 { 817 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 818 struct hdac_bus *bus = sof_to_bus(sdev); 819 struct pci_dev *pci = to_pci_dev(sdev->dev); 820 const struct sof_dsp_power_state target_dsp_state = { 821 .state = target_state, 822 .substate = target_state == SOF_DSP_PM_D0 ? 823 SOF_HDA_DSP_PM_D0I3 : 0, 824 }; 825 int ret; 826 827 /* cancel any attempt for DSP D0I3 */ 828 cancel_delayed_work_sync(&hda->d0i3_work); 829 830 if (target_state == SOF_DSP_PM_D0) { 831 /* we can't keep a wakeref to display driver at suspend */ 832 hda_codec_i915_display_power(sdev, false); 833 834 /* Set DSP power state */ 835 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 836 if (ret < 0) { 837 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 838 target_dsp_state.state, 839 target_dsp_state.substate); 840 return ret; 841 } 842 843 /* enable L1SEN to make sure the system can enter S0Ix */ 844 hda->l1_support_changed = 845 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 846 HDA_VS_INTEL_EM2, 847 HDA_VS_INTEL_EM2_L1SEN, 848 HDA_VS_INTEL_EM2_L1SEN); 849 850 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 851 /* stop the CORB/RIRB DMA if it is On */ 852 if (bus->cmd_dma_state) 853 snd_hdac_bus_stop_cmd_io(bus); 854 855 /* no link can be powered in s0ix state */ 856 ret = snd_hdac_ext_bus_link_power_down_all(bus); 857 if (ret < 0) { 858 dev_dbg(sdev->dev, 859 "error %d in %s: failed to power down links", 860 ret, __func__); 861 return ret; 862 } 863 #endif 864 865 /* enable the system waking up via IPC IRQ */ 866 enable_irq_wake(pci->irq); 867 pci_save_state(pci); 868 return 0; 869 } 870 871 /* stop hda controller and power dsp off */ 872 ret = hda_suspend(sdev, false); 873 if (ret < 0) { 874 dev_err(bus->dev, "error: suspending dsp\n"); 875 return ret; 876 } 877 878 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 879 } 880 881 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 882 { 883 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 884 struct hdac_bus *bus = sof_to_bus(sdev); 885 struct snd_soc_pcm_runtime *rtd; 886 struct hdac_ext_stream *stream; 887 struct hdac_ext_link *link; 888 struct hdac_stream *s; 889 const char *name; 890 int stream_tag; 891 892 /* set internal flag for BE */ 893 list_for_each_entry(s, &bus->stream_list, list) { 894 stream = stream_to_hdac_ext_stream(s); 895 896 /* 897 * clear stream. This should already be taken care for running 898 * streams when the SUSPEND trigger is called. But paused 899 * streams do not get suspended, so this needs to be done 900 * explicitly during suspend. 901 */ 902 if (stream->link_substream) { 903 rtd = asoc_substream_to_rtd(stream->link_substream); 904 name = asoc_rtd_to_codec(rtd, 0)->component->name; 905 link = snd_hdac_ext_bus_get_link(bus, name); 906 if (!link) 907 return -EINVAL; 908 909 stream->link_prepared = 0; 910 911 if (hdac_stream(stream)->direction == 912 SNDRV_PCM_STREAM_CAPTURE) 913 continue; 914 915 stream_tag = hdac_stream(stream)->stream_tag; 916 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 917 } 918 } 919 #endif 920 return 0; 921 } 922 923 void hda_dsp_d0i3_work(struct work_struct *work) 924 { 925 struct sof_intel_hda_dev *hdev = container_of(work, 926 struct sof_intel_hda_dev, 927 d0i3_work.work); 928 struct hdac_bus *bus = &hdev->hbus.core; 929 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 930 struct sof_dsp_power_state target_state; 931 int ret; 932 933 target_state.state = SOF_DSP_PM_D0; 934 935 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 936 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 937 target_state.substate = SOF_HDA_DSP_PM_D0I3; 938 else 939 target_state.substate = SOF_HDA_DSP_PM_D0I0; 940 941 /* remain in D0I0 */ 942 if (target_state.substate == SOF_HDA_DSP_PM_D0I0) 943 return; 944 945 /* This can fail but error cannot be propagated */ 946 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 947 if (ret < 0) 948 dev_err_ratelimited(sdev->dev, 949 "error: failed to set DSP state %d substate %d\n", 950 target_state.state, target_state.substate); 951 } 952