1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 #include "../ops.h" 21 #include "hda.h" 22 23 /* 24 * HDA Operations. 25 */ 26 27 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset) 28 { 29 unsigned long timeout; 30 u32 gctl = 0; 31 u32 val; 32 33 /* 0 to enter reset and 1 to exit reset */ 34 val = reset ? 0 : SOF_HDA_GCTL_RESET; 35 36 /* enter/exit HDA controller reset */ 37 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL, 38 SOF_HDA_GCTL_RESET, val); 39 40 /* wait to enter/exit reset */ 41 timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT); 42 while (time_before(jiffies, timeout)) { 43 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); 44 if ((gctl & SOF_HDA_GCTL_RESET) == val) 45 return 0; 46 usleep_range(500, 1000); 47 } 48 49 /* enter/exit reset failed */ 50 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n", 51 reset ? "reset" : "ready", gctl); 52 return -EIO; 53 } 54 55 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev) 56 { 57 struct hdac_bus *bus = sof_to_bus(sdev); 58 u32 cap, offset, feature; 59 int count = 0; 60 61 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH); 62 63 do { 64 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset); 65 66 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n", 67 offset & SOF_HDA_CAP_NEXT_MASK); 68 69 feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF; 70 71 switch (feature) { 72 case SOF_HDA_PP_CAP_ID: 73 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n", 74 offset); 75 bus->ppcap = bus->remap_addr + offset; 76 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap; 77 break; 78 case SOF_HDA_SPIB_CAP_ID: 79 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n", 80 offset); 81 bus->spbcap = bus->remap_addr + offset; 82 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap; 83 break; 84 case SOF_HDA_DRSM_CAP_ID: 85 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n", 86 offset); 87 bus->drsmcap = bus->remap_addr + offset; 88 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap; 89 break; 90 case SOF_HDA_GTS_CAP_ID: 91 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n", 92 offset); 93 bus->gtscap = bus->remap_addr + offset; 94 break; 95 case SOF_HDA_ML_CAP_ID: 96 dev_dbg(sdev->dev, "found ML capability at 0x%x\n", 97 offset); 98 bus->mlcap = bus->remap_addr + offset; 99 break; 100 default: 101 dev_vdbg(sdev->dev, "found capability %d at 0x%x\n", 102 feature, offset); 103 break; 104 } 105 106 offset = cap & SOF_HDA_CAP_NEXT_MASK; 107 } while (count++ <= SOF_HDA_MAX_CAPS && offset); 108 109 return 0; 110 } 111 112 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable) 113 { 114 u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0; 115 116 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 117 SOF_HDA_PPCTL_GPROCEN, val); 118 } 119 120 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable) 121 { 122 u32 val = enable ? SOF_HDA_PPCTL_PIE : 0; 123 124 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 125 SOF_HDA_PPCTL_PIE, val); 126 } 127 128 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable) 129 { 130 u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0; 131 132 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val); 133 } 134 135 /* 136 * enable/disable audio dsp clock gating and power gating bits. 137 * This allows the HW to opportunistically power and clock gate 138 * the audio dsp when it is idle 139 */ 140 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable) 141 { 142 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 143 struct hdac_bus *bus = sof_to_bus(sdev); 144 #endif 145 u32 val; 146 147 /* enable/disable audio dsp clock gating */ 148 val = enable ? PCI_CGCTL_ADSPDCGE : 0; 149 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val); 150 151 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 152 /* enable/disable L1 support */ 153 val = enable ? SOF_HDA_VS_EM2_L1SEN : 0; 154 snd_hdac_chip_updatel(bus, VS_EM2, SOF_HDA_VS_EM2_L1SEN, val); 155 #endif 156 157 /* enable/disable audio dsp power gating */ 158 val = enable ? 0 : PCI_PGCTL_ADSPPGD; 159 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val); 160 161 return 0; 162 } 163 164 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset) 165 { 166 struct hdac_bus *bus = sof_to_bus(sdev); 167 struct hdac_stream *stream; 168 int sd_offset, ret = 0; 169 170 if (bus->chip_init) 171 return 0; 172 173 hda_dsp_ctrl_misc_clock_gating(sdev, false); 174 175 if (full_reset) { 176 /* clear WAKESTS */ 177 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, 178 SOF_HDA_WAKESTS_INT_MASK, 179 SOF_HDA_WAKESTS_INT_MASK); 180 181 /* reset HDA controller */ 182 ret = hda_dsp_ctrl_link_reset(sdev, true); 183 if (ret < 0) { 184 dev_err(sdev->dev, "error: failed to reset HDA controller\n"); 185 return ret; 186 } 187 188 usleep_range(500, 1000); 189 190 /* exit HDA controller reset */ 191 ret = hda_dsp_ctrl_link_reset(sdev, false); 192 if (ret < 0) { 193 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n"); 194 return ret; 195 } 196 197 usleep_range(1000, 1200); 198 } 199 200 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 201 /* check to see if controller is ready */ 202 if (!snd_hdac_chip_readb(bus, GCTL)) { 203 dev_dbg(bus->dev, "controller not ready!\n"); 204 return -EBUSY; 205 } 206 207 /* Accept unsolicited responses */ 208 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); 209 210 /* detect codecs */ 211 if (!bus->codec_mask) { 212 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); 213 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); 214 } 215 #endif 216 217 /* clear stream status */ 218 list_for_each_entry(stream, &bus->stream_list, list) { 219 sd_offset = SOF_STREAM_SD_OFFSET(stream); 220 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 221 sd_offset + 222 SOF_HDA_ADSP_REG_CL_SD_STS, 223 SOF_HDA_CL_DMA_SD_INT_MASK, 224 SOF_HDA_CL_DMA_SD_INT_MASK); 225 } 226 227 /* clear WAKESTS */ 228 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, 229 SOF_HDA_WAKESTS_INT_MASK, 230 SOF_HDA_WAKESTS_INT_MASK); 231 232 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 233 /* clear rirb status */ 234 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 235 #endif 236 237 /* clear interrupt status register */ 238 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, 239 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM); 240 241 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 242 /* initialize the codec command I/O */ 243 snd_hdac_bus_init_cmd_io(bus); 244 #endif 245 246 /* enable CIE and GIE interrupts */ 247 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 248 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 249 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN); 250 251 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 252 /* program the position buffer */ 253 if (bus->use_posbuf && bus->posbuf.addr) { 254 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); 255 snd_hdac_chip_writel(bus, DPUBASE, 256 upper_32_bits(bus->posbuf.addr)); 257 } 258 #endif 259 260 bus->chip_init = true; 261 262 hda_dsp_ctrl_misc_clock_gating(sdev, true); 263 264 return ret; 265 } 266