1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for audio DSP on Cannonlake. 16 */ 17 18 #include <sound/sof/ext_manifest4.h> 19 #include <sound/sof/ipc4/header.h> 20 #include <trace/events/sof_intel.h> 21 #include "../ipc4-priv.h" 22 #include "../ops.h" 23 #include "hda.h" 24 #include "hda-ipc.h" 25 #include "../sof-audio.h" 26 27 static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = { 28 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 31 }; 32 33 static void cnl_ipc_host_done(struct snd_sof_dev *sdev); 34 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev); 35 36 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context) 37 { 38 struct sof_ipc4_msg notification_data = {{ 0 }}; 39 struct snd_sof_dev *sdev = context; 40 bool ipc_irq = false; 41 u32 hipcida, hipctdr; 42 43 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 44 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) { 45 /* DSP received the message */ 46 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 47 CNL_DSP_REG_HIPCCTL, 48 CNL_DSP_REG_HIPCCTL_DONE, 0); 49 cnl_ipc_dsp_done(sdev); 50 51 ipc_irq = true; 52 } 53 54 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 55 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) { 56 /* Message from DSP (reply or notification) */ 57 u32 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 58 CNL_DSP_REG_HIPCTDD); 59 u32 primary = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK; 60 u32 extension = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK; 61 62 if (primary & SOF_IPC4_MSG_DIR_MASK) { 63 /* Reply received */ 64 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 65 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 66 67 data->primary = primary; 68 data->extension = extension; 69 70 spin_lock_irq(&sdev->ipc_lock); 71 72 snd_sof_ipc_get_reply(sdev); 73 snd_sof_ipc_reply(sdev, data->primary); 74 75 spin_unlock_irq(&sdev->ipc_lock); 76 } else { 77 dev_dbg_ratelimited(sdev->dev, 78 "IPC reply before FW_READY: %#x|%#x\n", 79 primary, extension); 80 } 81 } else { 82 /* Notification received */ 83 notification_data.primary = primary; 84 notification_data.extension = extension; 85 86 sdev->ipc->msg.rx_data = ¬ification_data; 87 snd_sof_ipc_msgs_rx(sdev); 88 sdev->ipc->msg.rx_data = NULL; 89 } 90 91 /* Let DSP know that we have finished processing the message */ 92 cnl_ipc_host_done(sdev); 93 94 ipc_irq = true; 95 } 96 97 if (!ipc_irq) 98 /* This interrupt is not shared so no need to return IRQ_NONE. */ 99 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 100 101 return IRQ_HANDLED; 102 } 103 104 irqreturn_t cnl_ipc_irq_thread(int irq, void *context) 105 { 106 struct snd_sof_dev *sdev = context; 107 u32 hipci; 108 u32 hipcida; 109 u32 hipctdr; 110 u32 hipctdd; 111 u32 msg; 112 u32 msg_ext; 113 bool ipc_irq = false; 114 115 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 116 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 117 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD); 118 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR); 119 120 /* reply message from DSP */ 121 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) { 122 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK; 123 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK; 124 125 trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext); 126 127 /* mask Done interrupt */ 128 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 129 CNL_DSP_REG_HIPCCTL, 130 CNL_DSP_REG_HIPCCTL_DONE, 0); 131 132 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 133 spin_lock_irq(&sdev->ipc_lock); 134 135 /* handle immediate reply from DSP core */ 136 hda_dsp_ipc_get_reply(sdev); 137 snd_sof_ipc_reply(sdev, msg); 138 139 cnl_ipc_dsp_done(sdev); 140 141 spin_unlock_irq(&sdev->ipc_lock); 142 } else { 143 dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n", 144 msg); 145 } 146 147 ipc_irq = true; 148 } 149 150 /* new message from DSP */ 151 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) { 152 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK; 153 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK; 154 155 trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext); 156 157 /* handle messages from DSP */ 158 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 159 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 160 bool non_recoverable = true; 161 162 /* 163 * This is a PANIC message! 164 * 165 * If it is arriving during firmware boot and it is not 166 * the last boot attempt then change the non_recoverable 167 * to false as the DSP might be able to boot in the next 168 * iteration(s) 169 */ 170 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS && 171 hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS) 172 non_recoverable = false; 173 174 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext), 175 non_recoverable); 176 } else { 177 snd_sof_ipc_msgs_rx(sdev); 178 } 179 180 cnl_ipc_host_done(sdev); 181 182 ipc_irq = true; 183 } 184 185 if (!ipc_irq) { 186 /* 187 * This interrupt is not shared so no need to return IRQ_NONE. 188 */ 189 dev_dbg_ratelimited(sdev->dev, 190 "nothing to do in IPC IRQ thread\n"); 191 } 192 193 return IRQ_HANDLED; 194 } 195 196 static void cnl_ipc_host_done(struct snd_sof_dev *sdev) 197 { 198 /* 199 * clear busy interrupt to tell dsp controller this 200 * interrupt has been accepted, not trigger it again 201 */ 202 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 203 CNL_DSP_REG_HIPCTDR, 204 CNL_DSP_REG_HIPCTDR_BUSY, 205 CNL_DSP_REG_HIPCTDR_BUSY); 206 /* 207 * set done bit to ack dsp the msg has been 208 * processed and send reply msg to dsp 209 */ 210 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 211 CNL_DSP_REG_HIPCTDA, 212 CNL_DSP_REG_HIPCTDA_DONE, 213 CNL_DSP_REG_HIPCTDA_DONE); 214 } 215 216 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev) 217 { 218 /* 219 * set DONE bit - tell DSP we have received the reply msg 220 * from DSP, and processed it, don't send more reply to host 221 */ 222 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 223 CNL_DSP_REG_HIPCIDA, 224 CNL_DSP_REG_HIPCIDA_DONE, 225 CNL_DSP_REG_HIPCIDA_DONE); 226 227 /* unmask Done interrupt */ 228 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, 229 CNL_DSP_REG_HIPCCTL, 230 CNL_DSP_REG_HIPCCTL_DONE, 231 CNL_DSP_REG_HIPCCTL_DONE); 232 } 233 234 static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg, 235 u32 *dr, u32 *dd) 236 { 237 struct sof_ipc_pm_gate *pm_gate = msg->msg_data; 238 239 if (pm_gate->hdr.cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) { 240 /* send the compact message via the primary register */ 241 *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE; 242 243 /* send payload via the extended data register */ 244 *dd = pm_gate->flags; 245 246 return true; 247 } 248 249 return false; 250 } 251 252 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 253 { 254 struct sof_ipc4_msg *msg_data = msg->msg_data; 255 256 /* send the message via mailbox */ 257 if (msg_data->data_size) 258 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 259 msg_data->data_size); 260 261 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, msg_data->extension); 262 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, 263 msg_data->primary | CNL_DSP_REG_HIPCIDR_BUSY); 264 265 return 0; 266 } 267 268 int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 269 { 270 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 271 struct sof_ipc_cmd_hdr *hdr; 272 u32 dr = 0; 273 u32 dd = 0; 274 275 /* 276 * Currently the only compact IPC supported is the PM_GATE 277 * IPC which is used for transitioning the DSP between the 278 * D0I0 and D0I3 states. And these are sent only during the 279 * set_power_state() op. Therefore, there will never be a case 280 * that a compact IPC results in the DSP exiting D0I3 without 281 * the host and FW being in sync. 282 */ 283 if (cnl_compact_ipc_compress(msg, &dr, &dd)) { 284 /* send the message via IPC registers */ 285 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, 286 dd); 287 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, 288 CNL_DSP_REG_HIPCIDR_BUSY | dr); 289 return 0; 290 } 291 292 /* send the message via mailbox */ 293 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 294 msg->msg_size); 295 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, 296 CNL_DSP_REG_HIPCIDR_BUSY); 297 298 hdr = msg->msg_data; 299 300 /* 301 * Use mod_delayed_work() to schedule the delayed work 302 * to avoid scheduling multiple workqueue items when 303 * IPCs are sent at a high-rate. mod_delayed_work() 304 * modifies the timer if the work is pending. 305 * Also, a new delayed work should not be queued after the 306 * CTX_SAVE IPC, which is sent before the DSP enters D3. 307 */ 308 if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE)) 309 mod_delayed_work(system_wq, &hdev->d0i3_work, 310 msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS)); 311 312 return 0; 313 } 314 315 void cnl_ipc_dump(struct snd_sof_dev *sdev) 316 { 317 u32 hipcctl; 318 u32 hipcida; 319 u32 hipctdr; 320 321 hda_ipc_irq_dump(sdev); 322 323 /* read IPC status */ 324 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 325 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL); 326 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 327 328 /* dump the IPC regs */ 329 /* TODO: parse the raw msg */ 330 dev_err(sdev->dev, 331 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 332 hipcida, hipctdr, hipcctl); 333 } 334 335 void cnl_ipc4_dump(struct snd_sof_dev *sdev) 336 { 337 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl; 338 339 hda_ipc_irq_dump(sdev); 340 341 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR); 342 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD); 343 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); 344 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); 345 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD); 346 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDA); 347 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL); 348 349 /* dump the IPC regs */ 350 /* TODO: parse the raw msg */ 351 dev_err(sdev->dev, 352 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n", 353 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl); 354 } 355 356 /* cannonlake ops */ 357 struct snd_sof_dsp_ops sof_cnl_ops; 358 EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 359 360 int sof_cnl_ops_init(struct snd_sof_dev *sdev) 361 { 362 /* common defaults */ 363 memcpy(&sof_cnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 364 365 /* probe/remove/shutdown */ 366 sof_cnl_ops.shutdown = hda_dsp_shutdown; 367 368 /* ipc */ 369 if (sdev->pdata->ipc_type == SOF_IPC) { 370 /* doorbell */ 371 sof_cnl_ops.irq_thread = cnl_ipc_irq_thread; 372 373 /* ipc */ 374 sof_cnl_ops.send_msg = cnl_ipc_send_msg; 375 376 /* debug */ 377 sof_cnl_ops.ipc_dump = cnl_ipc_dump; 378 } 379 380 if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { 381 struct sof_ipc4_fw_data *ipc4_data; 382 383 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); 384 if (!sdev->private) 385 return -ENOMEM; 386 387 ipc4_data = sdev->private; 388 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 389 390 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_8; 391 392 /* doorbell */ 393 sof_cnl_ops.irq_thread = cnl_ipc4_irq_thread; 394 395 /* ipc */ 396 sof_cnl_ops.send_msg = cnl_ipc4_send_msg; 397 398 /* debug */ 399 sof_cnl_ops.ipc_dump = cnl_ipc4_dump; 400 } 401 402 /* set DAI driver ops */ 403 hda_set_dai_drv_ops(sdev, &sof_cnl_ops); 404 405 /* debug */ 406 sof_cnl_ops.debug_map = cnl_dsp_debugfs; 407 sof_cnl_ops.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs); 408 409 /* pre/post fw run */ 410 sof_cnl_ops.post_fw_run = hda_dsp_post_fw_run; 411 412 /* firmware run */ 413 sof_cnl_ops.run = hda_dsp_cl_boot_firmware; 414 415 /* dsp core get/put */ 416 sof_cnl_ops.core_get = hda_dsp_core_get; 417 418 return 0; 419 }; 420 EXPORT_SYMBOL_NS(sof_cnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 421 422 const struct sof_intel_dsp_desc cnl_chip_info = { 423 /* Cannonlake */ 424 .cores_num = 4, 425 .init_core_mask = 1, 426 .host_managed_cores_mask = GENMASK(3, 0), 427 .ipc_req = CNL_DSP_REG_HIPCIDR, 428 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 429 .ipc_ack = CNL_DSP_REG_HIPCIDA, 430 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 431 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 432 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 433 .rom_init_timeout = 300, 434 .ssp_count = CNL_SSP_COUNT, 435 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 436 .sdw_shim_base = SDW_SHIM_BASE, 437 .sdw_alh_base = SDW_ALH_BASE, 438 .check_sdw_irq = hda_common_check_sdw_irq, 439 .check_ipc_irq = hda_dsp_check_ipc_irq, 440 .cl_init = cl_dsp_init, 441 .power_down_dsp = hda_power_down_dsp, 442 .disable_interrupts = hda_dsp_disable_interrupts, 443 .hw_ip_version = SOF_INTEL_CAVS_1_8, 444 }; 445 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 446 447 /* 448 * JasperLake is technically derived from IceLake, and should be in 449 * described in icl.c. However since JasperLake was designed with 450 * two cores, it cannot support the IceLake-specific power-up sequences 451 * which rely on core3. To simplify, JasperLake uses the CannonLake ops and 452 * is described in cnl.c 453 */ 454 const struct sof_intel_dsp_desc jsl_chip_info = { 455 /* Jasperlake */ 456 .cores_num = 2, 457 .init_core_mask = 1, 458 .host_managed_cores_mask = GENMASK(1, 0), 459 .ipc_req = CNL_DSP_REG_HIPCIDR, 460 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 461 .ipc_ack = CNL_DSP_REG_HIPCIDA, 462 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 463 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 464 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 465 .rom_init_timeout = 300, 466 .ssp_count = ICL_SSP_COUNT, 467 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 468 .sdw_shim_base = SDW_SHIM_BASE, 469 .sdw_alh_base = SDW_ALH_BASE, 470 .check_sdw_irq = hda_common_check_sdw_irq, 471 .check_ipc_irq = hda_dsp_check_ipc_irq, 472 .cl_init = cl_dsp_init, 473 .power_down_dsp = hda_power_down_dsp, 474 .disable_interrupts = hda_dsp_disable_interrupts, 475 .hw_ip_version = SOF_INTEL_CAVS_2_0, 476 }; 477 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 478