1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include "../ops.h" 19 #include "shim.h" 20 #include "../sof-audio.h" 21 #include "../../intel/common/soc-intel-quirks.h" 22 23 /* DSP memories */ 24 #define IRAM_OFFSET 0x0C0000 25 #define IRAM_SIZE (80 * 1024) 26 #define DRAM_OFFSET 0x100000 27 #define DRAM_SIZE (160 * 1024) 28 #define SHIM_OFFSET 0x140000 29 #define SHIM_SIZE_BYT 0x100 30 #define SHIM_SIZE_CHT 0x118 31 #define MBOX_OFFSET 0x144000 32 #define MBOX_SIZE 0x1000 33 #define EXCEPT_OFFSET 0x800 34 #define EXCEPT_MAX_HDR_SIZE 0x400 35 36 /* DSP peripherals */ 37 #define DMAC0_OFFSET 0x098000 38 #define DMAC1_OFFSET 0x09c000 39 #define DMAC2_OFFSET 0x094000 40 #define DMAC_SIZE 0x420 41 #define SSP0_OFFSET 0x0a0000 42 #define SSP1_OFFSET 0x0a1000 43 #define SSP2_OFFSET 0x0a2000 44 #define SSP3_OFFSET 0x0a4000 45 #define SSP4_OFFSET 0x0a5000 46 #define SSP5_OFFSET 0x0a6000 47 #define SSP_SIZE 0x100 48 49 #define BYT_STACK_DUMP_SIZE 32 50 51 #define BYT_PCI_BAR_SIZE 0x200000 52 53 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 54 55 /* 56 * Debug 57 */ 58 59 #define MBOX_DUMP_SIZE 0x30 60 61 /* BARs */ 62 #define BYT_DSP_BAR 0 63 #define BYT_PCI_BAR 1 64 #define BYT_IMR_BAR 2 65 66 static const struct snd_sof_debugfs_map byt_debugfs[] = { 67 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 68 SOF_DEBUGFS_ACCESS_ALWAYS}, 69 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70 SOF_DEBUGFS_ACCESS_ALWAYS}, 71 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 78 SOF_DEBUGFS_ACCESS_D0_ONLY}, 79 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 80 SOF_DEBUGFS_ACCESS_D0_ONLY}, 81 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 82 SOF_DEBUGFS_ACCESS_ALWAYS}, 83 }; 84 85 static void byt_host_done(struct snd_sof_dev *sdev); 86 static void byt_dsp_done(struct snd_sof_dev *sdev); 87 static void byt_get_reply(struct snd_sof_dev *sdev); 88 89 /* 90 * Debug 91 */ 92 93 static void byt_get_registers(struct snd_sof_dev *sdev, 94 struct sof_ipc_dsp_oops_xtensa *xoops, 95 struct sof_ipc_panic_info *panic_info, 96 u32 *stack, size_t stack_words) 97 { 98 u32 offset = sdev->dsp_oops_offset; 99 100 /* first read regsisters */ 101 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 102 103 /* note: variable AR register array is not read */ 104 105 /* then get panic info */ 106 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 107 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 108 xoops->arch_hdr.totalsize); 109 return; 110 } 111 offset += xoops->arch_hdr.totalsize; 112 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 113 114 /* then get the stack */ 115 offset += sizeof(*panic_info); 116 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 117 } 118 119 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 120 { 121 struct sof_ipc_dsp_oops_xtensa xoops; 122 struct sof_ipc_panic_info panic_info; 123 u32 stack[BYT_STACK_DUMP_SIZE]; 124 u64 status, panic, imrd, imrx; 125 126 /* now try generic SOF status messages */ 127 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 128 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 129 byt_get_registers(sdev, &xoops, &panic_info, stack, 130 BYT_STACK_DUMP_SIZE); 131 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 132 BYT_STACK_DUMP_SIZE); 133 134 /* provide some context for firmware debug */ 135 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 136 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 137 dev_err(sdev->dev, 138 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 139 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 140 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 141 dev_err(sdev->dev, 142 "error: mask host: pending %s complete %s raw 0x%llx\n", 143 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 144 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 145 dev_err(sdev->dev, 146 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 147 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 148 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 149 dev_err(sdev->dev, 150 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 151 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 152 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 153 154 } 155 156 /* 157 * IPC Doorbell IRQ handler and thread. 158 */ 159 160 static irqreturn_t byt_irq_handler(int irq, void *context) 161 { 162 struct snd_sof_dev *sdev = context; 163 u64 isr; 164 int ret = IRQ_NONE; 165 166 /* Interrupt arrived, check src */ 167 isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX); 168 if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 169 ret = IRQ_WAKE_THREAD; 170 171 return ret; 172 } 173 174 static irqreturn_t byt_irq_thread(int irq, void *context) 175 { 176 struct snd_sof_dev *sdev = context; 177 u64 ipcx, ipcd; 178 u64 imrx; 179 180 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 181 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 182 183 /* reply message from DSP */ 184 if (ipcx & SHIM_BYT_IPCX_DONE && 185 !(imrx & SHIM_IMRX_DONE)) { 186 /* Mask Done interrupt before first */ 187 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 188 SHIM_IMRX, 189 SHIM_IMRX_DONE, 190 SHIM_IMRX_DONE); 191 192 spin_lock_irq(&sdev->ipc_lock); 193 194 /* 195 * handle immediate reply from DSP core. If the msg is 196 * found, set done bit in cmd_done which is called at the 197 * end of message processing function, else set it here 198 * because the done bit can't be set in cmd_done function 199 * which is triggered by msg 200 */ 201 byt_get_reply(sdev); 202 snd_sof_ipc_reply(sdev, ipcx); 203 204 byt_dsp_done(sdev); 205 206 spin_unlock_irq(&sdev->ipc_lock); 207 } 208 209 /* new message from DSP */ 210 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 211 if (ipcd & SHIM_BYT_IPCD_BUSY && 212 !(imrx & SHIM_IMRX_BUSY)) { 213 /* Mask Busy interrupt before return */ 214 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 215 SHIM_IMRX, 216 SHIM_IMRX_BUSY, 217 SHIM_IMRX_BUSY); 218 219 /* Handle messages from DSP Core */ 220 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 221 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 222 MBOX_OFFSET); 223 } else { 224 snd_sof_ipc_msgs_rx(sdev); 225 } 226 227 byt_host_done(sdev); 228 } 229 230 return IRQ_HANDLED; 231 } 232 233 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 234 { 235 /* send the message */ 236 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 237 msg->msg_size); 238 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 239 240 return 0; 241 } 242 243 static void byt_get_reply(struct snd_sof_dev *sdev) 244 { 245 struct snd_sof_ipc_msg *msg = sdev->msg; 246 struct sof_ipc_reply reply; 247 int ret = 0; 248 249 /* 250 * Sometimes, there is unexpected reply ipc arriving. The reply 251 * ipc belongs to none of the ipcs sent from driver. 252 * In this case, the driver must ignore the ipc. 253 */ 254 if (!msg) { 255 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 256 return; 257 } 258 259 /* get reply */ 260 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 261 262 if (reply.error < 0) { 263 memcpy(msg->reply_data, &reply, sizeof(reply)); 264 ret = reply.error; 265 } else { 266 /* reply correct size ? */ 267 if (reply.hdr.size != msg->reply_size) { 268 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 269 msg->reply_size, reply.hdr.size); 270 ret = -EINVAL; 271 } 272 273 /* read the message */ 274 if (msg->reply_size > 0) 275 sof_mailbox_read(sdev, sdev->host_box.offset, 276 msg->reply_data, msg->reply_size); 277 } 278 279 msg->reply_error = ret; 280 } 281 282 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 283 { 284 return MBOX_OFFSET; 285 } 286 287 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 288 { 289 return MBOX_OFFSET; 290 } 291 292 static void byt_host_done(struct snd_sof_dev *sdev) 293 { 294 /* clear BUSY bit and set DONE bit - accept new messages */ 295 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 296 SHIM_BYT_IPCD_BUSY | 297 SHIM_BYT_IPCD_DONE, 298 SHIM_BYT_IPCD_DONE); 299 300 /* unmask busy interrupt */ 301 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 302 SHIM_IMRX_BUSY, 0); 303 } 304 305 static void byt_dsp_done(struct snd_sof_dev *sdev) 306 { 307 /* clear DONE bit - tell DSP we have completed */ 308 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 309 SHIM_BYT_IPCX_DONE, 0); 310 311 /* unmask Done interrupt */ 312 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 313 SHIM_IMRX_DONE, 0); 314 } 315 316 /* 317 * DSP control. 318 */ 319 320 static int byt_run(struct snd_sof_dev *sdev) 321 { 322 int tries = 10; 323 324 /* release stall and wait to unstall */ 325 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 326 SHIM_BYT_CSR_STALL, 0x0); 327 while (tries--) { 328 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 329 SHIM_BYT_CSR_PWAITMODE)) 330 break; 331 msleep(100); 332 } 333 if (tries < 0) { 334 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 335 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 336 return -ENODEV; 337 } 338 339 /* return init core mask */ 340 return 1; 341 } 342 343 static int byt_reset(struct snd_sof_dev *sdev) 344 { 345 /* put DSP into reset, set reset vector and stall */ 346 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 347 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 348 SHIM_BYT_CSR_STALL, 349 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 350 SHIM_BYT_CSR_STALL); 351 352 usleep_range(10, 15); 353 354 /* take DSP out of reset and keep stalled for FW loading */ 355 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 356 SHIM_BYT_CSR_RST, 0); 357 358 return 0; 359 } 360 361 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 362 const char *sof_tplg_filename, 363 const char *ssp_str) 364 { 365 const char *tplg_filename = NULL; 366 char *filename; 367 char *split_ext; 368 369 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 370 if (!filename) 371 return NULL; 372 373 /* this assumes a .tplg extension */ 374 split_ext = strsep(&filename, "."); 375 if (split_ext) { 376 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 377 "%s-%s.tplg", 378 split_ext, ssp_str); 379 if (!tplg_filename) 380 return NULL; 381 } 382 return tplg_filename; 383 } 384 385 static void byt_machine_select(struct snd_sof_dev *sdev) 386 { 387 struct snd_sof_pdata *sof_pdata = sdev->pdata; 388 const struct sof_dev_desc *desc = sof_pdata->desc; 389 struct snd_soc_acpi_mach *mach; 390 struct platform_device *pdev; 391 const char *tplg_filename; 392 393 mach = snd_soc_acpi_find_machine(desc->machines); 394 if (!mach) { 395 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 396 return; 397 } 398 399 pdev = to_platform_device(sdev->dev); 400 if (soc_intel_is_byt_cr(pdev)) { 401 dev_dbg(sdev->dev, 402 "BYT-CR detected, SSP0 used instead of SSP2\n"); 403 404 tplg_filename = fixup_tplg_name(sdev, 405 mach->sof_tplg_filename, 406 "ssp0"); 407 } else { 408 tplg_filename = mach->sof_tplg_filename; 409 } 410 411 if (!tplg_filename) { 412 dev_dbg(sdev->dev, 413 "error: no topology filename\n"); 414 return; 415 } 416 417 sof_pdata->tplg_filename = tplg_filename; 418 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 419 sof_pdata->machine = mach; 420 } 421 422 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 423 struct device *dev) 424 { 425 struct snd_soc_acpi_mach_params *mach_params; 426 427 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 428 mach_params->platform = dev_name(dev); 429 } 430 431 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 432 { 433 /* Disable Interrupt from both sides */ 434 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 435 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 436 437 /* Put DSP into reset, set reset vector */ 438 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 439 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 440 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 441 } 442 443 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 444 { 445 byt_reset_dsp_disable_int(sdev); 446 447 return 0; 448 } 449 450 static int byt_resume(struct snd_sof_dev *sdev) 451 { 452 /* Enable Interrupt from both sides */ 453 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 454 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 455 456 return 0; 457 } 458 459 /* Baytrail DAIs */ 460 static struct snd_soc_dai_driver byt_dai[] = { 461 { 462 .name = "ssp0-port", 463 .playback = { 464 .channels_min = 1, 465 .channels_max = 8, 466 }, 467 .capture = { 468 .channels_min = 1, 469 .channels_max = 8, 470 }, 471 }, 472 { 473 .name = "ssp1-port", 474 .playback = { 475 .channels_min = 1, 476 .channels_max = 8, 477 }, 478 .capture = { 479 .channels_min = 1, 480 .channels_max = 8, 481 }, 482 }, 483 { 484 .name = "ssp2-port", 485 .playback = { 486 .channels_min = 1, 487 .channels_max = 8, 488 }, 489 .capture = { 490 .channels_min = 1, 491 .channels_max = 8, 492 } 493 }, 494 { 495 .name = "ssp3-port", 496 .playback = { 497 .channels_min = 1, 498 .channels_max = 8, 499 }, 500 .capture = { 501 .channels_min = 1, 502 .channels_max = 8, 503 }, 504 }, 505 { 506 .name = "ssp4-port", 507 .playback = { 508 .channels_min = 1, 509 .channels_max = 8, 510 }, 511 .capture = { 512 .channels_min = 1, 513 .channels_max = 8, 514 }, 515 }, 516 { 517 .name = "ssp5-port", 518 .playback = { 519 .channels_min = 1, 520 .channels_max = 8, 521 }, 522 .capture = { 523 .channels_min = 1, 524 .channels_max = 8, 525 }, 526 }, 527 }; 528 529 /* 530 * Probe and remove. 531 */ 532 533 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 534 535 static int tangier_pci_probe(struct snd_sof_dev *sdev) 536 { 537 struct snd_sof_pdata *pdata = sdev->pdata; 538 const struct sof_dev_desc *desc = pdata->desc; 539 struct pci_dev *pci = to_pci_dev(sdev->dev); 540 u32 base, size; 541 int ret; 542 543 /* DSP DMA can only access low 31 bits of host memory */ 544 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 545 if (ret < 0) { 546 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 547 return ret; 548 } 549 550 /* LPE base */ 551 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 552 size = BYT_PCI_BAR_SIZE; 553 554 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 555 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 556 if (!sdev->bar[BYT_DSP_BAR]) { 557 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 558 base, size); 559 return -ENODEV; 560 } 561 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 562 563 /* IMR base - optional */ 564 if (desc->resindex_imr_base == -1) 565 goto irq; 566 567 base = pci_resource_start(pci, desc->resindex_imr_base); 568 size = pci_resource_len(pci, desc->resindex_imr_base); 569 570 /* some BIOSes don't map IMR */ 571 if (base == 0x55aa55aa || base == 0x0) { 572 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 573 goto irq; 574 } 575 576 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 577 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 578 if (!sdev->bar[BYT_IMR_BAR]) { 579 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 580 base, size); 581 return -ENODEV; 582 } 583 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 584 585 irq: 586 /* register our IRQ */ 587 sdev->ipc_irq = pci->irq; 588 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 589 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 590 byt_irq_handler, byt_irq_thread, 591 0, "AudioDSP", sdev); 592 if (ret < 0) { 593 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 594 sdev->ipc_irq); 595 return ret; 596 } 597 598 /* enable Interrupt from both sides */ 599 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 600 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 601 602 /* set default mailbox offset for FW ready message */ 603 sdev->dsp_box.offset = MBOX_OFFSET; 604 605 return ret; 606 } 607 608 const struct snd_sof_dsp_ops sof_tng_ops = { 609 /* device init */ 610 .probe = tangier_pci_probe, 611 612 /* DSP core boot / reset */ 613 .run = byt_run, 614 .reset = byt_reset, 615 616 /* Register IO */ 617 .write = sof_io_write, 618 .read = sof_io_read, 619 .write64 = sof_io_write64, 620 .read64 = sof_io_read64, 621 622 /* Block IO */ 623 .block_read = sof_block_read, 624 .block_write = sof_block_write, 625 626 /* doorbell */ 627 .irq_handler = byt_irq_handler, 628 .irq_thread = byt_irq_thread, 629 630 /* ipc */ 631 .send_msg = byt_send_msg, 632 .fw_ready = sof_fw_ready, 633 .get_mailbox_offset = byt_get_mailbox_offset, 634 .get_window_offset = byt_get_window_offset, 635 636 .ipc_msg_data = intel_ipc_msg_data, 637 .ipc_pcm_params = intel_ipc_pcm_params, 638 639 /* machine driver */ 640 .machine_select = byt_machine_select, 641 .machine_register = sof_machine_register, 642 .machine_unregister = sof_machine_unregister, 643 .set_mach_params = byt_set_mach_params, 644 645 /* debug */ 646 .debug_map = byt_debugfs, 647 .debug_map_count = ARRAY_SIZE(byt_debugfs), 648 .dbg_dump = byt_dump, 649 650 /* stream callbacks */ 651 .pcm_open = intel_pcm_open, 652 .pcm_close = intel_pcm_close, 653 654 /* module loading */ 655 .load_module = snd_sof_parse_module_memcpy, 656 657 /*Firmware loading */ 658 .load_firmware = snd_sof_load_firmware_memcpy, 659 660 /* DAI drivers */ 661 .drv = byt_dai, 662 .num_drv = 3, /* we have only 3 SSPs on byt*/ 663 664 /* ALSA HW info flags */ 665 .hw_info = SNDRV_PCM_INFO_MMAP | 666 SNDRV_PCM_INFO_MMAP_VALID | 667 SNDRV_PCM_INFO_INTERLEAVED | 668 SNDRV_PCM_INFO_PAUSE | 669 SNDRV_PCM_INFO_BATCH, 670 671 .arch_ops = &sof_xtensa_arch_ops, 672 }; 673 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 674 675 const struct sof_intel_dsp_desc tng_chip_info = { 676 .cores_num = 1, 677 .cores_mask = 1, 678 }; 679 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 680 681 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 682 683 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 684 685 static const struct snd_sof_debugfs_map cht_debugfs[] = { 686 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 687 SOF_DEBUGFS_ACCESS_ALWAYS}, 688 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 689 SOF_DEBUGFS_ACCESS_ALWAYS}, 690 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 691 SOF_DEBUGFS_ACCESS_ALWAYS}, 692 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 693 SOF_DEBUGFS_ACCESS_ALWAYS}, 694 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 695 SOF_DEBUGFS_ACCESS_ALWAYS}, 696 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 697 SOF_DEBUGFS_ACCESS_ALWAYS}, 698 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 699 SOF_DEBUGFS_ACCESS_ALWAYS}, 700 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 701 SOF_DEBUGFS_ACCESS_ALWAYS}, 702 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 703 SOF_DEBUGFS_ACCESS_ALWAYS}, 704 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 705 SOF_DEBUGFS_ACCESS_D0_ONLY}, 706 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 707 SOF_DEBUGFS_ACCESS_D0_ONLY}, 708 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 709 SOF_DEBUGFS_ACCESS_ALWAYS}, 710 }; 711 712 static int byt_acpi_probe(struct snd_sof_dev *sdev) 713 { 714 struct snd_sof_pdata *pdata = sdev->pdata; 715 const struct sof_dev_desc *desc = pdata->desc; 716 struct platform_device *pdev = 717 container_of(sdev->dev, struct platform_device, dev); 718 struct resource *mmio; 719 u32 base, size; 720 int ret; 721 722 /* DSP DMA can only access low 31 bits of host memory */ 723 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 724 if (ret < 0) { 725 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 726 return ret; 727 } 728 729 /* LPE base */ 730 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 731 desc->resindex_lpe_base); 732 if (mmio) { 733 base = mmio->start; 734 size = resource_size(mmio); 735 } else { 736 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 737 desc->resindex_lpe_base); 738 return -EINVAL; 739 } 740 741 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 742 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 743 if (!sdev->bar[BYT_DSP_BAR]) { 744 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 745 base, size); 746 return -ENODEV; 747 } 748 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 749 750 /* TODO: add offsets */ 751 sdev->mmio_bar = BYT_DSP_BAR; 752 sdev->mailbox_bar = BYT_DSP_BAR; 753 754 /* IMR base - optional */ 755 if (desc->resindex_imr_base == -1) 756 goto irq; 757 758 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 759 desc->resindex_imr_base); 760 if (mmio) { 761 base = mmio->start; 762 size = resource_size(mmio); 763 } else { 764 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 765 desc->resindex_imr_base); 766 return -ENODEV; 767 } 768 769 /* some BIOSes don't map IMR */ 770 if (base == 0x55aa55aa || base == 0x0) { 771 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 772 goto irq; 773 } 774 775 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 776 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 777 if (!sdev->bar[BYT_IMR_BAR]) { 778 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 779 base, size); 780 return -ENODEV; 781 } 782 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 783 784 irq: 785 /* register our IRQ */ 786 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 787 if (sdev->ipc_irq < 0) 788 return sdev->ipc_irq; 789 790 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 791 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 792 byt_irq_handler, byt_irq_thread, 793 IRQF_SHARED, "AudioDSP", sdev); 794 if (ret < 0) { 795 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 796 sdev->ipc_irq); 797 return ret; 798 } 799 800 /* enable Interrupt from both sides */ 801 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 802 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 803 804 /* set default mailbox offset for FW ready message */ 805 sdev->dsp_box.offset = MBOX_OFFSET; 806 807 return ret; 808 } 809 810 /* baytrail ops */ 811 const struct snd_sof_dsp_ops sof_byt_ops = { 812 /* device init */ 813 .probe = byt_acpi_probe, 814 815 /* DSP core boot / reset */ 816 .run = byt_run, 817 .reset = byt_reset, 818 819 /* Register IO */ 820 .write = sof_io_write, 821 .read = sof_io_read, 822 .write64 = sof_io_write64, 823 .read64 = sof_io_read64, 824 825 /* Block IO */ 826 .block_read = sof_block_read, 827 .block_write = sof_block_write, 828 829 /* doorbell */ 830 .irq_handler = byt_irq_handler, 831 .irq_thread = byt_irq_thread, 832 833 /* ipc */ 834 .send_msg = byt_send_msg, 835 .fw_ready = sof_fw_ready, 836 .get_mailbox_offset = byt_get_mailbox_offset, 837 .get_window_offset = byt_get_window_offset, 838 839 .ipc_msg_data = intel_ipc_msg_data, 840 .ipc_pcm_params = intel_ipc_pcm_params, 841 842 /* machine driver */ 843 .machine_select = byt_machine_select, 844 .machine_register = sof_machine_register, 845 .machine_unregister = sof_machine_unregister, 846 .set_mach_params = byt_set_mach_params, 847 848 /* debug */ 849 .debug_map = byt_debugfs, 850 .debug_map_count = ARRAY_SIZE(byt_debugfs), 851 .dbg_dump = byt_dump, 852 853 /* stream callbacks */ 854 .pcm_open = intel_pcm_open, 855 .pcm_close = intel_pcm_close, 856 857 /* module loading */ 858 .load_module = snd_sof_parse_module_memcpy, 859 860 /*Firmware loading */ 861 .load_firmware = snd_sof_load_firmware_memcpy, 862 863 /* PM */ 864 .suspend = byt_suspend, 865 .resume = byt_resume, 866 867 /* DAI drivers */ 868 .drv = byt_dai, 869 .num_drv = 3, /* we have only 3 SSPs on byt*/ 870 871 /* ALSA HW info flags */ 872 .hw_info = SNDRV_PCM_INFO_MMAP | 873 SNDRV_PCM_INFO_MMAP_VALID | 874 SNDRV_PCM_INFO_INTERLEAVED | 875 SNDRV_PCM_INFO_PAUSE | 876 SNDRV_PCM_INFO_BATCH, 877 878 .arch_ops = &sof_xtensa_arch_ops, 879 }; 880 EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 881 882 const struct sof_intel_dsp_desc byt_chip_info = { 883 .cores_num = 1, 884 .cores_mask = 1, 885 }; 886 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 887 888 /* cherrytrail and braswell ops */ 889 const struct snd_sof_dsp_ops sof_cht_ops = { 890 /* device init */ 891 .probe = byt_acpi_probe, 892 893 /* DSP core boot / reset */ 894 .run = byt_run, 895 .reset = byt_reset, 896 897 /* Register IO */ 898 .write = sof_io_write, 899 .read = sof_io_read, 900 .write64 = sof_io_write64, 901 .read64 = sof_io_read64, 902 903 /* Block IO */ 904 .block_read = sof_block_read, 905 .block_write = sof_block_write, 906 907 /* doorbell */ 908 .irq_handler = byt_irq_handler, 909 .irq_thread = byt_irq_thread, 910 911 /* ipc */ 912 .send_msg = byt_send_msg, 913 .fw_ready = sof_fw_ready, 914 .get_mailbox_offset = byt_get_mailbox_offset, 915 .get_window_offset = byt_get_window_offset, 916 917 .ipc_msg_data = intel_ipc_msg_data, 918 .ipc_pcm_params = intel_ipc_pcm_params, 919 920 /* machine driver */ 921 .machine_select = byt_machine_select, 922 .machine_register = sof_machine_register, 923 .machine_unregister = sof_machine_unregister, 924 .set_mach_params = byt_set_mach_params, 925 926 /* debug */ 927 .debug_map = cht_debugfs, 928 .debug_map_count = ARRAY_SIZE(cht_debugfs), 929 .dbg_dump = byt_dump, 930 931 /* stream callbacks */ 932 .pcm_open = intel_pcm_open, 933 .pcm_close = intel_pcm_close, 934 935 /* module loading */ 936 .load_module = snd_sof_parse_module_memcpy, 937 938 /*Firmware loading */ 939 .load_firmware = snd_sof_load_firmware_memcpy, 940 941 /* PM */ 942 .suspend = byt_suspend, 943 .resume = byt_resume, 944 945 /* DAI drivers */ 946 .drv = byt_dai, 947 /* all 6 SSPs may be available for cherrytrail */ 948 .num_drv = ARRAY_SIZE(byt_dai), 949 950 /* ALSA HW info flags */ 951 .hw_info = SNDRV_PCM_INFO_MMAP | 952 SNDRV_PCM_INFO_MMAP_VALID | 953 SNDRV_PCM_INFO_INTERLEAVED | 954 SNDRV_PCM_INFO_PAUSE | 955 SNDRV_PCM_INFO_BATCH, 956 957 .arch_ops = &sof_xtensa_arch_ops, 958 }; 959 EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 960 961 const struct sof_intel_dsp_desc cht_chip_info = { 962 .cores_num = 1, 963 .cores_mask = 1, 964 }; 965 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 966 967 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 968 969 MODULE_LICENSE("Dual BSD/GPL"); 970 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 971 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 972