1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include "../ops.h" 19 #include "shim.h" 20 #include "../sof-audio.h" 21 #include "../../intel/common/soc-intel-quirks.h" 22 23 /* DSP memories */ 24 #define IRAM_OFFSET 0x0C0000 25 #define IRAM_SIZE (80 * 1024) 26 #define DRAM_OFFSET 0x100000 27 #define DRAM_SIZE (160 * 1024) 28 #define SHIM_OFFSET 0x140000 29 #define SHIM_SIZE_BYT 0x100 30 #define SHIM_SIZE_CHT 0x118 31 #define MBOX_OFFSET 0x144000 32 #define MBOX_SIZE 0x1000 33 #define EXCEPT_OFFSET 0x800 34 #define EXCEPT_MAX_HDR_SIZE 0x400 35 36 /* DSP peripherals */ 37 #define DMAC0_OFFSET 0x098000 38 #define DMAC1_OFFSET 0x09c000 39 #define DMAC2_OFFSET 0x094000 40 #define DMAC_SIZE 0x420 41 #define SSP0_OFFSET 0x0a0000 42 #define SSP1_OFFSET 0x0a1000 43 #define SSP2_OFFSET 0x0a2000 44 #define SSP3_OFFSET 0x0a4000 45 #define SSP4_OFFSET 0x0a5000 46 #define SSP5_OFFSET 0x0a6000 47 #define SSP_SIZE 0x100 48 49 #define BYT_STACK_DUMP_SIZE 32 50 51 #define BYT_PCI_BAR_SIZE 0x200000 52 53 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 54 55 /* 56 * Debug 57 */ 58 59 #define MBOX_DUMP_SIZE 0x30 60 61 /* BARs */ 62 #define BYT_DSP_BAR 0 63 #define BYT_PCI_BAR 1 64 #define BYT_IMR_BAR 2 65 66 static const struct snd_sof_debugfs_map byt_debugfs[] = { 67 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 68 SOF_DEBUGFS_ACCESS_ALWAYS}, 69 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70 SOF_DEBUGFS_ACCESS_ALWAYS}, 71 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 78 SOF_DEBUGFS_ACCESS_D0_ONLY}, 79 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 80 SOF_DEBUGFS_ACCESS_D0_ONLY}, 81 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 82 SOF_DEBUGFS_ACCESS_ALWAYS}, 83 }; 84 85 static void byt_host_done(struct snd_sof_dev *sdev); 86 static void byt_dsp_done(struct snd_sof_dev *sdev); 87 static void byt_get_reply(struct snd_sof_dev *sdev); 88 89 /* 90 * Debug 91 */ 92 93 static void byt_get_registers(struct snd_sof_dev *sdev, 94 struct sof_ipc_dsp_oops_xtensa *xoops, 95 struct sof_ipc_panic_info *panic_info, 96 u32 *stack, size_t stack_words) 97 { 98 u32 offset = sdev->dsp_oops_offset; 99 100 /* first read regsisters */ 101 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 102 103 /* note: variable AR register array is not read */ 104 105 /* then get panic info */ 106 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 107 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 108 xoops->arch_hdr.totalsize); 109 return; 110 } 111 offset += xoops->arch_hdr.totalsize; 112 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 113 114 /* then get the stack */ 115 offset += sizeof(*panic_info); 116 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 117 } 118 119 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 120 { 121 struct sof_ipc_dsp_oops_xtensa xoops; 122 struct sof_ipc_panic_info panic_info; 123 u32 stack[BYT_STACK_DUMP_SIZE]; 124 u64 status, panic, imrd, imrx; 125 126 /* now try generic SOF status messages */ 127 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 128 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 129 byt_get_registers(sdev, &xoops, &panic_info, stack, 130 BYT_STACK_DUMP_SIZE); 131 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 132 BYT_STACK_DUMP_SIZE); 133 134 /* provide some context for firmware debug */ 135 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 136 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 137 dev_err(sdev->dev, 138 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 139 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 140 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 141 dev_err(sdev->dev, 142 "error: mask host: pending %s complete %s raw 0x%llx\n", 143 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 144 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 145 dev_err(sdev->dev, 146 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 147 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 148 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 149 dev_err(sdev->dev, 150 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 151 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 152 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 153 154 } 155 156 /* 157 * IPC Doorbell IRQ handler and thread. 158 */ 159 160 static irqreturn_t byt_irq_handler(int irq, void *context) 161 { 162 struct snd_sof_dev *sdev = context; 163 u64 isr; 164 int ret = IRQ_NONE; 165 166 /* Interrupt arrived, check src */ 167 isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX); 168 if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 169 ret = IRQ_WAKE_THREAD; 170 171 return ret; 172 } 173 174 static irqreturn_t byt_irq_thread(int irq, void *context) 175 { 176 struct snd_sof_dev *sdev = context; 177 u64 ipcx, ipcd; 178 u64 imrx; 179 180 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 181 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 182 183 /* reply message from DSP */ 184 if (ipcx & SHIM_BYT_IPCX_DONE && 185 !(imrx & SHIM_IMRX_DONE)) { 186 /* Mask Done interrupt before first */ 187 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 188 SHIM_IMRX, 189 SHIM_IMRX_DONE, 190 SHIM_IMRX_DONE); 191 192 spin_lock_irq(&sdev->ipc_lock); 193 194 /* 195 * handle immediate reply from DSP core. If the msg is 196 * found, set done bit in cmd_done which is called at the 197 * end of message processing function, else set it here 198 * because the done bit can't be set in cmd_done function 199 * which is triggered by msg 200 */ 201 byt_get_reply(sdev); 202 snd_sof_ipc_reply(sdev, ipcx); 203 204 byt_dsp_done(sdev); 205 206 spin_unlock_irq(&sdev->ipc_lock); 207 } 208 209 /* new message from DSP */ 210 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 211 if (ipcd & SHIM_BYT_IPCD_BUSY && 212 !(imrx & SHIM_IMRX_BUSY)) { 213 /* Mask Busy interrupt before return */ 214 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 215 SHIM_IMRX, 216 SHIM_IMRX_BUSY, 217 SHIM_IMRX_BUSY); 218 219 /* Handle messages from DSP Core */ 220 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 221 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 222 MBOX_OFFSET); 223 } else { 224 snd_sof_ipc_msgs_rx(sdev); 225 } 226 227 byt_host_done(sdev); 228 } 229 230 return IRQ_HANDLED; 231 } 232 233 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 234 { 235 /* send the message */ 236 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 237 msg->msg_size); 238 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 239 240 return 0; 241 } 242 243 static void byt_get_reply(struct snd_sof_dev *sdev) 244 { 245 struct snd_sof_ipc_msg *msg = sdev->msg; 246 struct sof_ipc_reply reply; 247 int ret = 0; 248 249 /* 250 * Sometimes, there is unexpected reply ipc arriving. The reply 251 * ipc belongs to none of the ipcs sent from driver. 252 * In this case, the driver must ignore the ipc. 253 */ 254 if (!msg) { 255 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 256 return; 257 } 258 259 /* get reply */ 260 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 261 262 if (reply.error < 0) { 263 memcpy(msg->reply_data, &reply, sizeof(reply)); 264 ret = reply.error; 265 } else { 266 /* reply correct size ? */ 267 if (reply.hdr.size != msg->reply_size) { 268 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 269 msg->reply_size, reply.hdr.size); 270 ret = -EINVAL; 271 } 272 273 /* read the message */ 274 if (msg->reply_size > 0) 275 sof_mailbox_read(sdev, sdev->host_box.offset, 276 msg->reply_data, msg->reply_size); 277 } 278 279 msg->reply_error = ret; 280 } 281 282 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 283 { 284 return MBOX_OFFSET; 285 } 286 287 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 288 { 289 return MBOX_OFFSET; 290 } 291 292 static void byt_host_done(struct snd_sof_dev *sdev) 293 { 294 /* clear BUSY bit and set DONE bit - accept new messages */ 295 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 296 SHIM_BYT_IPCD_BUSY | 297 SHIM_BYT_IPCD_DONE, 298 SHIM_BYT_IPCD_DONE); 299 300 /* unmask busy interrupt */ 301 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 302 SHIM_IMRX_BUSY, 0); 303 } 304 305 static void byt_dsp_done(struct snd_sof_dev *sdev) 306 { 307 /* clear DONE bit - tell DSP we have completed */ 308 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 309 SHIM_BYT_IPCX_DONE, 0); 310 311 /* unmask Done interrupt */ 312 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 313 SHIM_IMRX_DONE, 0); 314 } 315 316 /* 317 * DSP control. 318 */ 319 320 static int byt_run(struct snd_sof_dev *sdev) 321 { 322 int tries = 10; 323 324 /* release stall and wait to unstall */ 325 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 326 SHIM_BYT_CSR_STALL, 0x0); 327 while (tries--) { 328 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 329 SHIM_BYT_CSR_PWAITMODE)) 330 break; 331 msleep(100); 332 } 333 if (tries < 0) { 334 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 335 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 336 return -ENODEV; 337 } 338 339 /* return init core mask */ 340 return 1; 341 } 342 343 static int byt_reset(struct snd_sof_dev *sdev) 344 { 345 /* put DSP into reset, set reset vector and stall */ 346 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 347 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 348 SHIM_BYT_CSR_STALL, 349 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 350 SHIM_BYT_CSR_STALL); 351 352 usleep_range(10, 15); 353 354 /* take DSP out of reset and keep stalled for FW loading */ 355 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 356 SHIM_BYT_CSR_RST, 0); 357 358 return 0; 359 } 360 361 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 362 const char *sof_tplg_filename, 363 const char *ssp_str) 364 { 365 const char *tplg_filename = NULL; 366 char *filename; 367 char *split_ext; 368 369 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 370 if (!filename) 371 return NULL; 372 373 /* this assumes a .tplg extension */ 374 split_ext = strsep(&filename, "."); 375 if (split_ext) { 376 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 377 "%s-%s.tplg", 378 split_ext, ssp_str); 379 if (!tplg_filename) 380 return NULL; 381 } 382 return tplg_filename; 383 } 384 385 static void byt_machine_select(struct snd_sof_dev *sdev) 386 { 387 struct snd_sof_pdata *sof_pdata = sdev->pdata; 388 const struct sof_dev_desc *desc = sof_pdata->desc; 389 struct snd_soc_acpi_mach *mach; 390 struct platform_device *pdev; 391 const char *tplg_filename; 392 393 mach = snd_soc_acpi_find_machine(desc->machines); 394 if (!mach) { 395 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 396 return; 397 } 398 399 pdev = to_platform_device(sdev->dev); 400 if (soc_intel_is_byt_cr(pdev)) { 401 dev_dbg(sdev->dev, 402 "BYT-CR detected, SSP0 used instead of SSP2\n"); 403 404 tplg_filename = fixup_tplg_name(sdev, 405 mach->sof_tplg_filename, 406 "ssp0"); 407 } else { 408 tplg_filename = mach->sof_tplg_filename; 409 } 410 411 if (!tplg_filename) { 412 dev_dbg(sdev->dev, 413 "error: no topology filename\n"); 414 return; 415 } 416 417 sof_pdata->tplg_filename = tplg_filename; 418 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 419 sof_pdata->machine = mach; 420 } 421 422 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 423 struct device *dev) 424 { 425 struct snd_soc_acpi_mach_params *mach_params; 426 427 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 428 mach_params->platform = dev_name(dev); 429 } 430 431 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 432 { 433 /* Disable Interrupt from both sides */ 434 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 435 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 436 437 /* Put DSP into reset, set reset vector */ 438 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 439 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 440 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 441 } 442 443 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 444 { 445 byt_reset_dsp_disable_int(sdev); 446 447 return 0; 448 } 449 450 static int byt_resume(struct snd_sof_dev *sdev) 451 { 452 /* Enable Interrupt from both sides */ 453 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 454 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 455 456 return 0; 457 } 458 459 static int byt_remove(struct snd_sof_dev *sdev) 460 { 461 byt_reset_dsp_disable_int(sdev); 462 463 return 0; 464 } 465 466 /* Baytrail DAIs */ 467 static struct snd_soc_dai_driver byt_dai[] = { 468 { 469 .name = "ssp0-port", 470 .playback = { 471 .channels_min = 1, 472 .channels_max = 8, 473 }, 474 .capture = { 475 .channels_min = 1, 476 .channels_max = 8, 477 }, 478 }, 479 { 480 .name = "ssp1-port", 481 .playback = { 482 .channels_min = 1, 483 .channels_max = 8, 484 }, 485 .capture = { 486 .channels_min = 1, 487 .channels_max = 8, 488 }, 489 }, 490 { 491 .name = "ssp2-port", 492 .playback = { 493 .channels_min = 1, 494 .channels_max = 8, 495 }, 496 .capture = { 497 .channels_min = 1, 498 .channels_max = 8, 499 } 500 }, 501 { 502 .name = "ssp3-port", 503 .playback = { 504 .channels_min = 1, 505 .channels_max = 8, 506 }, 507 .capture = { 508 .channels_min = 1, 509 .channels_max = 8, 510 }, 511 }, 512 { 513 .name = "ssp4-port", 514 .playback = { 515 .channels_min = 1, 516 .channels_max = 8, 517 }, 518 .capture = { 519 .channels_min = 1, 520 .channels_max = 8, 521 }, 522 }, 523 { 524 .name = "ssp5-port", 525 .playback = { 526 .channels_min = 1, 527 .channels_max = 8, 528 }, 529 .capture = { 530 .channels_min = 1, 531 .channels_max = 8, 532 }, 533 }, 534 }; 535 536 /* 537 * Probe and remove. 538 */ 539 540 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 541 542 static int tangier_pci_probe(struct snd_sof_dev *sdev) 543 { 544 struct snd_sof_pdata *pdata = sdev->pdata; 545 const struct sof_dev_desc *desc = pdata->desc; 546 struct pci_dev *pci = to_pci_dev(sdev->dev); 547 u32 base, size; 548 int ret; 549 550 /* DSP DMA can only access low 31 bits of host memory */ 551 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 552 if (ret < 0) { 553 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 554 return ret; 555 } 556 557 /* LPE base */ 558 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 559 size = BYT_PCI_BAR_SIZE; 560 561 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 562 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 563 if (!sdev->bar[BYT_DSP_BAR]) { 564 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 565 base, size); 566 return -ENODEV; 567 } 568 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 569 570 /* IMR base - optional */ 571 if (desc->resindex_imr_base == -1) 572 goto irq; 573 574 base = pci_resource_start(pci, desc->resindex_imr_base); 575 size = pci_resource_len(pci, desc->resindex_imr_base); 576 577 /* some BIOSes don't map IMR */ 578 if (base == 0x55aa55aa || base == 0x0) { 579 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 580 goto irq; 581 } 582 583 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 584 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 585 if (!sdev->bar[BYT_IMR_BAR]) { 586 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 587 base, size); 588 return -ENODEV; 589 } 590 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 591 592 irq: 593 /* register our IRQ */ 594 sdev->ipc_irq = pci->irq; 595 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 596 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 597 byt_irq_handler, byt_irq_thread, 598 0, "AudioDSP", sdev); 599 if (ret < 0) { 600 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 601 sdev->ipc_irq); 602 return ret; 603 } 604 605 /* enable Interrupt from both sides */ 606 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 607 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 608 609 /* set default mailbox offset for FW ready message */ 610 sdev->dsp_box.offset = MBOX_OFFSET; 611 612 return ret; 613 } 614 615 const struct snd_sof_dsp_ops sof_tng_ops = { 616 /* device init */ 617 .probe = tangier_pci_probe, 618 619 /* DSP core boot / reset */ 620 .run = byt_run, 621 .reset = byt_reset, 622 623 /* Register IO */ 624 .write = sof_io_write, 625 .read = sof_io_read, 626 .write64 = sof_io_write64, 627 .read64 = sof_io_read64, 628 629 /* Block IO */ 630 .block_read = sof_block_read, 631 .block_write = sof_block_write, 632 633 /* doorbell */ 634 .irq_handler = byt_irq_handler, 635 .irq_thread = byt_irq_thread, 636 637 /* ipc */ 638 .send_msg = byt_send_msg, 639 .fw_ready = sof_fw_ready, 640 .get_mailbox_offset = byt_get_mailbox_offset, 641 .get_window_offset = byt_get_window_offset, 642 643 .ipc_msg_data = intel_ipc_msg_data, 644 .ipc_pcm_params = intel_ipc_pcm_params, 645 646 /* machine driver */ 647 .machine_select = byt_machine_select, 648 .machine_register = sof_machine_register, 649 .machine_unregister = sof_machine_unregister, 650 .set_mach_params = byt_set_mach_params, 651 652 /* debug */ 653 .debug_map = byt_debugfs, 654 .debug_map_count = ARRAY_SIZE(byt_debugfs), 655 .dbg_dump = byt_dump, 656 657 /* stream callbacks */ 658 .pcm_open = intel_pcm_open, 659 .pcm_close = intel_pcm_close, 660 661 /* module loading */ 662 .load_module = snd_sof_parse_module_memcpy, 663 664 /*Firmware loading */ 665 .load_firmware = snd_sof_load_firmware_memcpy, 666 667 /* DAI drivers */ 668 .drv = byt_dai, 669 .num_drv = 3, /* we have only 3 SSPs on byt*/ 670 671 /* ALSA HW info flags */ 672 .hw_info = SNDRV_PCM_INFO_MMAP | 673 SNDRV_PCM_INFO_MMAP_VALID | 674 SNDRV_PCM_INFO_INTERLEAVED | 675 SNDRV_PCM_INFO_PAUSE | 676 SNDRV_PCM_INFO_BATCH, 677 678 .arch_ops = &sof_xtensa_arch_ops, 679 }; 680 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 681 682 const struct sof_intel_dsp_desc tng_chip_info = { 683 .cores_num = 1, 684 .cores_mask = 1, 685 }; 686 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 687 688 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 689 690 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 691 692 static const struct snd_sof_debugfs_map cht_debugfs[] = { 693 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 694 SOF_DEBUGFS_ACCESS_ALWAYS}, 695 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 696 SOF_DEBUGFS_ACCESS_ALWAYS}, 697 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 698 SOF_DEBUGFS_ACCESS_ALWAYS}, 699 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 700 SOF_DEBUGFS_ACCESS_ALWAYS}, 701 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 702 SOF_DEBUGFS_ACCESS_ALWAYS}, 703 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 704 SOF_DEBUGFS_ACCESS_ALWAYS}, 705 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 706 SOF_DEBUGFS_ACCESS_ALWAYS}, 707 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 708 SOF_DEBUGFS_ACCESS_ALWAYS}, 709 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 710 SOF_DEBUGFS_ACCESS_ALWAYS}, 711 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 712 SOF_DEBUGFS_ACCESS_D0_ONLY}, 713 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 714 SOF_DEBUGFS_ACCESS_D0_ONLY}, 715 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 716 SOF_DEBUGFS_ACCESS_ALWAYS}, 717 }; 718 719 static int byt_acpi_probe(struct snd_sof_dev *sdev) 720 { 721 struct snd_sof_pdata *pdata = sdev->pdata; 722 const struct sof_dev_desc *desc = pdata->desc; 723 struct platform_device *pdev = 724 container_of(sdev->dev, struct platform_device, dev); 725 struct resource *mmio; 726 u32 base, size; 727 int ret; 728 729 /* DSP DMA can only access low 31 bits of host memory */ 730 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 731 if (ret < 0) { 732 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 733 return ret; 734 } 735 736 /* LPE base */ 737 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 738 desc->resindex_lpe_base); 739 if (mmio) { 740 base = mmio->start; 741 size = resource_size(mmio); 742 } else { 743 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 744 desc->resindex_lpe_base); 745 return -EINVAL; 746 } 747 748 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 749 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 750 if (!sdev->bar[BYT_DSP_BAR]) { 751 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 752 base, size); 753 return -ENODEV; 754 } 755 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 756 757 /* TODO: add offsets */ 758 sdev->mmio_bar = BYT_DSP_BAR; 759 sdev->mailbox_bar = BYT_DSP_BAR; 760 761 /* IMR base - optional */ 762 if (desc->resindex_imr_base == -1) 763 goto irq; 764 765 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 766 desc->resindex_imr_base); 767 if (mmio) { 768 base = mmio->start; 769 size = resource_size(mmio); 770 } else { 771 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 772 desc->resindex_imr_base); 773 return -ENODEV; 774 } 775 776 /* some BIOSes don't map IMR */ 777 if (base == 0x55aa55aa || base == 0x0) { 778 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 779 goto irq; 780 } 781 782 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 783 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 784 if (!sdev->bar[BYT_IMR_BAR]) { 785 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 786 base, size); 787 return -ENODEV; 788 } 789 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 790 791 irq: 792 /* register our IRQ */ 793 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 794 if (sdev->ipc_irq < 0) 795 return sdev->ipc_irq; 796 797 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 798 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 799 byt_irq_handler, byt_irq_thread, 800 IRQF_SHARED, "AudioDSP", sdev); 801 if (ret < 0) { 802 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 803 sdev->ipc_irq); 804 return ret; 805 } 806 807 /* enable Interrupt from both sides */ 808 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 809 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 810 811 /* set default mailbox offset for FW ready message */ 812 sdev->dsp_box.offset = MBOX_OFFSET; 813 814 return ret; 815 } 816 817 /* baytrail ops */ 818 const struct snd_sof_dsp_ops sof_byt_ops = { 819 /* device init */ 820 .probe = byt_acpi_probe, 821 .remove = byt_remove, 822 823 /* DSP core boot / reset */ 824 .run = byt_run, 825 .reset = byt_reset, 826 827 /* Register IO */ 828 .write = sof_io_write, 829 .read = sof_io_read, 830 .write64 = sof_io_write64, 831 .read64 = sof_io_read64, 832 833 /* Block IO */ 834 .block_read = sof_block_read, 835 .block_write = sof_block_write, 836 837 /* doorbell */ 838 .irq_handler = byt_irq_handler, 839 .irq_thread = byt_irq_thread, 840 841 /* ipc */ 842 .send_msg = byt_send_msg, 843 .fw_ready = sof_fw_ready, 844 .get_mailbox_offset = byt_get_mailbox_offset, 845 .get_window_offset = byt_get_window_offset, 846 847 .ipc_msg_data = intel_ipc_msg_data, 848 .ipc_pcm_params = intel_ipc_pcm_params, 849 850 /* machine driver */ 851 .machine_select = byt_machine_select, 852 .machine_register = sof_machine_register, 853 .machine_unregister = sof_machine_unregister, 854 .set_mach_params = byt_set_mach_params, 855 856 /* debug */ 857 .debug_map = byt_debugfs, 858 .debug_map_count = ARRAY_SIZE(byt_debugfs), 859 .dbg_dump = byt_dump, 860 861 /* stream callbacks */ 862 .pcm_open = intel_pcm_open, 863 .pcm_close = intel_pcm_close, 864 865 /* module loading */ 866 .load_module = snd_sof_parse_module_memcpy, 867 868 /*Firmware loading */ 869 .load_firmware = snd_sof_load_firmware_memcpy, 870 871 /* PM */ 872 .suspend = byt_suspend, 873 .resume = byt_resume, 874 875 /* DAI drivers */ 876 .drv = byt_dai, 877 .num_drv = 3, /* we have only 3 SSPs on byt*/ 878 879 /* ALSA HW info flags */ 880 .hw_info = SNDRV_PCM_INFO_MMAP | 881 SNDRV_PCM_INFO_MMAP_VALID | 882 SNDRV_PCM_INFO_INTERLEAVED | 883 SNDRV_PCM_INFO_PAUSE | 884 SNDRV_PCM_INFO_BATCH, 885 886 .arch_ops = &sof_xtensa_arch_ops, 887 }; 888 EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 889 890 const struct sof_intel_dsp_desc byt_chip_info = { 891 .cores_num = 1, 892 .cores_mask = 1, 893 }; 894 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 895 896 /* cherrytrail and braswell ops */ 897 const struct snd_sof_dsp_ops sof_cht_ops = { 898 /* device init */ 899 .probe = byt_acpi_probe, 900 .remove = byt_remove, 901 902 /* DSP core boot / reset */ 903 .run = byt_run, 904 .reset = byt_reset, 905 906 /* Register IO */ 907 .write = sof_io_write, 908 .read = sof_io_read, 909 .write64 = sof_io_write64, 910 .read64 = sof_io_read64, 911 912 /* Block IO */ 913 .block_read = sof_block_read, 914 .block_write = sof_block_write, 915 916 /* doorbell */ 917 .irq_handler = byt_irq_handler, 918 .irq_thread = byt_irq_thread, 919 920 /* ipc */ 921 .send_msg = byt_send_msg, 922 .fw_ready = sof_fw_ready, 923 .get_mailbox_offset = byt_get_mailbox_offset, 924 .get_window_offset = byt_get_window_offset, 925 926 .ipc_msg_data = intel_ipc_msg_data, 927 .ipc_pcm_params = intel_ipc_pcm_params, 928 929 /* machine driver */ 930 .machine_select = byt_machine_select, 931 .machine_register = sof_machine_register, 932 .machine_unregister = sof_machine_unregister, 933 .set_mach_params = byt_set_mach_params, 934 935 /* debug */ 936 .debug_map = cht_debugfs, 937 .debug_map_count = ARRAY_SIZE(cht_debugfs), 938 .dbg_dump = byt_dump, 939 940 /* stream callbacks */ 941 .pcm_open = intel_pcm_open, 942 .pcm_close = intel_pcm_close, 943 944 /* module loading */ 945 .load_module = snd_sof_parse_module_memcpy, 946 947 /*Firmware loading */ 948 .load_firmware = snd_sof_load_firmware_memcpy, 949 950 /* PM */ 951 .suspend = byt_suspend, 952 .resume = byt_resume, 953 954 /* DAI drivers */ 955 .drv = byt_dai, 956 /* all 6 SSPs may be available for cherrytrail */ 957 .num_drv = ARRAY_SIZE(byt_dai), 958 959 /* ALSA HW info flags */ 960 .hw_info = SNDRV_PCM_INFO_MMAP | 961 SNDRV_PCM_INFO_MMAP_VALID | 962 SNDRV_PCM_INFO_INTERLEAVED | 963 SNDRV_PCM_INFO_PAUSE | 964 SNDRV_PCM_INFO_BATCH, 965 966 .arch_ops = &sof_xtensa_arch_ops, 967 }; 968 EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 969 970 const struct sof_intel_dsp_desc cht_chip_info = { 971 .cores_num = 1, 972 .cores_mask = 1, 973 }; 974 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 975 976 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 977 978 MODULE_LICENSE("Dual BSD/GPL"); 979 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 980 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 981