1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include <sound/soc-acpi.h> 19 #include <sound/soc-acpi-intel-match.h> 20 #include <sound/intel-dsp-config.h> 21 #include "../ops.h" 22 #include "atom.h" 23 #include "shim.h" 24 #include "../sof-acpi-dev.h" 25 #include "../sof-audio.h" 26 #include "../../intel/common/soc-intel-quirks.h" 27 28 static const struct snd_sof_debugfs_map byt_debugfs[] = { 29 {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 30 SOF_DEBUGFS_ACCESS_ALWAYS}, 31 {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 32 SOF_DEBUGFS_ACCESS_ALWAYS}, 33 {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE, 34 SOF_DEBUGFS_ACCESS_ALWAYS}, 35 {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE, 36 SOF_DEBUGFS_ACCESS_ALWAYS}, 37 {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE, 38 SOF_DEBUGFS_ACCESS_ALWAYS}, 39 {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 40 SOF_DEBUGFS_ACCESS_D0_ONLY}, 41 {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 42 SOF_DEBUGFS_ACCESS_D0_ONLY}, 43 {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 44 SOF_DEBUGFS_ACCESS_ALWAYS}, 45 }; 46 47 static const struct snd_sof_debugfs_map cht_debugfs[] = { 48 {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 49 SOF_DEBUGFS_ACCESS_ALWAYS}, 50 {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 51 SOF_DEBUGFS_ACCESS_ALWAYS}, 52 {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 53 SOF_DEBUGFS_ACCESS_ALWAYS}, 54 {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE, 55 SOF_DEBUGFS_ACCESS_ALWAYS}, 56 {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE, 57 SOF_DEBUGFS_ACCESS_ALWAYS}, 58 {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE, 59 SOF_DEBUGFS_ACCESS_ALWAYS}, 60 {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE, 61 SOF_DEBUGFS_ACCESS_ALWAYS}, 62 {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE, 63 SOF_DEBUGFS_ACCESS_ALWAYS}, 64 {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE, 65 SOF_DEBUGFS_ACCESS_ALWAYS}, 66 {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 67 SOF_DEBUGFS_ACCESS_D0_ONLY}, 68 {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 69 SOF_DEBUGFS_ACCESS_D0_ONLY}, 70 {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 71 SOF_DEBUGFS_ACCESS_ALWAYS}, 72 }; 73 74 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 75 { 76 /* Disable Interrupt from both sides */ 77 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3); 78 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3); 79 80 /* Put DSP into reset, set reset vector */ 81 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR, 82 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 83 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 84 } 85 86 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 87 { 88 byt_reset_dsp_disable_int(sdev); 89 90 return 0; 91 } 92 93 static int byt_resume(struct snd_sof_dev *sdev) 94 { 95 /* enable BUSY and disable DONE Interrupt by default */ 96 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 97 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 98 SHIM_IMRX_DONE); 99 100 return 0; 101 } 102 103 static int byt_remove(struct snd_sof_dev *sdev) 104 { 105 byt_reset_dsp_disable_int(sdev); 106 107 return 0; 108 } 109 110 static int byt_acpi_probe(struct snd_sof_dev *sdev) 111 { 112 struct snd_sof_pdata *pdata = sdev->pdata; 113 const struct sof_dev_desc *desc = pdata->desc; 114 struct platform_device *pdev = 115 container_of(sdev->dev, struct platform_device, dev); 116 const struct sof_intel_dsp_desc *chip; 117 struct resource *mmio; 118 u32 base, size; 119 int ret; 120 121 chip = get_chip_info(sdev->pdata); 122 if (!chip) { 123 dev_err(sdev->dev, "error: no such device supported\n"); 124 return -EIO; 125 } 126 127 sdev->num_cores = chip->cores_num; 128 129 /* DSP DMA can only access low 31 bits of host memory */ 130 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 131 if (ret < 0) { 132 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 133 return ret; 134 } 135 136 /* LPE base */ 137 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 138 desc->resindex_lpe_base); 139 if (mmio) { 140 base = mmio->start; 141 size = resource_size(mmio); 142 } else { 143 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 144 desc->resindex_lpe_base); 145 return -EINVAL; 146 } 147 148 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 149 sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size); 150 if (!sdev->bar[DSP_BAR]) { 151 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 152 base, size); 153 return -ENODEV; 154 } 155 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]); 156 157 /* TODO: add offsets */ 158 sdev->mmio_bar = DSP_BAR; 159 sdev->mailbox_bar = DSP_BAR; 160 161 /* IMR base - optional */ 162 if (desc->resindex_imr_base == -1) 163 goto irq; 164 165 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 166 desc->resindex_imr_base); 167 if (mmio) { 168 base = mmio->start; 169 size = resource_size(mmio); 170 } else { 171 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 172 desc->resindex_imr_base); 173 return -ENODEV; 174 } 175 176 /* some BIOSes don't map IMR */ 177 if (base == 0x55aa55aa || base == 0x0) { 178 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 179 goto irq; 180 } 181 182 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 183 sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size); 184 if (!sdev->bar[IMR_BAR]) { 185 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 186 base, size); 187 return -ENODEV; 188 } 189 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]); 190 191 irq: 192 /* register our IRQ */ 193 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 194 if (sdev->ipc_irq < 0) 195 return sdev->ipc_irq; 196 197 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 198 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 199 atom_irq_handler, atom_irq_thread, 200 IRQF_SHARED, "AudioDSP", sdev); 201 if (ret < 0) { 202 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 203 sdev->ipc_irq); 204 return ret; 205 } 206 207 /* enable BUSY and disable DONE Interrupt by default */ 208 snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 209 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 210 SHIM_IMRX_DONE); 211 212 /* set default mailbox offset for FW ready message */ 213 sdev->dsp_box.offset = MBOX_OFFSET; 214 215 return ret; 216 } 217 218 /* baytrail ops */ 219 static const struct snd_sof_dsp_ops sof_byt_ops = { 220 /* device init */ 221 .probe = byt_acpi_probe, 222 .remove = byt_remove, 223 224 /* DSP core boot / reset */ 225 .run = atom_run, 226 .reset = atom_reset, 227 228 /* Register IO */ 229 .write = sof_io_write, 230 .read = sof_io_read, 231 .write64 = sof_io_write64, 232 .read64 = sof_io_read64, 233 234 /* Block IO */ 235 .block_read = sof_block_read, 236 .block_write = sof_block_write, 237 238 /* Mailbox IO */ 239 .mailbox_read = sof_mailbox_read, 240 .mailbox_write = sof_mailbox_write, 241 242 /* doorbell */ 243 .irq_handler = atom_irq_handler, 244 .irq_thread = atom_irq_thread, 245 246 /* ipc */ 247 .send_msg = atom_send_msg, 248 .fw_ready = sof_fw_ready, 249 .get_mailbox_offset = atom_get_mailbox_offset, 250 .get_window_offset = atom_get_window_offset, 251 252 .ipc_msg_data = sof_ipc_msg_data, 253 .set_stream_data_offset = sof_set_stream_data_offset, 254 255 /* machine driver */ 256 .machine_select = atom_machine_select, 257 .machine_register = sof_machine_register, 258 .machine_unregister = sof_machine_unregister, 259 .set_mach_params = atom_set_mach_params, 260 261 /* debug */ 262 .debug_map = byt_debugfs, 263 .debug_map_count = ARRAY_SIZE(byt_debugfs), 264 .dbg_dump = atom_dump, 265 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 266 267 /* stream callbacks */ 268 .pcm_open = sof_stream_pcm_open, 269 .pcm_close = sof_stream_pcm_close, 270 271 /* module loading */ 272 .load_module = snd_sof_parse_module_memcpy, 273 274 /*Firmware loading */ 275 .load_firmware = snd_sof_load_firmware_memcpy, 276 277 /* PM */ 278 .suspend = byt_suspend, 279 .resume = byt_resume, 280 281 /* DAI drivers */ 282 .drv = atom_dai, 283 .num_drv = 3, /* we have only 3 SSPs on byt*/ 284 285 /* ALSA HW info flags */ 286 .hw_info = SNDRV_PCM_INFO_MMAP | 287 SNDRV_PCM_INFO_MMAP_VALID | 288 SNDRV_PCM_INFO_INTERLEAVED | 289 SNDRV_PCM_INFO_PAUSE | 290 SNDRV_PCM_INFO_BATCH, 291 292 .dsp_arch_ops = &sof_xtensa_arch_ops, 293 }; 294 295 static const struct sof_intel_dsp_desc byt_chip_info = { 296 .cores_num = 1, 297 .host_managed_cores_mask = 1, 298 }; 299 300 /* cherrytrail and braswell ops */ 301 static const struct snd_sof_dsp_ops sof_cht_ops = { 302 /* device init */ 303 .probe = byt_acpi_probe, 304 .remove = byt_remove, 305 306 /* DSP core boot / reset */ 307 .run = atom_run, 308 .reset = atom_reset, 309 310 /* Register IO */ 311 .write = sof_io_write, 312 .read = sof_io_read, 313 .write64 = sof_io_write64, 314 .read64 = sof_io_read64, 315 316 /* Block IO */ 317 .block_read = sof_block_read, 318 .block_write = sof_block_write, 319 320 /* Mailbox IO */ 321 .mailbox_read = sof_mailbox_read, 322 .mailbox_write = sof_mailbox_write, 323 324 /* doorbell */ 325 .irq_handler = atom_irq_handler, 326 .irq_thread = atom_irq_thread, 327 328 /* ipc */ 329 .send_msg = atom_send_msg, 330 .fw_ready = sof_fw_ready, 331 .get_mailbox_offset = atom_get_mailbox_offset, 332 .get_window_offset = atom_get_window_offset, 333 334 .ipc_msg_data = sof_ipc_msg_data, 335 .set_stream_data_offset = sof_set_stream_data_offset, 336 337 /* machine driver */ 338 .machine_select = atom_machine_select, 339 .machine_register = sof_machine_register, 340 .machine_unregister = sof_machine_unregister, 341 .set_mach_params = atom_set_mach_params, 342 343 /* debug */ 344 .debug_map = cht_debugfs, 345 .debug_map_count = ARRAY_SIZE(cht_debugfs), 346 .dbg_dump = atom_dump, 347 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 348 349 /* stream callbacks */ 350 .pcm_open = sof_stream_pcm_open, 351 .pcm_close = sof_stream_pcm_close, 352 353 /* module loading */ 354 .load_module = snd_sof_parse_module_memcpy, 355 356 /*Firmware loading */ 357 .load_firmware = snd_sof_load_firmware_memcpy, 358 359 /* PM */ 360 .suspend = byt_suspend, 361 .resume = byt_resume, 362 363 /* DAI drivers */ 364 .drv = atom_dai, 365 /* all 6 SSPs may be available for cherrytrail */ 366 .num_drv = 6, 367 368 /* ALSA HW info flags */ 369 .hw_info = SNDRV_PCM_INFO_MMAP | 370 SNDRV_PCM_INFO_MMAP_VALID | 371 SNDRV_PCM_INFO_INTERLEAVED | 372 SNDRV_PCM_INFO_PAUSE | 373 SNDRV_PCM_INFO_BATCH, 374 375 .dsp_arch_ops = &sof_xtensa_arch_ops, 376 }; 377 378 static const struct sof_intel_dsp_desc cht_chip_info = { 379 .cores_num = 1, 380 .host_managed_cores_mask = 1, 381 }; 382 383 /* BYTCR uses different IRQ index */ 384 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { 385 .machines = snd_soc_acpi_intel_baytrail_machines, 386 .resindex_lpe_base = 0, 387 .resindex_pcicfg_base = 1, 388 .resindex_imr_base = 2, 389 .irqindex_host_ipc = 0, 390 .chip_info = &byt_chip_info, 391 .default_fw_path = { 392 [SOF_IPC] = "intel/sof", 393 }, 394 .default_tplg_path = { 395 [SOF_IPC] = "intel/sof-tplg", 396 }, 397 .default_fw_filename = "sof-byt.ri", 398 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 399 .ops = &sof_byt_ops, 400 }; 401 402 static const struct sof_dev_desc sof_acpi_baytrail_desc = { 403 .machines = snd_soc_acpi_intel_baytrail_machines, 404 .resindex_lpe_base = 0, 405 .resindex_pcicfg_base = 1, 406 .resindex_imr_base = 2, 407 .irqindex_host_ipc = 5, 408 .chip_info = &byt_chip_info, 409 .default_fw_path = { 410 [SOF_IPC] = "intel/sof", 411 }, 412 .default_tplg_path = { 413 [SOF_IPC] = "intel/sof-tplg", 414 }, 415 .default_fw_filename = "sof-byt.ri", 416 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 417 .ops = &sof_byt_ops, 418 }; 419 420 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { 421 .machines = snd_soc_acpi_intel_cherrytrail_machines, 422 .resindex_lpe_base = 0, 423 .resindex_pcicfg_base = 1, 424 .resindex_imr_base = 2, 425 .irqindex_host_ipc = 5, 426 .chip_info = &cht_chip_info, 427 .default_fw_path = { 428 [SOF_IPC] = "intel/sof", 429 }, 430 .default_tplg_path = { 431 [SOF_IPC] = "intel/sof-tplg", 432 }, 433 .default_fw_filename = "sof-cht.ri", 434 .nocodec_tplg_filename = "sof-cht-nocodec.tplg", 435 .ops = &sof_cht_ops, 436 }; 437 438 static const struct acpi_device_id sof_baytrail_match[] = { 439 { "80860F28", (unsigned long)&sof_acpi_baytrail_desc }, 440 { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc }, 441 { } 442 }; 443 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match); 444 445 static int sof_baytrail_probe(struct platform_device *pdev) 446 { 447 struct device *dev = &pdev->dev; 448 const struct sof_dev_desc *desc; 449 const struct acpi_device_id *id; 450 int ret; 451 452 id = acpi_match_device(dev->driver->acpi_match_table, dev); 453 if (!id) 454 return -ENODEV; 455 456 ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 457 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 458 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 459 return -ENODEV; 460 } 461 462 desc = device_get_match_data(&pdev->dev); 463 if (!desc) 464 return -ENODEV; 465 466 if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) 467 desc = &sof_acpi_baytrailcr_desc; 468 469 return sof_acpi_probe(pdev, desc); 470 } 471 472 /* acpi_driver definition */ 473 static struct platform_driver snd_sof_acpi_intel_byt_driver = { 474 .probe = sof_baytrail_probe, 475 .remove = sof_acpi_remove, 476 .driver = { 477 .name = "sof-audio-acpi-intel-byt", 478 .pm = &sof_acpi_pm, 479 .acpi_match_table = sof_baytrail_match, 480 }, 481 }; 482 module_platform_driver(snd_sof_acpi_intel_byt_driver); 483 484 MODULE_LICENSE("Dual BSD/GPL"); 485 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 486 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 487 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 488 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP); 489