1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include "../ops.h" 19 #include "shim.h" 20 #include "../sof-audio.h" 21 #include "../../intel/common/soc-intel-quirks.h" 22 23 /* DSP memories */ 24 #define IRAM_OFFSET 0x0C0000 25 #define IRAM_SIZE (80 * 1024) 26 #define DRAM_OFFSET 0x100000 27 #define DRAM_SIZE (160 * 1024) 28 #define SHIM_OFFSET 0x140000 29 #define SHIM_SIZE_BYT 0x100 30 #define SHIM_SIZE_CHT 0x118 31 #define MBOX_OFFSET 0x144000 32 #define MBOX_SIZE 0x1000 33 #define EXCEPT_OFFSET 0x800 34 #define EXCEPT_MAX_HDR_SIZE 0x400 35 36 /* DSP peripherals */ 37 #define DMAC0_OFFSET 0x098000 38 #define DMAC1_OFFSET 0x09c000 39 #define DMAC2_OFFSET 0x094000 40 #define DMAC_SIZE 0x420 41 #define SSP0_OFFSET 0x0a0000 42 #define SSP1_OFFSET 0x0a1000 43 #define SSP2_OFFSET 0x0a2000 44 #define SSP3_OFFSET 0x0a4000 45 #define SSP4_OFFSET 0x0a5000 46 #define SSP5_OFFSET 0x0a6000 47 #define SSP_SIZE 0x100 48 49 #define BYT_STACK_DUMP_SIZE 32 50 51 #define BYT_PCI_BAR_SIZE 0x200000 52 53 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 54 55 /* 56 * Debug 57 */ 58 59 #define MBOX_DUMP_SIZE 0x30 60 61 /* BARs */ 62 #define BYT_DSP_BAR 0 63 #define BYT_PCI_BAR 1 64 #define BYT_IMR_BAR 2 65 66 static const struct snd_sof_debugfs_map byt_debugfs[] = { 67 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 68 SOF_DEBUGFS_ACCESS_ALWAYS}, 69 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70 SOF_DEBUGFS_ACCESS_ALWAYS}, 71 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 78 SOF_DEBUGFS_ACCESS_D0_ONLY}, 79 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 80 SOF_DEBUGFS_ACCESS_D0_ONLY}, 81 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 82 SOF_DEBUGFS_ACCESS_ALWAYS}, 83 }; 84 85 static void byt_host_done(struct snd_sof_dev *sdev); 86 static void byt_dsp_done(struct snd_sof_dev *sdev); 87 static void byt_get_reply(struct snd_sof_dev *sdev); 88 89 /* 90 * Debug 91 */ 92 93 static void byt_get_registers(struct snd_sof_dev *sdev, 94 struct sof_ipc_dsp_oops_xtensa *xoops, 95 struct sof_ipc_panic_info *panic_info, 96 u32 *stack, size_t stack_words) 97 { 98 u32 offset = sdev->dsp_oops_offset; 99 100 /* first read regsisters */ 101 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 102 103 /* note: variable AR register array is not read */ 104 105 /* then get panic info */ 106 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 107 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 108 xoops->arch_hdr.totalsize); 109 return; 110 } 111 offset += xoops->arch_hdr.totalsize; 112 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 113 114 /* then get the stack */ 115 offset += sizeof(*panic_info); 116 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 117 } 118 119 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 120 { 121 struct sof_ipc_dsp_oops_xtensa xoops; 122 struct sof_ipc_panic_info panic_info; 123 u32 stack[BYT_STACK_DUMP_SIZE]; 124 u64 status, panic, imrd, imrx; 125 126 /* now try generic SOF status messages */ 127 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 128 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 129 byt_get_registers(sdev, &xoops, &panic_info, stack, 130 BYT_STACK_DUMP_SIZE); 131 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 132 BYT_STACK_DUMP_SIZE); 133 134 /* provide some context for firmware debug */ 135 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 136 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 137 dev_err(sdev->dev, 138 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 139 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 140 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 141 dev_err(sdev->dev, 142 "error: mask host: pending %s complete %s raw 0x%llx\n", 143 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 144 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 145 dev_err(sdev->dev, 146 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 147 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 148 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 149 dev_err(sdev->dev, 150 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 151 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 152 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 153 154 } 155 156 /* 157 * IPC Doorbell IRQ handler and thread. 158 */ 159 160 static irqreturn_t byt_irq_handler(int irq, void *context) 161 { 162 struct snd_sof_dev *sdev = context; 163 u64 ipcx, ipcd; 164 int ret = IRQ_NONE; 165 166 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 167 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 168 169 if (ipcx & SHIM_BYT_IPCX_DONE) { 170 171 /* reply message from DSP, Mask Done interrupt first */ 172 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 173 SHIM_IMRX, 174 SHIM_IMRX_DONE, 175 SHIM_IMRX_DONE); 176 ret = IRQ_WAKE_THREAD; 177 } 178 179 if (ipcd & SHIM_BYT_IPCD_BUSY) { 180 181 /* new message from DSP, Mask Busy interrupt first */ 182 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 183 SHIM_IMRX, 184 SHIM_IMRX_BUSY, 185 SHIM_IMRX_BUSY); 186 ret = IRQ_WAKE_THREAD; 187 } 188 189 return ret; 190 } 191 192 static irqreturn_t byt_irq_thread(int irq, void *context) 193 { 194 struct snd_sof_dev *sdev = context; 195 u64 ipcx, ipcd; 196 197 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 198 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 199 200 /* reply message from DSP */ 201 if (ipcx & SHIM_BYT_IPCX_DONE) { 202 203 spin_lock_irq(&sdev->ipc_lock); 204 205 /* 206 * handle immediate reply from DSP core. If the msg is 207 * found, set done bit in cmd_done which is called at the 208 * end of message processing function, else set it here 209 * because the done bit can't be set in cmd_done function 210 * which is triggered by msg 211 */ 212 byt_get_reply(sdev); 213 snd_sof_ipc_reply(sdev, ipcx); 214 215 byt_dsp_done(sdev); 216 217 spin_unlock_irq(&sdev->ipc_lock); 218 } 219 220 /* new message from DSP */ 221 if (ipcd & SHIM_BYT_IPCD_BUSY) { 222 223 /* Handle messages from DSP Core */ 224 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 225 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 226 MBOX_OFFSET); 227 } else { 228 snd_sof_ipc_msgs_rx(sdev); 229 } 230 231 byt_host_done(sdev); 232 } 233 234 return IRQ_HANDLED; 235 } 236 237 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 238 { 239 /* unmask and prepare to receive Done interrupt */ 240 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 241 SHIM_IMRX_DONE, 0); 242 243 /* send the message */ 244 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 245 msg->msg_size); 246 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 247 248 return 0; 249 } 250 251 static void byt_get_reply(struct snd_sof_dev *sdev) 252 { 253 struct snd_sof_ipc_msg *msg = sdev->msg; 254 struct sof_ipc_reply reply; 255 int ret = 0; 256 257 /* 258 * Sometimes, there is unexpected reply ipc arriving. The reply 259 * ipc belongs to none of the ipcs sent from driver. 260 * In this case, the driver must ignore the ipc. 261 */ 262 if (!msg) { 263 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 264 return; 265 } 266 267 /* get reply */ 268 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 269 270 if (reply.error < 0) { 271 memcpy(msg->reply_data, &reply, sizeof(reply)); 272 ret = reply.error; 273 } else { 274 /* reply correct size ? */ 275 if (reply.hdr.size != msg->reply_size) { 276 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 277 msg->reply_size, reply.hdr.size); 278 ret = -EINVAL; 279 } 280 281 /* read the message */ 282 if (msg->reply_size > 0) 283 sof_mailbox_read(sdev, sdev->host_box.offset, 284 msg->reply_data, msg->reply_size); 285 } 286 287 msg->reply_error = ret; 288 } 289 290 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 291 { 292 return MBOX_OFFSET; 293 } 294 295 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 296 { 297 return MBOX_OFFSET; 298 } 299 300 static void byt_host_done(struct snd_sof_dev *sdev) 301 { 302 /* clear BUSY bit and set DONE bit - accept new messages */ 303 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 304 SHIM_BYT_IPCD_BUSY | 305 SHIM_BYT_IPCD_DONE, 306 SHIM_BYT_IPCD_DONE); 307 308 /* unmask and prepare to receive next new message */ 309 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 310 SHIM_IMRX_BUSY, 0); 311 } 312 313 static void byt_dsp_done(struct snd_sof_dev *sdev) 314 { 315 /* clear DONE bit - tell DSP we have completed */ 316 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 317 SHIM_BYT_IPCX_DONE, 0); 318 } 319 320 /* 321 * DSP control. 322 */ 323 324 static int byt_run(struct snd_sof_dev *sdev) 325 { 326 int tries = 10; 327 328 /* release stall and wait to unstall */ 329 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 330 SHIM_BYT_CSR_STALL, 0x0); 331 while (tries--) { 332 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 333 SHIM_BYT_CSR_PWAITMODE)) 334 break; 335 msleep(100); 336 } 337 if (tries < 0) { 338 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 339 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 340 return -ENODEV; 341 } 342 343 /* return init core mask */ 344 return 1; 345 } 346 347 static int byt_reset(struct snd_sof_dev *sdev) 348 { 349 /* put DSP into reset, set reset vector and stall */ 350 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 351 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 352 SHIM_BYT_CSR_STALL, 353 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 354 SHIM_BYT_CSR_STALL); 355 356 usleep_range(10, 15); 357 358 /* take DSP out of reset and keep stalled for FW loading */ 359 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 360 SHIM_BYT_CSR_RST, 0); 361 362 return 0; 363 } 364 365 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 366 const char *sof_tplg_filename, 367 const char *ssp_str) 368 { 369 const char *tplg_filename = NULL; 370 char *filename; 371 char *split_ext; 372 373 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 374 if (!filename) 375 return NULL; 376 377 /* this assumes a .tplg extension */ 378 split_ext = strsep(&filename, "."); 379 if (split_ext) { 380 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 381 "%s-%s.tplg", 382 split_ext, ssp_str); 383 if (!tplg_filename) 384 return NULL; 385 } 386 return tplg_filename; 387 } 388 389 static void byt_machine_select(struct snd_sof_dev *sdev) 390 { 391 struct snd_sof_pdata *sof_pdata = sdev->pdata; 392 const struct sof_dev_desc *desc = sof_pdata->desc; 393 struct snd_soc_acpi_mach *mach; 394 struct platform_device *pdev; 395 const char *tplg_filename; 396 397 mach = snd_soc_acpi_find_machine(desc->machines); 398 if (!mach) { 399 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 400 return; 401 } 402 403 pdev = to_platform_device(sdev->dev); 404 if (soc_intel_is_byt_cr(pdev)) { 405 dev_dbg(sdev->dev, 406 "BYT-CR detected, SSP0 used instead of SSP2\n"); 407 408 tplg_filename = fixup_tplg_name(sdev, 409 mach->sof_tplg_filename, 410 "ssp0"); 411 } else { 412 tplg_filename = mach->sof_tplg_filename; 413 } 414 415 if (!tplg_filename) { 416 dev_dbg(sdev->dev, 417 "error: no topology filename\n"); 418 return; 419 } 420 421 sof_pdata->tplg_filename = tplg_filename; 422 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 423 sof_pdata->machine = mach; 424 } 425 426 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 427 struct device *dev) 428 { 429 struct snd_soc_acpi_mach_params *mach_params; 430 431 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 432 mach_params->platform = dev_name(dev); 433 } 434 435 /* Baytrail DAIs */ 436 static struct snd_soc_dai_driver byt_dai[] = { 437 { 438 .name = "ssp0-port", 439 .playback = { 440 .channels_min = 1, 441 .channels_max = 8, 442 }, 443 .capture = { 444 .channels_min = 1, 445 .channels_max = 8, 446 }, 447 }, 448 { 449 .name = "ssp1-port", 450 .playback = { 451 .channels_min = 1, 452 .channels_max = 8, 453 }, 454 .capture = { 455 .channels_min = 1, 456 .channels_max = 8, 457 }, 458 }, 459 { 460 .name = "ssp2-port", 461 .playback = { 462 .channels_min = 1, 463 .channels_max = 8, 464 }, 465 .capture = { 466 .channels_min = 1, 467 .channels_max = 8, 468 } 469 }, 470 { 471 .name = "ssp3-port", 472 .playback = { 473 .channels_min = 1, 474 .channels_max = 8, 475 }, 476 .capture = { 477 .channels_min = 1, 478 .channels_max = 8, 479 }, 480 }, 481 { 482 .name = "ssp4-port", 483 .playback = { 484 .channels_min = 1, 485 .channels_max = 8, 486 }, 487 .capture = { 488 .channels_min = 1, 489 .channels_max = 8, 490 }, 491 }, 492 { 493 .name = "ssp5-port", 494 .playback = { 495 .channels_min = 1, 496 .channels_max = 8, 497 }, 498 .capture = { 499 .channels_min = 1, 500 .channels_max = 8, 501 }, 502 }, 503 }; 504 505 /* 506 * Probe and remove. 507 */ 508 509 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 510 511 static int tangier_pci_probe(struct snd_sof_dev *sdev) 512 { 513 struct snd_sof_pdata *pdata = sdev->pdata; 514 const struct sof_dev_desc *desc = pdata->desc; 515 struct pci_dev *pci = to_pci_dev(sdev->dev); 516 u32 base, size; 517 int ret; 518 519 /* DSP DMA can only access low 31 bits of host memory */ 520 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 521 if (ret < 0) { 522 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 523 return ret; 524 } 525 526 /* LPE base */ 527 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 528 size = BYT_PCI_BAR_SIZE; 529 530 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 531 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 532 if (!sdev->bar[BYT_DSP_BAR]) { 533 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 534 base, size); 535 return -ENODEV; 536 } 537 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 538 539 /* IMR base - optional */ 540 if (desc->resindex_imr_base == -1) 541 goto irq; 542 543 base = pci_resource_start(pci, desc->resindex_imr_base); 544 size = pci_resource_len(pci, desc->resindex_imr_base); 545 546 /* some BIOSes don't map IMR */ 547 if (base == 0x55aa55aa || base == 0x0) { 548 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 549 goto irq; 550 } 551 552 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 553 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 554 if (!sdev->bar[BYT_IMR_BAR]) { 555 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 556 base, size); 557 return -ENODEV; 558 } 559 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 560 561 irq: 562 /* register our IRQ */ 563 sdev->ipc_irq = pci->irq; 564 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 565 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 566 byt_irq_handler, byt_irq_thread, 567 0, "AudioDSP", sdev); 568 if (ret < 0) { 569 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 570 sdev->ipc_irq); 571 return ret; 572 } 573 574 /* enable BUSY and disable DONE Interrupt by default */ 575 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 576 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 577 SHIM_IMRX_DONE); 578 579 /* set default mailbox offset for FW ready message */ 580 sdev->dsp_box.offset = MBOX_OFFSET; 581 582 return ret; 583 } 584 585 const struct snd_sof_dsp_ops sof_tng_ops = { 586 /* device init */ 587 .probe = tangier_pci_probe, 588 589 /* DSP core boot / reset */ 590 .run = byt_run, 591 .reset = byt_reset, 592 593 /* Register IO */ 594 .write = sof_io_write, 595 .read = sof_io_read, 596 .write64 = sof_io_write64, 597 .read64 = sof_io_read64, 598 599 /* Block IO */ 600 .block_read = sof_block_read, 601 .block_write = sof_block_write, 602 603 /* doorbell */ 604 .irq_handler = byt_irq_handler, 605 .irq_thread = byt_irq_thread, 606 607 /* ipc */ 608 .send_msg = byt_send_msg, 609 .fw_ready = sof_fw_ready, 610 .get_mailbox_offset = byt_get_mailbox_offset, 611 .get_window_offset = byt_get_window_offset, 612 613 .ipc_msg_data = intel_ipc_msg_data, 614 .ipc_pcm_params = intel_ipc_pcm_params, 615 616 /* machine driver */ 617 .machine_select = byt_machine_select, 618 .machine_register = sof_machine_register, 619 .machine_unregister = sof_machine_unregister, 620 .set_mach_params = byt_set_mach_params, 621 622 /* debug */ 623 .debug_map = byt_debugfs, 624 .debug_map_count = ARRAY_SIZE(byt_debugfs), 625 .dbg_dump = byt_dump, 626 627 /* stream callbacks */ 628 .pcm_open = intel_pcm_open, 629 .pcm_close = intel_pcm_close, 630 631 /* module loading */ 632 .load_module = snd_sof_parse_module_memcpy, 633 634 /*Firmware loading */ 635 .load_firmware = snd_sof_load_firmware_memcpy, 636 637 /* DAI drivers */ 638 .drv = byt_dai, 639 .num_drv = 3, /* we have only 3 SSPs on byt*/ 640 641 /* ALSA HW info flags */ 642 .hw_info = SNDRV_PCM_INFO_MMAP | 643 SNDRV_PCM_INFO_MMAP_VALID | 644 SNDRV_PCM_INFO_INTERLEAVED | 645 SNDRV_PCM_INFO_PAUSE | 646 SNDRV_PCM_INFO_BATCH, 647 648 .arch_ops = &sof_xtensa_arch_ops, 649 }; 650 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 651 652 const struct sof_intel_dsp_desc tng_chip_info = { 653 .cores_num = 1, 654 .host_managed_cores_mask = 1, 655 }; 656 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 657 658 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 659 660 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 661 662 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 663 { 664 /* Disable Interrupt from both sides */ 665 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 666 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 667 668 /* Put DSP into reset, set reset vector */ 669 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 670 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 671 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 672 } 673 674 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 675 { 676 byt_reset_dsp_disable_int(sdev); 677 678 return 0; 679 } 680 681 static int byt_resume(struct snd_sof_dev *sdev) 682 { 683 /* enable BUSY and disable DONE Interrupt by default */ 684 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 685 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 686 SHIM_IMRX_DONE); 687 688 return 0; 689 } 690 691 static int byt_remove(struct snd_sof_dev *sdev) 692 { 693 byt_reset_dsp_disable_int(sdev); 694 695 return 0; 696 } 697 698 static const struct snd_sof_debugfs_map cht_debugfs[] = { 699 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 700 SOF_DEBUGFS_ACCESS_ALWAYS}, 701 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 702 SOF_DEBUGFS_ACCESS_ALWAYS}, 703 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 704 SOF_DEBUGFS_ACCESS_ALWAYS}, 705 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 706 SOF_DEBUGFS_ACCESS_ALWAYS}, 707 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 708 SOF_DEBUGFS_ACCESS_ALWAYS}, 709 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 710 SOF_DEBUGFS_ACCESS_ALWAYS}, 711 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 712 SOF_DEBUGFS_ACCESS_ALWAYS}, 713 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 714 SOF_DEBUGFS_ACCESS_ALWAYS}, 715 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 716 SOF_DEBUGFS_ACCESS_ALWAYS}, 717 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 718 SOF_DEBUGFS_ACCESS_D0_ONLY}, 719 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 720 SOF_DEBUGFS_ACCESS_D0_ONLY}, 721 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 722 SOF_DEBUGFS_ACCESS_ALWAYS}, 723 }; 724 725 static int byt_acpi_probe(struct snd_sof_dev *sdev) 726 { 727 struct snd_sof_pdata *pdata = sdev->pdata; 728 const struct sof_dev_desc *desc = pdata->desc; 729 struct platform_device *pdev = 730 container_of(sdev->dev, struct platform_device, dev); 731 struct resource *mmio; 732 u32 base, size; 733 int ret; 734 735 /* DSP DMA can only access low 31 bits of host memory */ 736 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 737 if (ret < 0) { 738 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 739 return ret; 740 } 741 742 /* LPE base */ 743 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 744 desc->resindex_lpe_base); 745 if (mmio) { 746 base = mmio->start; 747 size = resource_size(mmio); 748 } else { 749 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 750 desc->resindex_lpe_base); 751 return -EINVAL; 752 } 753 754 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 755 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 756 if (!sdev->bar[BYT_DSP_BAR]) { 757 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 758 base, size); 759 return -ENODEV; 760 } 761 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 762 763 /* TODO: add offsets */ 764 sdev->mmio_bar = BYT_DSP_BAR; 765 sdev->mailbox_bar = BYT_DSP_BAR; 766 767 /* IMR base - optional */ 768 if (desc->resindex_imr_base == -1) 769 goto irq; 770 771 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 772 desc->resindex_imr_base); 773 if (mmio) { 774 base = mmio->start; 775 size = resource_size(mmio); 776 } else { 777 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 778 desc->resindex_imr_base); 779 return -ENODEV; 780 } 781 782 /* some BIOSes don't map IMR */ 783 if (base == 0x55aa55aa || base == 0x0) { 784 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 785 goto irq; 786 } 787 788 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 789 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 790 if (!sdev->bar[BYT_IMR_BAR]) { 791 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 792 base, size); 793 return -ENODEV; 794 } 795 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 796 797 irq: 798 /* register our IRQ */ 799 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 800 if (sdev->ipc_irq < 0) 801 return sdev->ipc_irq; 802 803 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 804 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 805 byt_irq_handler, byt_irq_thread, 806 IRQF_SHARED, "AudioDSP", sdev); 807 if (ret < 0) { 808 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 809 sdev->ipc_irq); 810 return ret; 811 } 812 813 /* enable BUSY and disable DONE Interrupt by default */ 814 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 815 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 816 SHIM_IMRX_DONE); 817 818 /* set default mailbox offset for FW ready message */ 819 sdev->dsp_box.offset = MBOX_OFFSET; 820 821 return ret; 822 } 823 824 /* baytrail ops */ 825 const struct snd_sof_dsp_ops sof_byt_ops = { 826 /* device init */ 827 .probe = byt_acpi_probe, 828 .remove = byt_remove, 829 830 /* DSP core boot / reset */ 831 .run = byt_run, 832 .reset = byt_reset, 833 834 /* Register IO */ 835 .write = sof_io_write, 836 .read = sof_io_read, 837 .write64 = sof_io_write64, 838 .read64 = sof_io_read64, 839 840 /* Block IO */ 841 .block_read = sof_block_read, 842 .block_write = sof_block_write, 843 844 /* doorbell */ 845 .irq_handler = byt_irq_handler, 846 .irq_thread = byt_irq_thread, 847 848 /* ipc */ 849 .send_msg = byt_send_msg, 850 .fw_ready = sof_fw_ready, 851 .get_mailbox_offset = byt_get_mailbox_offset, 852 .get_window_offset = byt_get_window_offset, 853 854 .ipc_msg_data = intel_ipc_msg_data, 855 .ipc_pcm_params = intel_ipc_pcm_params, 856 857 /* machine driver */ 858 .machine_select = byt_machine_select, 859 .machine_register = sof_machine_register, 860 .machine_unregister = sof_machine_unregister, 861 .set_mach_params = byt_set_mach_params, 862 863 /* debug */ 864 .debug_map = byt_debugfs, 865 .debug_map_count = ARRAY_SIZE(byt_debugfs), 866 .dbg_dump = byt_dump, 867 868 /* stream callbacks */ 869 .pcm_open = intel_pcm_open, 870 .pcm_close = intel_pcm_close, 871 872 /* module loading */ 873 .load_module = snd_sof_parse_module_memcpy, 874 875 /*Firmware loading */ 876 .load_firmware = snd_sof_load_firmware_memcpy, 877 878 /* PM */ 879 .suspend = byt_suspend, 880 .resume = byt_resume, 881 882 /* DAI drivers */ 883 .drv = byt_dai, 884 .num_drv = 3, /* we have only 3 SSPs on byt*/ 885 886 /* ALSA HW info flags */ 887 .hw_info = SNDRV_PCM_INFO_MMAP | 888 SNDRV_PCM_INFO_MMAP_VALID | 889 SNDRV_PCM_INFO_INTERLEAVED | 890 SNDRV_PCM_INFO_PAUSE | 891 SNDRV_PCM_INFO_BATCH, 892 893 .arch_ops = &sof_xtensa_arch_ops, 894 }; 895 EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 896 897 const struct sof_intel_dsp_desc byt_chip_info = { 898 .cores_num = 1, 899 .host_managed_cores_mask = 1, 900 }; 901 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 902 903 /* cherrytrail and braswell ops */ 904 const struct snd_sof_dsp_ops sof_cht_ops = { 905 /* device init */ 906 .probe = byt_acpi_probe, 907 .remove = byt_remove, 908 909 /* DSP core boot / reset */ 910 .run = byt_run, 911 .reset = byt_reset, 912 913 /* Register IO */ 914 .write = sof_io_write, 915 .read = sof_io_read, 916 .write64 = sof_io_write64, 917 .read64 = sof_io_read64, 918 919 /* Block IO */ 920 .block_read = sof_block_read, 921 .block_write = sof_block_write, 922 923 /* doorbell */ 924 .irq_handler = byt_irq_handler, 925 .irq_thread = byt_irq_thread, 926 927 /* ipc */ 928 .send_msg = byt_send_msg, 929 .fw_ready = sof_fw_ready, 930 .get_mailbox_offset = byt_get_mailbox_offset, 931 .get_window_offset = byt_get_window_offset, 932 933 .ipc_msg_data = intel_ipc_msg_data, 934 .ipc_pcm_params = intel_ipc_pcm_params, 935 936 /* machine driver */ 937 .machine_select = byt_machine_select, 938 .machine_register = sof_machine_register, 939 .machine_unregister = sof_machine_unregister, 940 .set_mach_params = byt_set_mach_params, 941 942 /* debug */ 943 .debug_map = cht_debugfs, 944 .debug_map_count = ARRAY_SIZE(cht_debugfs), 945 .dbg_dump = byt_dump, 946 947 /* stream callbacks */ 948 .pcm_open = intel_pcm_open, 949 .pcm_close = intel_pcm_close, 950 951 /* module loading */ 952 .load_module = snd_sof_parse_module_memcpy, 953 954 /*Firmware loading */ 955 .load_firmware = snd_sof_load_firmware_memcpy, 956 957 /* PM */ 958 .suspend = byt_suspend, 959 .resume = byt_resume, 960 961 /* DAI drivers */ 962 .drv = byt_dai, 963 /* all 6 SSPs may be available for cherrytrail */ 964 .num_drv = ARRAY_SIZE(byt_dai), 965 966 /* ALSA HW info flags */ 967 .hw_info = SNDRV_PCM_INFO_MMAP | 968 SNDRV_PCM_INFO_MMAP_VALID | 969 SNDRV_PCM_INFO_INTERLEAVED | 970 SNDRV_PCM_INFO_PAUSE | 971 SNDRV_PCM_INFO_BATCH, 972 973 .arch_ops = &sof_xtensa_arch_ops, 974 }; 975 EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 976 977 const struct sof_intel_dsp_desc cht_chip_info = { 978 .cores_num = 1, 979 .host_managed_cores_mask = 1, 980 }; 981 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 982 983 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 984 985 MODULE_LICENSE("Dual BSD/GPL"); 986 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 987 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 988