1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include <sound/soc-acpi.h> 19 #include <sound/soc-acpi-intel-match.h> 20 #include <sound/intel-dsp-config.h> 21 #include "../ops.h" 22 #include "shim.h" 23 #include "../sof-acpi-dev.h" 24 #include "../sof-audio.h" 25 #include "../../intel/common/soc-intel-quirks.h" 26 27 /* DSP memories */ 28 #define IRAM_OFFSET 0x0C0000 29 #define IRAM_SIZE (80 * 1024) 30 #define DRAM_OFFSET 0x100000 31 #define DRAM_SIZE (160 * 1024) 32 #define SHIM_OFFSET 0x140000 33 #define SHIM_SIZE_BYT 0x100 34 #define SHIM_SIZE_CHT 0x118 35 #define MBOX_OFFSET 0x144000 36 #define MBOX_SIZE 0x1000 37 #define EXCEPT_OFFSET 0x800 38 #define EXCEPT_MAX_HDR_SIZE 0x400 39 40 /* DSP peripherals */ 41 #define DMAC0_OFFSET 0x098000 42 #define DMAC1_OFFSET 0x09c000 43 #define DMAC2_OFFSET 0x094000 44 #define DMAC_SIZE 0x420 45 #define SSP0_OFFSET 0x0a0000 46 #define SSP1_OFFSET 0x0a1000 47 #define SSP2_OFFSET 0x0a2000 48 #define SSP3_OFFSET 0x0a4000 49 #define SSP4_OFFSET 0x0a5000 50 #define SSP5_OFFSET 0x0a6000 51 #define SSP_SIZE 0x100 52 53 #define BYT_STACK_DUMP_SIZE 32 54 55 #define BYT_PCI_BAR_SIZE 0x200000 56 57 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 58 59 /* 60 * Debug 61 */ 62 63 #define MBOX_DUMP_SIZE 0x30 64 65 /* BARs */ 66 #define BYT_DSP_BAR 0 67 #define BYT_PCI_BAR 1 68 #define BYT_IMR_BAR 2 69 70 static const struct snd_sof_debugfs_map byt_debugfs[] = { 71 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 78 SOF_DEBUGFS_ACCESS_ALWAYS}, 79 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 80 SOF_DEBUGFS_ACCESS_ALWAYS}, 81 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 82 SOF_DEBUGFS_ACCESS_D0_ONLY}, 83 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 84 SOF_DEBUGFS_ACCESS_D0_ONLY}, 85 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 86 SOF_DEBUGFS_ACCESS_ALWAYS}, 87 }; 88 89 static void byt_host_done(struct snd_sof_dev *sdev); 90 static void byt_dsp_done(struct snd_sof_dev *sdev); 91 static void byt_get_reply(struct snd_sof_dev *sdev); 92 93 /* 94 * Debug 95 */ 96 97 static void byt_get_registers(struct snd_sof_dev *sdev, 98 struct sof_ipc_dsp_oops_xtensa *xoops, 99 struct sof_ipc_panic_info *panic_info, 100 u32 *stack, size_t stack_words) 101 { 102 u32 offset = sdev->dsp_oops_offset; 103 104 /* first read regsisters */ 105 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 106 107 /* note: variable AR register array is not read */ 108 109 /* then get panic info */ 110 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 111 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 112 xoops->arch_hdr.totalsize); 113 return; 114 } 115 offset += xoops->arch_hdr.totalsize; 116 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 117 118 /* then get the stack */ 119 offset += sizeof(*panic_info); 120 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 121 } 122 123 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 124 { 125 struct sof_ipc_dsp_oops_xtensa xoops; 126 struct sof_ipc_panic_info panic_info; 127 u32 stack[BYT_STACK_DUMP_SIZE]; 128 u64 status, panic, imrd, imrx; 129 130 /* now try generic SOF status messages */ 131 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 132 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 133 byt_get_registers(sdev, &xoops, &panic_info, stack, 134 BYT_STACK_DUMP_SIZE); 135 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 136 BYT_STACK_DUMP_SIZE); 137 138 /* provide some context for firmware debug */ 139 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 140 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 141 dev_err(sdev->dev, 142 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 143 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 144 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 145 dev_err(sdev->dev, 146 "error: mask host: pending %s complete %s raw 0x%llx\n", 147 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 148 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 149 dev_err(sdev->dev, 150 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 151 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 152 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 153 dev_err(sdev->dev, 154 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 155 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 156 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 157 158 } 159 160 /* 161 * IPC Doorbell IRQ handler and thread. 162 */ 163 164 static irqreturn_t byt_irq_handler(int irq, void *context) 165 { 166 struct snd_sof_dev *sdev = context; 167 u64 ipcx, ipcd; 168 int ret = IRQ_NONE; 169 170 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 171 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 172 173 if (ipcx & SHIM_BYT_IPCX_DONE) { 174 175 /* reply message from DSP, Mask Done interrupt first */ 176 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 177 SHIM_IMRX, 178 SHIM_IMRX_DONE, 179 SHIM_IMRX_DONE); 180 ret = IRQ_WAKE_THREAD; 181 } 182 183 if (ipcd & SHIM_BYT_IPCD_BUSY) { 184 185 /* new message from DSP, Mask Busy interrupt first */ 186 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 187 SHIM_IMRX, 188 SHIM_IMRX_BUSY, 189 SHIM_IMRX_BUSY); 190 ret = IRQ_WAKE_THREAD; 191 } 192 193 return ret; 194 } 195 196 static irqreturn_t byt_irq_thread(int irq, void *context) 197 { 198 struct snd_sof_dev *sdev = context; 199 u64 ipcx, ipcd; 200 201 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 202 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 203 204 /* reply message from DSP */ 205 if (ipcx & SHIM_BYT_IPCX_DONE) { 206 207 spin_lock_irq(&sdev->ipc_lock); 208 209 /* 210 * handle immediate reply from DSP core. If the msg is 211 * found, set done bit in cmd_done which is called at the 212 * end of message processing function, else set it here 213 * because the done bit can't be set in cmd_done function 214 * which is triggered by msg 215 */ 216 byt_get_reply(sdev); 217 snd_sof_ipc_reply(sdev, ipcx); 218 219 byt_dsp_done(sdev); 220 221 spin_unlock_irq(&sdev->ipc_lock); 222 } 223 224 /* new message from DSP */ 225 if (ipcd & SHIM_BYT_IPCD_BUSY) { 226 227 /* Handle messages from DSP Core */ 228 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 229 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 230 MBOX_OFFSET); 231 } else { 232 snd_sof_ipc_msgs_rx(sdev); 233 } 234 235 byt_host_done(sdev); 236 } 237 238 return IRQ_HANDLED; 239 } 240 241 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 242 { 243 /* unmask and prepare to receive Done interrupt */ 244 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 245 SHIM_IMRX_DONE, 0); 246 247 /* send the message */ 248 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 249 msg->msg_size); 250 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 251 252 return 0; 253 } 254 255 static void byt_get_reply(struct snd_sof_dev *sdev) 256 { 257 struct snd_sof_ipc_msg *msg = sdev->msg; 258 struct sof_ipc_reply reply; 259 int ret = 0; 260 261 /* 262 * Sometimes, there is unexpected reply ipc arriving. The reply 263 * ipc belongs to none of the ipcs sent from driver. 264 * In this case, the driver must ignore the ipc. 265 */ 266 if (!msg) { 267 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 268 return; 269 } 270 271 /* get reply */ 272 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 273 274 if (reply.error < 0) { 275 memcpy(msg->reply_data, &reply, sizeof(reply)); 276 ret = reply.error; 277 } else { 278 /* reply correct size ? */ 279 if (reply.hdr.size != msg->reply_size) { 280 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 281 msg->reply_size, reply.hdr.size); 282 ret = -EINVAL; 283 } 284 285 /* read the message */ 286 if (msg->reply_size > 0) 287 sof_mailbox_read(sdev, sdev->host_box.offset, 288 msg->reply_data, msg->reply_size); 289 } 290 291 msg->reply_error = ret; 292 } 293 294 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 295 { 296 return MBOX_OFFSET; 297 } 298 299 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 300 { 301 return MBOX_OFFSET; 302 } 303 304 static void byt_host_done(struct snd_sof_dev *sdev) 305 { 306 /* clear BUSY bit and set DONE bit - accept new messages */ 307 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 308 SHIM_BYT_IPCD_BUSY | 309 SHIM_BYT_IPCD_DONE, 310 SHIM_BYT_IPCD_DONE); 311 312 /* unmask and prepare to receive next new message */ 313 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 314 SHIM_IMRX_BUSY, 0); 315 } 316 317 static void byt_dsp_done(struct snd_sof_dev *sdev) 318 { 319 /* clear DONE bit - tell DSP we have completed */ 320 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 321 SHIM_BYT_IPCX_DONE, 0); 322 } 323 324 /* 325 * DSP control. 326 */ 327 328 static int byt_run(struct snd_sof_dev *sdev) 329 { 330 int tries = 10; 331 332 /* release stall and wait to unstall */ 333 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 334 SHIM_BYT_CSR_STALL, 0x0); 335 while (tries--) { 336 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 337 SHIM_BYT_CSR_PWAITMODE)) 338 break; 339 msleep(100); 340 } 341 if (tries < 0) { 342 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 343 byt_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX); 344 return -ENODEV; 345 } 346 347 /* return init core mask */ 348 return 1; 349 } 350 351 static int byt_reset(struct snd_sof_dev *sdev) 352 { 353 /* put DSP into reset, set reset vector and stall */ 354 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 355 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 356 SHIM_BYT_CSR_STALL, 357 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 358 SHIM_BYT_CSR_STALL); 359 360 usleep_range(10, 15); 361 362 /* take DSP out of reset and keep stalled for FW loading */ 363 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 364 SHIM_BYT_CSR_RST, 0); 365 366 return 0; 367 } 368 369 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 370 const char *sof_tplg_filename, 371 const char *ssp_str) 372 { 373 const char *tplg_filename = NULL; 374 char *filename; 375 char *split_ext; 376 377 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 378 if (!filename) 379 return NULL; 380 381 /* this assumes a .tplg extension */ 382 split_ext = strsep(&filename, "."); 383 if (split_ext) { 384 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 385 "%s-%s.tplg", 386 split_ext, ssp_str); 387 if (!tplg_filename) 388 return NULL; 389 } 390 return tplg_filename; 391 } 392 393 static void byt_machine_select(struct snd_sof_dev *sdev) 394 { 395 struct snd_sof_pdata *sof_pdata = sdev->pdata; 396 const struct sof_dev_desc *desc = sof_pdata->desc; 397 struct snd_soc_acpi_mach *mach; 398 struct platform_device *pdev; 399 const char *tplg_filename; 400 401 mach = snd_soc_acpi_find_machine(desc->machines); 402 if (!mach) { 403 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 404 return; 405 } 406 407 pdev = to_platform_device(sdev->dev); 408 if (soc_intel_is_byt_cr(pdev)) { 409 dev_dbg(sdev->dev, 410 "BYT-CR detected, SSP0 used instead of SSP2\n"); 411 412 tplg_filename = fixup_tplg_name(sdev, 413 mach->sof_tplg_filename, 414 "ssp0"); 415 } else { 416 tplg_filename = mach->sof_tplg_filename; 417 } 418 419 if (!tplg_filename) { 420 dev_dbg(sdev->dev, 421 "error: no topology filename\n"); 422 return; 423 } 424 425 sof_pdata->tplg_filename = tplg_filename; 426 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 427 sof_pdata->machine = mach; 428 } 429 430 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 431 struct device *dev) 432 { 433 struct snd_soc_acpi_mach_params *mach_params; 434 435 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 436 mach_params->platform = dev_name(dev); 437 } 438 439 /* Baytrail DAIs */ 440 static struct snd_soc_dai_driver byt_dai[] = { 441 { 442 .name = "ssp0-port", 443 .playback = { 444 .channels_min = 1, 445 .channels_max = 8, 446 }, 447 .capture = { 448 .channels_min = 1, 449 .channels_max = 8, 450 }, 451 }, 452 { 453 .name = "ssp1-port", 454 .playback = { 455 .channels_min = 1, 456 .channels_max = 8, 457 }, 458 .capture = { 459 .channels_min = 1, 460 .channels_max = 8, 461 }, 462 }, 463 { 464 .name = "ssp2-port", 465 .playback = { 466 .channels_min = 1, 467 .channels_max = 8, 468 }, 469 .capture = { 470 .channels_min = 1, 471 .channels_max = 8, 472 } 473 }, 474 { 475 .name = "ssp3-port", 476 .playback = { 477 .channels_min = 1, 478 .channels_max = 8, 479 }, 480 .capture = { 481 .channels_min = 1, 482 .channels_max = 8, 483 }, 484 }, 485 { 486 .name = "ssp4-port", 487 .playback = { 488 .channels_min = 1, 489 .channels_max = 8, 490 }, 491 .capture = { 492 .channels_min = 1, 493 .channels_max = 8, 494 }, 495 }, 496 { 497 .name = "ssp5-port", 498 .playback = { 499 .channels_min = 1, 500 .channels_max = 8, 501 }, 502 .capture = { 503 .channels_min = 1, 504 .channels_max = 8, 505 }, 506 }, 507 }; 508 509 /* 510 * Probe and remove. 511 */ 512 513 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 514 515 static int tangier_pci_probe(struct snd_sof_dev *sdev) 516 { 517 struct snd_sof_pdata *pdata = sdev->pdata; 518 const struct sof_dev_desc *desc = pdata->desc; 519 struct pci_dev *pci = to_pci_dev(sdev->dev); 520 u32 base, size; 521 int ret; 522 523 /* DSP DMA can only access low 31 bits of host memory */ 524 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 525 if (ret < 0) { 526 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 527 return ret; 528 } 529 530 /* LPE base */ 531 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 532 size = BYT_PCI_BAR_SIZE; 533 534 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 535 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 536 if (!sdev->bar[BYT_DSP_BAR]) { 537 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 538 base, size); 539 return -ENODEV; 540 } 541 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 542 543 /* IMR base - optional */ 544 if (desc->resindex_imr_base == -1) 545 goto irq; 546 547 base = pci_resource_start(pci, desc->resindex_imr_base); 548 size = pci_resource_len(pci, desc->resindex_imr_base); 549 550 /* some BIOSes don't map IMR */ 551 if (base == 0x55aa55aa || base == 0x0) { 552 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 553 goto irq; 554 } 555 556 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 557 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 558 if (!sdev->bar[BYT_IMR_BAR]) { 559 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 560 base, size); 561 return -ENODEV; 562 } 563 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 564 565 irq: 566 /* register our IRQ */ 567 sdev->ipc_irq = pci->irq; 568 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 569 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 570 byt_irq_handler, byt_irq_thread, 571 0, "AudioDSP", sdev); 572 if (ret < 0) { 573 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 574 sdev->ipc_irq); 575 return ret; 576 } 577 578 /* enable BUSY and disable DONE Interrupt by default */ 579 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 580 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 581 SHIM_IMRX_DONE); 582 583 /* set default mailbox offset for FW ready message */ 584 sdev->dsp_box.offset = MBOX_OFFSET; 585 586 return ret; 587 } 588 589 const struct snd_sof_dsp_ops sof_tng_ops = { 590 /* device init */ 591 .probe = tangier_pci_probe, 592 593 /* DSP core boot / reset */ 594 .run = byt_run, 595 .reset = byt_reset, 596 597 /* Register IO */ 598 .write = sof_io_write, 599 .read = sof_io_read, 600 .write64 = sof_io_write64, 601 .read64 = sof_io_read64, 602 603 /* Block IO */ 604 .block_read = sof_block_read, 605 .block_write = sof_block_write, 606 607 /* doorbell */ 608 .irq_handler = byt_irq_handler, 609 .irq_thread = byt_irq_thread, 610 611 /* ipc */ 612 .send_msg = byt_send_msg, 613 .fw_ready = sof_fw_ready, 614 .get_mailbox_offset = byt_get_mailbox_offset, 615 .get_window_offset = byt_get_window_offset, 616 617 .ipc_msg_data = intel_ipc_msg_data, 618 .ipc_pcm_params = intel_ipc_pcm_params, 619 620 /* machine driver */ 621 .machine_select = byt_machine_select, 622 .machine_register = sof_machine_register, 623 .machine_unregister = sof_machine_unregister, 624 .set_mach_params = byt_set_mach_params, 625 626 /* debug */ 627 .debug_map = byt_debugfs, 628 .debug_map_count = ARRAY_SIZE(byt_debugfs), 629 .dbg_dump = byt_dump, 630 631 /* stream callbacks */ 632 .pcm_open = intel_pcm_open, 633 .pcm_close = intel_pcm_close, 634 635 /* module loading */ 636 .load_module = snd_sof_parse_module_memcpy, 637 638 /*Firmware loading */ 639 .load_firmware = snd_sof_load_firmware_memcpy, 640 641 /* DAI drivers */ 642 .drv = byt_dai, 643 .num_drv = 3, /* we have only 3 SSPs on byt*/ 644 645 /* ALSA HW info flags */ 646 .hw_info = SNDRV_PCM_INFO_MMAP | 647 SNDRV_PCM_INFO_MMAP_VALID | 648 SNDRV_PCM_INFO_INTERLEAVED | 649 SNDRV_PCM_INFO_PAUSE | 650 SNDRV_PCM_INFO_BATCH, 651 652 .arch_ops = &sof_xtensa_arch_ops, 653 }; 654 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 655 656 const struct sof_intel_dsp_desc tng_chip_info = { 657 .cores_num = 1, 658 .host_managed_cores_mask = 1, 659 }; 660 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 661 662 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 663 664 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 665 666 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 667 { 668 /* Disable Interrupt from both sides */ 669 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 670 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 671 672 /* Put DSP into reset, set reset vector */ 673 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 674 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 675 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 676 } 677 678 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 679 { 680 byt_reset_dsp_disable_int(sdev); 681 682 return 0; 683 } 684 685 static int byt_resume(struct snd_sof_dev *sdev) 686 { 687 /* enable BUSY and disable DONE Interrupt by default */ 688 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 689 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 690 SHIM_IMRX_DONE); 691 692 return 0; 693 } 694 695 static int byt_remove(struct snd_sof_dev *sdev) 696 { 697 byt_reset_dsp_disable_int(sdev); 698 699 return 0; 700 } 701 702 static const struct snd_sof_debugfs_map cht_debugfs[] = { 703 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 704 SOF_DEBUGFS_ACCESS_ALWAYS}, 705 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 706 SOF_DEBUGFS_ACCESS_ALWAYS}, 707 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 708 SOF_DEBUGFS_ACCESS_ALWAYS}, 709 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 710 SOF_DEBUGFS_ACCESS_ALWAYS}, 711 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 712 SOF_DEBUGFS_ACCESS_ALWAYS}, 713 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 714 SOF_DEBUGFS_ACCESS_ALWAYS}, 715 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 716 SOF_DEBUGFS_ACCESS_ALWAYS}, 717 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 718 SOF_DEBUGFS_ACCESS_ALWAYS}, 719 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 720 SOF_DEBUGFS_ACCESS_ALWAYS}, 721 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 722 SOF_DEBUGFS_ACCESS_D0_ONLY}, 723 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 724 SOF_DEBUGFS_ACCESS_D0_ONLY}, 725 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 726 SOF_DEBUGFS_ACCESS_ALWAYS}, 727 }; 728 729 static int byt_acpi_probe(struct snd_sof_dev *sdev) 730 { 731 struct snd_sof_pdata *pdata = sdev->pdata; 732 const struct sof_dev_desc *desc = pdata->desc; 733 struct platform_device *pdev = 734 container_of(sdev->dev, struct platform_device, dev); 735 struct resource *mmio; 736 u32 base, size; 737 int ret; 738 739 /* DSP DMA can only access low 31 bits of host memory */ 740 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 741 if (ret < 0) { 742 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 743 return ret; 744 } 745 746 /* LPE base */ 747 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 748 desc->resindex_lpe_base); 749 if (mmio) { 750 base = mmio->start; 751 size = resource_size(mmio); 752 } else { 753 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 754 desc->resindex_lpe_base); 755 return -EINVAL; 756 } 757 758 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 759 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 760 if (!sdev->bar[BYT_DSP_BAR]) { 761 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 762 base, size); 763 return -ENODEV; 764 } 765 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 766 767 /* TODO: add offsets */ 768 sdev->mmio_bar = BYT_DSP_BAR; 769 sdev->mailbox_bar = BYT_DSP_BAR; 770 771 /* IMR base - optional */ 772 if (desc->resindex_imr_base == -1) 773 goto irq; 774 775 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 776 desc->resindex_imr_base); 777 if (mmio) { 778 base = mmio->start; 779 size = resource_size(mmio); 780 } else { 781 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 782 desc->resindex_imr_base); 783 return -ENODEV; 784 } 785 786 /* some BIOSes don't map IMR */ 787 if (base == 0x55aa55aa || base == 0x0) { 788 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 789 goto irq; 790 } 791 792 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 793 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 794 if (!sdev->bar[BYT_IMR_BAR]) { 795 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 796 base, size); 797 return -ENODEV; 798 } 799 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 800 801 irq: 802 /* register our IRQ */ 803 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 804 if (sdev->ipc_irq < 0) 805 return sdev->ipc_irq; 806 807 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 808 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 809 byt_irq_handler, byt_irq_thread, 810 IRQF_SHARED, "AudioDSP", sdev); 811 if (ret < 0) { 812 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 813 sdev->ipc_irq); 814 return ret; 815 } 816 817 /* enable BUSY and disable DONE Interrupt by default */ 818 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 819 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 820 SHIM_IMRX_DONE); 821 822 /* set default mailbox offset for FW ready message */ 823 sdev->dsp_box.offset = MBOX_OFFSET; 824 825 return ret; 826 } 827 828 /* baytrail ops */ 829 static const struct snd_sof_dsp_ops sof_byt_ops = { 830 /* device init */ 831 .probe = byt_acpi_probe, 832 .remove = byt_remove, 833 834 /* DSP core boot / reset */ 835 .run = byt_run, 836 .reset = byt_reset, 837 838 /* Register IO */ 839 .write = sof_io_write, 840 .read = sof_io_read, 841 .write64 = sof_io_write64, 842 .read64 = sof_io_read64, 843 844 /* Block IO */ 845 .block_read = sof_block_read, 846 .block_write = sof_block_write, 847 848 /* doorbell */ 849 .irq_handler = byt_irq_handler, 850 .irq_thread = byt_irq_thread, 851 852 /* ipc */ 853 .send_msg = byt_send_msg, 854 .fw_ready = sof_fw_ready, 855 .get_mailbox_offset = byt_get_mailbox_offset, 856 .get_window_offset = byt_get_window_offset, 857 858 .ipc_msg_data = intel_ipc_msg_data, 859 .ipc_pcm_params = intel_ipc_pcm_params, 860 861 /* machine driver */ 862 .machine_select = byt_machine_select, 863 .machine_register = sof_machine_register, 864 .machine_unregister = sof_machine_unregister, 865 .set_mach_params = byt_set_mach_params, 866 867 /* debug */ 868 .debug_map = byt_debugfs, 869 .debug_map_count = ARRAY_SIZE(byt_debugfs), 870 .dbg_dump = byt_dump, 871 872 /* stream callbacks */ 873 .pcm_open = intel_pcm_open, 874 .pcm_close = intel_pcm_close, 875 876 /* module loading */ 877 .load_module = snd_sof_parse_module_memcpy, 878 879 /*Firmware loading */ 880 .load_firmware = snd_sof_load_firmware_memcpy, 881 882 /* PM */ 883 .suspend = byt_suspend, 884 .resume = byt_resume, 885 886 /* DAI drivers */ 887 .drv = byt_dai, 888 .num_drv = 3, /* we have only 3 SSPs on byt*/ 889 890 /* ALSA HW info flags */ 891 .hw_info = SNDRV_PCM_INFO_MMAP | 892 SNDRV_PCM_INFO_MMAP_VALID | 893 SNDRV_PCM_INFO_INTERLEAVED | 894 SNDRV_PCM_INFO_PAUSE | 895 SNDRV_PCM_INFO_BATCH, 896 897 .arch_ops = &sof_xtensa_arch_ops, 898 }; 899 900 static const struct sof_intel_dsp_desc byt_chip_info = { 901 .cores_num = 1, 902 .host_managed_cores_mask = 1, 903 }; 904 905 /* cherrytrail and braswell ops */ 906 static const struct snd_sof_dsp_ops sof_cht_ops = { 907 /* device init */ 908 .probe = byt_acpi_probe, 909 .remove = byt_remove, 910 911 /* DSP core boot / reset */ 912 .run = byt_run, 913 .reset = byt_reset, 914 915 /* Register IO */ 916 .write = sof_io_write, 917 .read = sof_io_read, 918 .write64 = sof_io_write64, 919 .read64 = sof_io_read64, 920 921 /* Block IO */ 922 .block_read = sof_block_read, 923 .block_write = sof_block_write, 924 925 /* doorbell */ 926 .irq_handler = byt_irq_handler, 927 .irq_thread = byt_irq_thread, 928 929 /* ipc */ 930 .send_msg = byt_send_msg, 931 .fw_ready = sof_fw_ready, 932 .get_mailbox_offset = byt_get_mailbox_offset, 933 .get_window_offset = byt_get_window_offset, 934 935 .ipc_msg_data = intel_ipc_msg_data, 936 .ipc_pcm_params = intel_ipc_pcm_params, 937 938 /* machine driver */ 939 .machine_select = byt_machine_select, 940 .machine_register = sof_machine_register, 941 .machine_unregister = sof_machine_unregister, 942 .set_mach_params = byt_set_mach_params, 943 944 /* debug */ 945 .debug_map = cht_debugfs, 946 .debug_map_count = ARRAY_SIZE(cht_debugfs), 947 .dbg_dump = byt_dump, 948 949 /* stream callbacks */ 950 .pcm_open = intel_pcm_open, 951 .pcm_close = intel_pcm_close, 952 953 /* module loading */ 954 .load_module = snd_sof_parse_module_memcpy, 955 956 /*Firmware loading */ 957 .load_firmware = snd_sof_load_firmware_memcpy, 958 959 /* PM */ 960 .suspend = byt_suspend, 961 .resume = byt_resume, 962 963 /* DAI drivers */ 964 .drv = byt_dai, 965 /* all 6 SSPs may be available for cherrytrail */ 966 .num_drv = ARRAY_SIZE(byt_dai), 967 968 /* ALSA HW info flags */ 969 .hw_info = SNDRV_PCM_INFO_MMAP | 970 SNDRV_PCM_INFO_MMAP_VALID | 971 SNDRV_PCM_INFO_INTERLEAVED | 972 SNDRV_PCM_INFO_PAUSE | 973 SNDRV_PCM_INFO_BATCH, 974 975 .arch_ops = &sof_xtensa_arch_ops, 976 }; 977 978 static const struct sof_intel_dsp_desc cht_chip_info = { 979 .cores_num = 1, 980 .host_managed_cores_mask = 1, 981 }; 982 983 /* BYTCR uses different IRQ index */ 984 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { 985 .machines = snd_soc_acpi_intel_baytrail_machines, 986 .resindex_lpe_base = 0, 987 .resindex_pcicfg_base = 1, 988 .resindex_imr_base = 2, 989 .irqindex_host_ipc = 0, 990 .chip_info = &byt_chip_info, 991 .default_fw_path = "intel/sof", 992 .default_tplg_path = "intel/sof-tplg", 993 .default_fw_filename = "sof-byt.ri", 994 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 995 .ops = &sof_byt_ops, 996 }; 997 998 static const struct sof_dev_desc sof_acpi_baytrail_desc = { 999 .machines = snd_soc_acpi_intel_baytrail_machines, 1000 .resindex_lpe_base = 0, 1001 .resindex_pcicfg_base = 1, 1002 .resindex_imr_base = 2, 1003 .irqindex_host_ipc = 5, 1004 .chip_info = &byt_chip_info, 1005 .default_fw_path = "intel/sof", 1006 .default_tplg_path = "intel/sof-tplg", 1007 .default_fw_filename = "sof-byt.ri", 1008 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 1009 .ops = &sof_byt_ops, 1010 }; 1011 1012 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { 1013 .machines = snd_soc_acpi_intel_cherrytrail_machines, 1014 .resindex_lpe_base = 0, 1015 .resindex_pcicfg_base = 1, 1016 .resindex_imr_base = 2, 1017 .irqindex_host_ipc = 5, 1018 .chip_info = &cht_chip_info, 1019 .default_fw_path = "intel/sof", 1020 .default_tplg_path = "intel/sof-tplg", 1021 .default_fw_filename = "sof-cht.ri", 1022 .nocodec_tplg_filename = "sof-cht-nocodec.tplg", 1023 .ops = &sof_cht_ops, 1024 }; 1025 1026 static const struct acpi_device_id sof_baytrail_match[] = { 1027 { "80860F28", (unsigned long)&sof_acpi_baytrail_desc }, 1028 { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc }, 1029 { } 1030 }; 1031 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match); 1032 1033 static int sof_baytrail_probe(struct platform_device *pdev) 1034 { 1035 struct device *dev = &pdev->dev; 1036 const struct sof_dev_desc *desc; 1037 const struct acpi_device_id *id; 1038 int ret; 1039 1040 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1041 if (!id) 1042 return -ENODEV; 1043 1044 ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 1045 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1046 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 1047 return -ENODEV; 1048 } 1049 1050 desc = device_get_match_data(&pdev->dev); 1051 if (!desc) 1052 return -ENODEV; 1053 1054 if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) 1055 desc = &sof_acpi_baytrailcr_desc; 1056 1057 return sof_acpi_probe(pdev, desc); 1058 } 1059 1060 /* acpi_driver definition */ 1061 static struct platform_driver snd_sof_acpi_intel_byt_driver = { 1062 .probe = sof_baytrail_probe, 1063 .remove = sof_acpi_remove, 1064 .driver = { 1065 .name = "sof-audio-acpi-intel-byt", 1066 .pm = &sof_acpi_pm, 1067 .acpi_match_table = sof_baytrail_match, 1068 }, 1069 }; 1070 module_platform_driver(snd_sof_acpi_intel_byt_driver); 1071 1072 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 1073 1074 MODULE_LICENSE("Dual BSD/GPL"); 1075 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 1076 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1077 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 1078