1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include "../ops.h" 19 #include "shim.h" 20 #include "../sof-audio.h" 21 #include "../../intel/common/soc-intel-quirks.h" 22 23 /* DSP memories */ 24 #define IRAM_OFFSET 0x0C0000 25 #define IRAM_SIZE (80 * 1024) 26 #define DRAM_OFFSET 0x100000 27 #define DRAM_SIZE (160 * 1024) 28 #define SHIM_OFFSET 0x140000 29 #define SHIM_SIZE_BYT 0x100 30 #define SHIM_SIZE_CHT 0x118 31 #define MBOX_OFFSET 0x144000 32 #define MBOX_SIZE 0x1000 33 #define EXCEPT_OFFSET 0x800 34 #define EXCEPT_MAX_HDR_SIZE 0x400 35 36 /* DSP peripherals */ 37 #define DMAC0_OFFSET 0x098000 38 #define DMAC1_OFFSET 0x09c000 39 #define DMAC2_OFFSET 0x094000 40 #define DMAC_SIZE 0x420 41 #define SSP0_OFFSET 0x0a0000 42 #define SSP1_OFFSET 0x0a1000 43 #define SSP2_OFFSET 0x0a2000 44 #define SSP3_OFFSET 0x0a4000 45 #define SSP4_OFFSET 0x0a5000 46 #define SSP5_OFFSET 0x0a6000 47 #define SSP_SIZE 0x100 48 49 #define BYT_STACK_DUMP_SIZE 32 50 51 #define BYT_PCI_BAR_SIZE 0x200000 52 53 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 54 55 /* 56 * Debug 57 */ 58 59 #define MBOX_DUMP_SIZE 0x30 60 61 /* BARs */ 62 #define BYT_DSP_BAR 0 63 #define BYT_PCI_BAR 1 64 #define BYT_IMR_BAR 2 65 66 static const struct snd_sof_debugfs_map byt_debugfs[] = { 67 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 68 SOF_DEBUGFS_ACCESS_ALWAYS}, 69 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70 SOF_DEBUGFS_ACCESS_ALWAYS}, 71 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 78 SOF_DEBUGFS_ACCESS_D0_ONLY}, 79 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 80 SOF_DEBUGFS_ACCESS_D0_ONLY}, 81 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 82 SOF_DEBUGFS_ACCESS_ALWAYS}, 83 }; 84 85 static void byt_host_done(struct snd_sof_dev *sdev); 86 static void byt_dsp_done(struct snd_sof_dev *sdev); 87 static void byt_get_reply(struct snd_sof_dev *sdev); 88 89 /* 90 * Debug 91 */ 92 93 static void byt_get_registers(struct snd_sof_dev *sdev, 94 struct sof_ipc_dsp_oops_xtensa *xoops, 95 struct sof_ipc_panic_info *panic_info, 96 u32 *stack, size_t stack_words) 97 { 98 u32 offset = sdev->dsp_oops_offset; 99 100 /* first read regsisters */ 101 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 102 103 /* note: variable AR register array is not read */ 104 105 /* then get panic info */ 106 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 107 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 108 xoops->arch_hdr.totalsize); 109 return; 110 } 111 offset += xoops->arch_hdr.totalsize; 112 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 113 114 /* then get the stack */ 115 offset += sizeof(*panic_info); 116 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 117 } 118 119 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 120 { 121 struct sof_ipc_dsp_oops_xtensa xoops; 122 struct sof_ipc_panic_info panic_info; 123 u32 stack[BYT_STACK_DUMP_SIZE]; 124 u64 status, panic, imrd, imrx; 125 126 /* now try generic SOF status messages */ 127 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 128 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 129 byt_get_registers(sdev, &xoops, &panic_info, stack, 130 BYT_STACK_DUMP_SIZE); 131 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 132 BYT_STACK_DUMP_SIZE); 133 134 /* provide some context for firmware debug */ 135 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 136 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 137 dev_err(sdev->dev, 138 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 139 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 140 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 141 dev_err(sdev->dev, 142 "error: mask host: pending %s complete %s raw 0x%llx\n", 143 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 144 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 145 dev_err(sdev->dev, 146 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 147 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 148 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 149 dev_err(sdev->dev, 150 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 151 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 152 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 153 154 } 155 156 /* 157 * IPC Doorbell IRQ handler and thread. 158 */ 159 160 static irqreturn_t byt_irq_handler(int irq, void *context) 161 { 162 struct snd_sof_dev *sdev = context; 163 u64 ipcx, ipcd; 164 int ret = IRQ_NONE; 165 166 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 167 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 168 169 if (ipcx & SHIM_BYT_IPCX_DONE) { 170 171 /* reply message from DSP, Mask Done interrupt first */ 172 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 173 SHIM_IMRX, 174 SHIM_IMRX_DONE, 175 SHIM_IMRX_DONE); 176 ret = IRQ_WAKE_THREAD; 177 } 178 179 if (ipcd & SHIM_BYT_IPCD_BUSY) { 180 181 /* new message from DSP, Mask Busy interrupt first */ 182 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 183 SHIM_IMRX, 184 SHIM_IMRX_BUSY, 185 SHIM_IMRX_BUSY); 186 ret = IRQ_WAKE_THREAD; 187 } 188 189 return ret; 190 } 191 192 static irqreturn_t byt_irq_thread(int irq, void *context) 193 { 194 struct snd_sof_dev *sdev = context; 195 u64 ipcx, ipcd; 196 197 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 198 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 199 200 /* reply message from DSP */ 201 if (ipcx & SHIM_BYT_IPCX_DONE) { 202 203 spin_lock_irq(&sdev->ipc_lock); 204 205 /* 206 * handle immediate reply from DSP core. If the msg is 207 * found, set done bit in cmd_done which is called at the 208 * end of message processing function, else set it here 209 * because the done bit can't be set in cmd_done function 210 * which is triggered by msg 211 */ 212 byt_get_reply(sdev); 213 snd_sof_ipc_reply(sdev, ipcx); 214 215 byt_dsp_done(sdev); 216 217 spin_unlock_irq(&sdev->ipc_lock); 218 } 219 220 /* new message from DSP */ 221 if (ipcd & SHIM_BYT_IPCD_BUSY) { 222 223 /* Handle messages from DSP Core */ 224 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 225 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 226 MBOX_OFFSET); 227 } else { 228 snd_sof_ipc_msgs_rx(sdev); 229 } 230 231 byt_host_done(sdev); 232 } 233 234 return IRQ_HANDLED; 235 } 236 237 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 238 { 239 /* send the message */ 240 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 241 msg->msg_size); 242 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 243 244 return 0; 245 } 246 247 static void byt_get_reply(struct snd_sof_dev *sdev) 248 { 249 struct snd_sof_ipc_msg *msg = sdev->msg; 250 struct sof_ipc_reply reply; 251 int ret = 0; 252 253 /* 254 * Sometimes, there is unexpected reply ipc arriving. The reply 255 * ipc belongs to none of the ipcs sent from driver. 256 * In this case, the driver must ignore the ipc. 257 */ 258 if (!msg) { 259 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 260 return; 261 } 262 263 /* get reply */ 264 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 265 266 if (reply.error < 0) { 267 memcpy(msg->reply_data, &reply, sizeof(reply)); 268 ret = reply.error; 269 } else { 270 /* reply correct size ? */ 271 if (reply.hdr.size != msg->reply_size) { 272 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 273 msg->reply_size, reply.hdr.size); 274 ret = -EINVAL; 275 } 276 277 /* read the message */ 278 if (msg->reply_size > 0) 279 sof_mailbox_read(sdev, sdev->host_box.offset, 280 msg->reply_data, msg->reply_size); 281 } 282 283 msg->reply_error = ret; 284 } 285 286 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 287 { 288 return MBOX_OFFSET; 289 } 290 291 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 292 { 293 return MBOX_OFFSET; 294 } 295 296 static void byt_host_done(struct snd_sof_dev *sdev) 297 { 298 /* clear BUSY bit and set DONE bit - accept new messages */ 299 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 300 SHIM_BYT_IPCD_BUSY | 301 SHIM_BYT_IPCD_DONE, 302 SHIM_BYT_IPCD_DONE); 303 304 /* unmask busy interrupt */ 305 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 306 SHIM_IMRX_BUSY, 0); 307 } 308 309 static void byt_dsp_done(struct snd_sof_dev *sdev) 310 { 311 /* clear DONE bit - tell DSP we have completed */ 312 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 313 SHIM_BYT_IPCX_DONE, 0); 314 315 /* unmask Done interrupt */ 316 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 317 SHIM_IMRX_DONE, 0); 318 } 319 320 /* 321 * DSP control. 322 */ 323 324 static int byt_run(struct snd_sof_dev *sdev) 325 { 326 int tries = 10; 327 328 /* release stall and wait to unstall */ 329 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 330 SHIM_BYT_CSR_STALL, 0x0); 331 while (tries--) { 332 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 333 SHIM_BYT_CSR_PWAITMODE)) 334 break; 335 msleep(100); 336 } 337 if (tries < 0) { 338 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 339 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 340 return -ENODEV; 341 } 342 343 /* return init core mask */ 344 return 1; 345 } 346 347 static int byt_reset(struct snd_sof_dev *sdev) 348 { 349 /* put DSP into reset, set reset vector and stall */ 350 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 351 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 352 SHIM_BYT_CSR_STALL, 353 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 354 SHIM_BYT_CSR_STALL); 355 356 usleep_range(10, 15); 357 358 /* take DSP out of reset and keep stalled for FW loading */ 359 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 360 SHIM_BYT_CSR_RST, 0); 361 362 return 0; 363 } 364 365 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 366 const char *sof_tplg_filename, 367 const char *ssp_str) 368 { 369 const char *tplg_filename = NULL; 370 char *filename; 371 char *split_ext; 372 373 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 374 if (!filename) 375 return NULL; 376 377 /* this assumes a .tplg extension */ 378 split_ext = strsep(&filename, "."); 379 if (split_ext) { 380 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 381 "%s-%s.tplg", 382 split_ext, ssp_str); 383 if (!tplg_filename) 384 return NULL; 385 } 386 return tplg_filename; 387 } 388 389 static void byt_machine_select(struct snd_sof_dev *sdev) 390 { 391 struct snd_sof_pdata *sof_pdata = sdev->pdata; 392 const struct sof_dev_desc *desc = sof_pdata->desc; 393 struct snd_soc_acpi_mach *mach; 394 struct platform_device *pdev; 395 const char *tplg_filename; 396 397 mach = snd_soc_acpi_find_machine(desc->machines); 398 if (!mach) { 399 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 400 return; 401 } 402 403 pdev = to_platform_device(sdev->dev); 404 if (soc_intel_is_byt_cr(pdev)) { 405 dev_dbg(sdev->dev, 406 "BYT-CR detected, SSP0 used instead of SSP2\n"); 407 408 tplg_filename = fixup_tplg_name(sdev, 409 mach->sof_tplg_filename, 410 "ssp0"); 411 } else { 412 tplg_filename = mach->sof_tplg_filename; 413 } 414 415 if (!tplg_filename) { 416 dev_dbg(sdev->dev, 417 "error: no topology filename\n"); 418 return; 419 } 420 421 sof_pdata->tplg_filename = tplg_filename; 422 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 423 sof_pdata->machine = mach; 424 } 425 426 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 427 struct device *dev) 428 { 429 struct snd_soc_acpi_mach_params *mach_params; 430 431 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 432 mach_params->platform = dev_name(dev); 433 } 434 435 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 436 { 437 /* Disable Interrupt from both sides */ 438 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 439 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 440 441 /* Put DSP into reset, set reset vector */ 442 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 443 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 444 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 445 } 446 447 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 448 { 449 byt_reset_dsp_disable_int(sdev); 450 451 return 0; 452 } 453 454 static int byt_resume(struct snd_sof_dev *sdev) 455 { 456 /* Enable Interrupt from both sides */ 457 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 458 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 459 460 return 0; 461 } 462 463 static int byt_remove(struct snd_sof_dev *sdev) 464 { 465 byt_reset_dsp_disable_int(sdev); 466 467 return 0; 468 } 469 470 /* Baytrail DAIs */ 471 static struct snd_soc_dai_driver byt_dai[] = { 472 { 473 .name = "ssp0-port", 474 .playback = { 475 .channels_min = 1, 476 .channels_max = 8, 477 }, 478 .capture = { 479 .channels_min = 1, 480 .channels_max = 8, 481 }, 482 }, 483 { 484 .name = "ssp1-port", 485 .playback = { 486 .channels_min = 1, 487 .channels_max = 8, 488 }, 489 .capture = { 490 .channels_min = 1, 491 .channels_max = 8, 492 }, 493 }, 494 { 495 .name = "ssp2-port", 496 .playback = { 497 .channels_min = 1, 498 .channels_max = 8, 499 }, 500 .capture = { 501 .channels_min = 1, 502 .channels_max = 8, 503 } 504 }, 505 { 506 .name = "ssp3-port", 507 .playback = { 508 .channels_min = 1, 509 .channels_max = 8, 510 }, 511 .capture = { 512 .channels_min = 1, 513 .channels_max = 8, 514 }, 515 }, 516 { 517 .name = "ssp4-port", 518 .playback = { 519 .channels_min = 1, 520 .channels_max = 8, 521 }, 522 .capture = { 523 .channels_min = 1, 524 .channels_max = 8, 525 }, 526 }, 527 { 528 .name = "ssp5-port", 529 .playback = { 530 .channels_min = 1, 531 .channels_max = 8, 532 }, 533 .capture = { 534 .channels_min = 1, 535 .channels_max = 8, 536 }, 537 }, 538 }; 539 540 /* 541 * Probe and remove. 542 */ 543 544 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 545 546 static int tangier_pci_probe(struct snd_sof_dev *sdev) 547 { 548 struct snd_sof_pdata *pdata = sdev->pdata; 549 const struct sof_dev_desc *desc = pdata->desc; 550 struct pci_dev *pci = to_pci_dev(sdev->dev); 551 u32 base, size; 552 int ret; 553 554 /* DSP DMA can only access low 31 bits of host memory */ 555 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 556 if (ret < 0) { 557 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 558 return ret; 559 } 560 561 /* LPE base */ 562 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 563 size = BYT_PCI_BAR_SIZE; 564 565 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 566 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 567 if (!sdev->bar[BYT_DSP_BAR]) { 568 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 569 base, size); 570 return -ENODEV; 571 } 572 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 573 574 /* IMR base - optional */ 575 if (desc->resindex_imr_base == -1) 576 goto irq; 577 578 base = pci_resource_start(pci, desc->resindex_imr_base); 579 size = pci_resource_len(pci, desc->resindex_imr_base); 580 581 /* some BIOSes don't map IMR */ 582 if (base == 0x55aa55aa || base == 0x0) { 583 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 584 goto irq; 585 } 586 587 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 588 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 589 if (!sdev->bar[BYT_IMR_BAR]) { 590 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 591 base, size); 592 return -ENODEV; 593 } 594 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 595 596 irq: 597 /* register our IRQ */ 598 sdev->ipc_irq = pci->irq; 599 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 600 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 601 byt_irq_handler, byt_irq_thread, 602 0, "AudioDSP", sdev); 603 if (ret < 0) { 604 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 605 sdev->ipc_irq); 606 return ret; 607 } 608 609 /* enable Interrupt from both sides */ 610 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 611 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 612 613 /* set default mailbox offset for FW ready message */ 614 sdev->dsp_box.offset = MBOX_OFFSET; 615 616 return ret; 617 } 618 619 const struct snd_sof_dsp_ops sof_tng_ops = { 620 /* device init */ 621 .probe = tangier_pci_probe, 622 623 /* DSP core boot / reset */ 624 .run = byt_run, 625 .reset = byt_reset, 626 627 /* Register IO */ 628 .write = sof_io_write, 629 .read = sof_io_read, 630 .write64 = sof_io_write64, 631 .read64 = sof_io_read64, 632 633 /* Block IO */ 634 .block_read = sof_block_read, 635 .block_write = sof_block_write, 636 637 /* doorbell */ 638 .irq_handler = byt_irq_handler, 639 .irq_thread = byt_irq_thread, 640 641 /* ipc */ 642 .send_msg = byt_send_msg, 643 .fw_ready = sof_fw_ready, 644 .get_mailbox_offset = byt_get_mailbox_offset, 645 .get_window_offset = byt_get_window_offset, 646 647 .ipc_msg_data = intel_ipc_msg_data, 648 .ipc_pcm_params = intel_ipc_pcm_params, 649 650 /* machine driver */ 651 .machine_select = byt_machine_select, 652 .machine_register = sof_machine_register, 653 .machine_unregister = sof_machine_unregister, 654 .set_mach_params = byt_set_mach_params, 655 656 /* debug */ 657 .debug_map = byt_debugfs, 658 .debug_map_count = ARRAY_SIZE(byt_debugfs), 659 .dbg_dump = byt_dump, 660 661 /* stream callbacks */ 662 .pcm_open = intel_pcm_open, 663 .pcm_close = intel_pcm_close, 664 665 /* module loading */ 666 .load_module = snd_sof_parse_module_memcpy, 667 668 /*Firmware loading */ 669 .load_firmware = snd_sof_load_firmware_memcpy, 670 671 /* DAI drivers */ 672 .drv = byt_dai, 673 .num_drv = 3, /* we have only 3 SSPs on byt*/ 674 675 /* ALSA HW info flags */ 676 .hw_info = SNDRV_PCM_INFO_MMAP | 677 SNDRV_PCM_INFO_MMAP_VALID | 678 SNDRV_PCM_INFO_INTERLEAVED | 679 SNDRV_PCM_INFO_PAUSE | 680 SNDRV_PCM_INFO_BATCH, 681 682 .arch_ops = &sof_xtensa_arch_ops, 683 }; 684 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 685 686 const struct sof_intel_dsp_desc tng_chip_info = { 687 .cores_num = 1, 688 .cores_mask = 1, 689 }; 690 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 691 692 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 693 694 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 695 696 static const struct snd_sof_debugfs_map cht_debugfs[] = { 697 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 698 SOF_DEBUGFS_ACCESS_ALWAYS}, 699 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 700 SOF_DEBUGFS_ACCESS_ALWAYS}, 701 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 702 SOF_DEBUGFS_ACCESS_ALWAYS}, 703 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 704 SOF_DEBUGFS_ACCESS_ALWAYS}, 705 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 706 SOF_DEBUGFS_ACCESS_ALWAYS}, 707 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 708 SOF_DEBUGFS_ACCESS_ALWAYS}, 709 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 710 SOF_DEBUGFS_ACCESS_ALWAYS}, 711 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 712 SOF_DEBUGFS_ACCESS_ALWAYS}, 713 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 714 SOF_DEBUGFS_ACCESS_ALWAYS}, 715 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 716 SOF_DEBUGFS_ACCESS_D0_ONLY}, 717 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 718 SOF_DEBUGFS_ACCESS_D0_ONLY}, 719 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 720 SOF_DEBUGFS_ACCESS_ALWAYS}, 721 }; 722 723 static int byt_acpi_probe(struct snd_sof_dev *sdev) 724 { 725 struct snd_sof_pdata *pdata = sdev->pdata; 726 const struct sof_dev_desc *desc = pdata->desc; 727 struct platform_device *pdev = 728 container_of(sdev->dev, struct platform_device, dev); 729 struct resource *mmio; 730 u32 base, size; 731 int ret; 732 733 /* DSP DMA can only access low 31 bits of host memory */ 734 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 735 if (ret < 0) { 736 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 737 return ret; 738 } 739 740 /* LPE base */ 741 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 742 desc->resindex_lpe_base); 743 if (mmio) { 744 base = mmio->start; 745 size = resource_size(mmio); 746 } else { 747 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 748 desc->resindex_lpe_base); 749 return -EINVAL; 750 } 751 752 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 753 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 754 if (!sdev->bar[BYT_DSP_BAR]) { 755 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 756 base, size); 757 return -ENODEV; 758 } 759 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 760 761 /* TODO: add offsets */ 762 sdev->mmio_bar = BYT_DSP_BAR; 763 sdev->mailbox_bar = BYT_DSP_BAR; 764 765 /* IMR base - optional */ 766 if (desc->resindex_imr_base == -1) 767 goto irq; 768 769 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 770 desc->resindex_imr_base); 771 if (mmio) { 772 base = mmio->start; 773 size = resource_size(mmio); 774 } else { 775 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 776 desc->resindex_imr_base); 777 return -ENODEV; 778 } 779 780 /* some BIOSes don't map IMR */ 781 if (base == 0x55aa55aa || base == 0x0) { 782 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 783 goto irq; 784 } 785 786 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 787 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 788 if (!sdev->bar[BYT_IMR_BAR]) { 789 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 790 base, size); 791 return -ENODEV; 792 } 793 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 794 795 irq: 796 /* register our IRQ */ 797 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 798 if (sdev->ipc_irq < 0) 799 return sdev->ipc_irq; 800 801 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 802 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 803 byt_irq_handler, byt_irq_thread, 804 IRQF_SHARED, "AudioDSP", sdev); 805 if (ret < 0) { 806 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 807 sdev->ipc_irq); 808 return ret; 809 } 810 811 /* enable Interrupt from both sides */ 812 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 813 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 814 815 /* set default mailbox offset for FW ready message */ 816 sdev->dsp_box.offset = MBOX_OFFSET; 817 818 return ret; 819 } 820 821 /* baytrail ops */ 822 const struct snd_sof_dsp_ops sof_byt_ops = { 823 /* device init */ 824 .probe = byt_acpi_probe, 825 .remove = byt_remove, 826 827 /* DSP core boot / reset */ 828 .run = byt_run, 829 .reset = byt_reset, 830 831 /* Register IO */ 832 .write = sof_io_write, 833 .read = sof_io_read, 834 .write64 = sof_io_write64, 835 .read64 = sof_io_read64, 836 837 /* Block IO */ 838 .block_read = sof_block_read, 839 .block_write = sof_block_write, 840 841 /* doorbell */ 842 .irq_handler = byt_irq_handler, 843 .irq_thread = byt_irq_thread, 844 845 /* ipc */ 846 .send_msg = byt_send_msg, 847 .fw_ready = sof_fw_ready, 848 .get_mailbox_offset = byt_get_mailbox_offset, 849 .get_window_offset = byt_get_window_offset, 850 851 .ipc_msg_data = intel_ipc_msg_data, 852 .ipc_pcm_params = intel_ipc_pcm_params, 853 854 /* machine driver */ 855 .machine_select = byt_machine_select, 856 .machine_register = sof_machine_register, 857 .machine_unregister = sof_machine_unregister, 858 .set_mach_params = byt_set_mach_params, 859 860 /* debug */ 861 .debug_map = byt_debugfs, 862 .debug_map_count = ARRAY_SIZE(byt_debugfs), 863 .dbg_dump = byt_dump, 864 865 /* stream callbacks */ 866 .pcm_open = intel_pcm_open, 867 .pcm_close = intel_pcm_close, 868 869 /* module loading */ 870 .load_module = snd_sof_parse_module_memcpy, 871 872 /*Firmware loading */ 873 .load_firmware = snd_sof_load_firmware_memcpy, 874 875 /* PM */ 876 .suspend = byt_suspend, 877 .resume = byt_resume, 878 879 /* DAI drivers */ 880 .drv = byt_dai, 881 .num_drv = 3, /* we have only 3 SSPs on byt*/ 882 883 /* ALSA HW info flags */ 884 .hw_info = SNDRV_PCM_INFO_MMAP | 885 SNDRV_PCM_INFO_MMAP_VALID | 886 SNDRV_PCM_INFO_INTERLEAVED | 887 SNDRV_PCM_INFO_PAUSE | 888 SNDRV_PCM_INFO_BATCH, 889 890 .arch_ops = &sof_xtensa_arch_ops, 891 }; 892 EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 893 894 const struct sof_intel_dsp_desc byt_chip_info = { 895 .cores_num = 1, 896 .cores_mask = 1, 897 }; 898 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 899 900 /* cherrytrail and braswell ops */ 901 const struct snd_sof_dsp_ops sof_cht_ops = { 902 /* device init */ 903 .probe = byt_acpi_probe, 904 .remove = byt_remove, 905 906 /* DSP core boot / reset */ 907 .run = byt_run, 908 .reset = byt_reset, 909 910 /* Register IO */ 911 .write = sof_io_write, 912 .read = sof_io_read, 913 .write64 = sof_io_write64, 914 .read64 = sof_io_read64, 915 916 /* Block IO */ 917 .block_read = sof_block_read, 918 .block_write = sof_block_write, 919 920 /* doorbell */ 921 .irq_handler = byt_irq_handler, 922 .irq_thread = byt_irq_thread, 923 924 /* ipc */ 925 .send_msg = byt_send_msg, 926 .fw_ready = sof_fw_ready, 927 .get_mailbox_offset = byt_get_mailbox_offset, 928 .get_window_offset = byt_get_window_offset, 929 930 .ipc_msg_data = intel_ipc_msg_data, 931 .ipc_pcm_params = intel_ipc_pcm_params, 932 933 /* machine driver */ 934 .machine_select = byt_machine_select, 935 .machine_register = sof_machine_register, 936 .machine_unregister = sof_machine_unregister, 937 .set_mach_params = byt_set_mach_params, 938 939 /* debug */ 940 .debug_map = cht_debugfs, 941 .debug_map_count = ARRAY_SIZE(cht_debugfs), 942 .dbg_dump = byt_dump, 943 944 /* stream callbacks */ 945 .pcm_open = intel_pcm_open, 946 .pcm_close = intel_pcm_close, 947 948 /* module loading */ 949 .load_module = snd_sof_parse_module_memcpy, 950 951 /*Firmware loading */ 952 .load_firmware = snd_sof_load_firmware_memcpy, 953 954 /* PM */ 955 .suspend = byt_suspend, 956 .resume = byt_resume, 957 958 /* DAI drivers */ 959 .drv = byt_dai, 960 /* all 6 SSPs may be available for cherrytrail */ 961 .num_drv = ARRAY_SIZE(byt_dai), 962 963 /* ALSA HW info flags */ 964 .hw_info = SNDRV_PCM_INFO_MMAP | 965 SNDRV_PCM_INFO_MMAP_VALID | 966 SNDRV_PCM_INFO_INTERLEAVED | 967 SNDRV_PCM_INFO_PAUSE | 968 SNDRV_PCM_INFO_BATCH, 969 970 .arch_ops = &sof_xtensa_arch_ops, 971 }; 972 EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 973 974 const struct sof_intel_dsp_desc cht_chip_info = { 975 .cores_num = 1, 976 .cores_mask = 1, 977 }; 978 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 979 980 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 981 982 MODULE_LICENSE("Dual BSD/GPL"); 983 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 984 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 985