19e42c5caSLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 189e42c5caSLiam Girdwood #include "../ops.h" 199e42c5caSLiam Girdwood #include "shim.h" 20285880a2SDaniel Baluta #include "../sof-audio.h" 212aae447aSPierre-Louis Bossart #include "../../intel/common/soc-intel-quirks.h" 229e42c5caSLiam Girdwood 239e42c5caSLiam Girdwood /* DSP memories */ 249e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 259e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 269e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 279e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 289e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 29f84337c3SCurtis Malainey #define SHIM_SIZE_BYT 0x100 30f84337c3SCurtis Malainey #define SHIM_SIZE_CHT 0x118 319e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 329e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 339e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 34ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 359e42c5caSLiam Girdwood 369e42c5caSLiam Girdwood /* DSP peripherals */ 379e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 389e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 399e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 409e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 419e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 429e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 439e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 449e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 459e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 469e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 479e42c5caSLiam Girdwood #define SSP_SIZE 0x100 489e42c5caSLiam Girdwood 499e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE 32 509e42c5caSLiam Girdwood 519e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE 0x200000 529e42c5caSLiam Girdwood 539e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 549e42c5caSLiam Girdwood 559e42c5caSLiam Girdwood /* 569e42c5caSLiam Girdwood * Debug 579e42c5caSLiam Girdwood */ 589e42c5caSLiam Girdwood 599e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 609e42c5caSLiam Girdwood 619e42c5caSLiam Girdwood /* BARs */ 629e42c5caSLiam Girdwood #define BYT_DSP_BAR 0 639e42c5caSLiam Girdwood #define BYT_PCI_BAR 1 649e42c5caSLiam Girdwood #define BYT_IMR_BAR 2 659e42c5caSLiam Girdwood 669e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 679e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 689e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 699e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 709e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 719e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 739e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 759e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 779e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 799e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 809e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 81f84337c3SCurtis Malainey {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 829e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 839e42c5caSLiam Girdwood }; 849e42c5caSLiam Girdwood 859e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map cht_debugfs[] = { 869e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 879e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 889e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 899e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 909e42c5caSLiam Girdwood {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 919e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 929e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 939e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 949e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 959e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 969e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 979e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 989e42c5caSLiam Girdwood {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 999e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1009e42c5caSLiam Girdwood {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 1019e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1029e42c5caSLiam Girdwood {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 1039e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1049e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 1059e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 1069e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 1079e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 108f84337c3SCurtis Malainey {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 1099e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1109e42c5caSLiam Girdwood }; 1119e42c5caSLiam Girdwood 1129e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev); 1139e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev); 1149e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev); 1159e42c5caSLiam Girdwood 1169e42c5caSLiam Girdwood /* 1179e42c5caSLiam Girdwood * Debug 1189e42c5caSLiam Girdwood */ 1199e42c5caSLiam Girdwood 1209e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev, 1219e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 1229e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 1239e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 1249e42c5caSLiam Girdwood { 12514104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 12614104eb6SKai Vehmanen 1279e42c5caSLiam Girdwood /* first read regsisters */ 12814104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 12914104eb6SKai Vehmanen 13014104eb6SKai Vehmanen /* note: variable AR register array is not read */ 1319e42c5caSLiam Girdwood 1329e42c5caSLiam Girdwood /* then get panic info */ 133ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 134ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 135ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 136ff2be865SLiam Girdwood return; 137ff2be865SLiam Girdwood } 13814104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 13914104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 1409e42c5caSLiam Girdwood 1419e42c5caSLiam Girdwood /* then get the stack */ 14214104eb6SKai Vehmanen offset += sizeof(*panic_info); 14314104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 1449e42c5caSLiam Girdwood } 1459e42c5caSLiam Girdwood 1469e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 1479e42c5caSLiam Girdwood { 1489e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 1499e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 1509e42c5caSLiam Girdwood u32 stack[BYT_STACK_DUMP_SIZE]; 151b81eb73bSKeyon Jie u64 status, panic, imrd, imrx; 1529e42c5caSLiam Girdwood 1539e42c5caSLiam Girdwood /* now try generic SOF status messages */ 154b81eb73bSKeyon Jie status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 155b81eb73bSKeyon Jie panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1569e42c5caSLiam Girdwood byt_get_registers(sdev, &xoops, &panic_info, stack, 1579e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1589e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 1599e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1603a9e204dSLiam Girdwood 1613a9e204dSLiam Girdwood /* provide some context for firmware debug */ 162b81eb73bSKeyon Jie imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 163b81eb73bSKeyon Jie imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 1643a9e204dSLiam Girdwood dev_err(sdev->dev, 165b81eb73bSKeyon Jie "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 166f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 167f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 1683a9e204dSLiam Girdwood dev_err(sdev->dev, 169b81eb73bSKeyon Jie "error: mask host: pending %s complete %s raw 0x%llx\n", 170f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 171f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 1723a9e204dSLiam Girdwood dev_err(sdev->dev, 173b81eb73bSKeyon Jie "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 174f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_BUSY) ? "yes" : "no", 175f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 1763a9e204dSLiam Girdwood dev_err(sdev->dev, 177b81eb73bSKeyon Jie "error: mask DSP: pending %s complete %s raw 0x%llx\n", 178f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 179f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 1803a9e204dSLiam Girdwood 1819e42c5caSLiam Girdwood } 1829e42c5caSLiam Girdwood 1839e42c5caSLiam Girdwood /* 1849e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 1859e42c5caSLiam Girdwood */ 1869e42c5caSLiam Girdwood 1879e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context) 1889e42c5caSLiam Girdwood { 1899e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1909e42c5caSLiam Girdwood u64 isr; 1919e42c5caSLiam Girdwood int ret = IRQ_NONE; 1929e42c5caSLiam Girdwood 1939e42c5caSLiam Girdwood /* Interrupt arrived, check src */ 1949e42c5caSLiam Girdwood isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX); 1959e42c5caSLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 1969e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 1979e42c5caSLiam Girdwood 1989e42c5caSLiam Girdwood return ret; 1999e42c5caSLiam Girdwood } 2009e42c5caSLiam Girdwood 2019e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context) 2029e42c5caSLiam Girdwood { 2039e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 2049e42c5caSLiam Girdwood u64 ipcx, ipcd; 2059e42c5caSLiam Girdwood u64 imrx; 2069e42c5caSLiam Girdwood 2079e42c5caSLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 2089e42c5caSLiam Girdwood ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 2099e42c5caSLiam Girdwood 2109e42c5caSLiam Girdwood /* reply message from DSP */ 2119e42c5caSLiam Girdwood if (ipcx & SHIM_BYT_IPCX_DONE && 2129e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 2139e42c5caSLiam Girdwood /* Mask Done interrupt before first */ 2149e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 2159e42c5caSLiam Girdwood SHIM_IMRX, 2169e42c5caSLiam Girdwood SHIM_IMRX_DONE, 2179e42c5caSLiam Girdwood SHIM_IMRX_DONE); 2181183e9a6SGuennadi Liakhovetski 2191183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2201183e9a6SGuennadi Liakhovetski 2219e42c5caSLiam Girdwood /* 2229e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 2239e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 2249e42c5caSLiam Girdwood * end of message processing function, else set it here 2259e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 2269e42c5caSLiam Girdwood * which is triggered by msg 2279e42c5caSLiam Girdwood */ 2289e42c5caSLiam Girdwood byt_get_reply(sdev); 2299e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 2309e42c5caSLiam Girdwood 2319e42c5caSLiam Girdwood byt_dsp_done(sdev); 2321183e9a6SGuennadi Liakhovetski 2331183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 2349e42c5caSLiam Girdwood } 2359e42c5caSLiam Girdwood 2369e42c5caSLiam Girdwood /* new message from DSP */ 2379e42c5caSLiam Girdwood ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 2389e42c5caSLiam Girdwood if (ipcd & SHIM_BYT_IPCD_BUSY && 2399e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 2409e42c5caSLiam Girdwood /* Mask Busy interrupt before return */ 2419e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 2429e42c5caSLiam Girdwood SHIM_IMRX, 2439e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 2449e42c5caSLiam Girdwood SHIM_IMRX_BUSY); 2459e42c5caSLiam Girdwood 2469e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 2479e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 2489e42c5caSLiam Girdwood snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 2499e42c5caSLiam Girdwood MBOX_OFFSET); 2509e42c5caSLiam Girdwood } else { 2519e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 2529e42c5caSLiam Girdwood } 2539e42c5caSLiam Girdwood 2549e42c5caSLiam Girdwood byt_host_done(sdev); 2559e42c5caSLiam Girdwood } 2569e42c5caSLiam Girdwood 2579e42c5caSLiam Girdwood return IRQ_HANDLED; 2589e42c5caSLiam Girdwood } 2599e42c5caSLiam Girdwood 2609e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 2619e42c5caSLiam Girdwood { 2629e42c5caSLiam Girdwood /* send the message */ 2639e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 2649e42c5caSLiam Girdwood msg->msg_size); 2656fbbc18eSDaniel Baluta snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 2669e42c5caSLiam Girdwood 2679e42c5caSLiam Girdwood return 0; 2689e42c5caSLiam Girdwood } 2699e42c5caSLiam Girdwood 2709e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev) 2719e42c5caSLiam Girdwood { 2729e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 2739e42c5caSLiam Girdwood struct sof_ipc_reply reply; 2749e42c5caSLiam Girdwood int ret = 0; 2759e42c5caSLiam Girdwood 2769e42c5caSLiam Girdwood /* 2779e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 2789e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 2799e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 2809e42c5caSLiam Girdwood */ 2819e42c5caSLiam Girdwood if (!msg) { 2829e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 2839e42c5caSLiam Girdwood return; 2849e42c5caSLiam Girdwood } 2859e42c5caSLiam Girdwood 2869e42c5caSLiam Girdwood /* get reply */ 2879e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 2889e42c5caSLiam Girdwood 2899e42c5caSLiam Girdwood if (reply.error < 0) { 2909e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 2919e42c5caSLiam Girdwood ret = reply.error; 2929e42c5caSLiam Girdwood } else { 2939e42c5caSLiam Girdwood /* reply correct size ? */ 2949e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 2959e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 2969e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 2979e42c5caSLiam Girdwood ret = -EINVAL; 2989e42c5caSLiam Girdwood } 2999e42c5caSLiam Girdwood 3009e42c5caSLiam Girdwood /* read the message */ 3019e42c5caSLiam Girdwood if (msg->reply_size > 0) 3029e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 3039e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 3049e42c5caSLiam Girdwood } 3059e42c5caSLiam Girdwood 3069e42c5caSLiam Girdwood msg->reply_error = ret; 3079e42c5caSLiam Girdwood } 3089e42c5caSLiam Girdwood 30983ee7ab1SDaniel Baluta static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 31083ee7ab1SDaniel Baluta { 31183ee7ab1SDaniel Baluta return MBOX_OFFSET; 31283ee7ab1SDaniel Baluta } 31383ee7ab1SDaniel Baluta 31483ee7ab1SDaniel Baluta static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 31583ee7ab1SDaniel Baluta { 31683ee7ab1SDaniel Baluta return MBOX_OFFSET; 31783ee7ab1SDaniel Baluta } 31883ee7ab1SDaniel Baluta 3199e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev) 3209e42c5caSLiam Girdwood { 3219e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 3229e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 3239e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 3249e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 3259e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 3269e42c5caSLiam Girdwood 3279e42c5caSLiam Girdwood /* unmask busy interrupt */ 3289e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3299e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 3309e42c5caSLiam Girdwood } 3319e42c5caSLiam Girdwood 3329e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev) 3339e42c5caSLiam Girdwood { 3349e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 3359e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 3369e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 3379e42c5caSLiam Girdwood 3389e42c5caSLiam Girdwood /* unmask Done interrupt */ 3399e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3409e42c5caSLiam Girdwood SHIM_IMRX_DONE, 0); 3419e42c5caSLiam Girdwood } 3429e42c5caSLiam Girdwood 3439e42c5caSLiam Girdwood /* 3449e42c5caSLiam Girdwood * DSP control. 3459e42c5caSLiam Girdwood */ 3469e42c5caSLiam Girdwood 3479e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev) 3489e42c5caSLiam Girdwood { 3499e42c5caSLiam Girdwood int tries = 10; 3509e42c5caSLiam Girdwood 3519e42c5caSLiam Girdwood /* release stall and wait to unstall */ 3529e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3539e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 3549e42c5caSLiam Girdwood while (tries--) { 3559e42c5caSLiam Girdwood if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 3569e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 3579e42c5caSLiam Girdwood break; 3589e42c5caSLiam Girdwood msleep(100); 3599e42c5caSLiam Girdwood } 3609e42c5caSLiam Girdwood if (tries < 0) { 3619e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 3629e42c5caSLiam Girdwood byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 3639e42c5caSLiam Girdwood return -ENODEV; 3649e42c5caSLiam Girdwood } 3659e42c5caSLiam Girdwood 3669e42c5caSLiam Girdwood /* return init core mask */ 3679e42c5caSLiam Girdwood return 1; 3689e42c5caSLiam Girdwood } 3699e42c5caSLiam Girdwood 3709e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev) 3719e42c5caSLiam Girdwood { 3729e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 3739e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3749e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3759e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 3769e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3779e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 3789e42c5caSLiam Girdwood 3799e42c5caSLiam Girdwood usleep_range(10, 15); 3809e42c5caSLiam Girdwood 3819e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 3829e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3839e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 3849e42c5caSLiam Girdwood 3859e42c5caSLiam Girdwood return 0; 3869e42c5caSLiam Girdwood } 3879e42c5caSLiam Girdwood 3882aae447aSPierre-Louis Bossart static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 3892aae447aSPierre-Louis Bossart const char *sof_tplg_filename, 3902aae447aSPierre-Louis Bossart const char *ssp_str) 3912aae447aSPierre-Louis Bossart { 3922aae447aSPierre-Louis Bossart const char *tplg_filename = NULL; 3932aae447aSPierre-Louis Bossart char *filename; 3942aae447aSPierre-Louis Bossart char *split_ext; 3952aae447aSPierre-Louis Bossart 3962aae447aSPierre-Louis Bossart filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 3972aae447aSPierre-Louis Bossart if (!filename) 3982aae447aSPierre-Louis Bossart return NULL; 3992aae447aSPierre-Louis Bossart 4002aae447aSPierre-Louis Bossart /* this assumes a .tplg extension */ 4012aae447aSPierre-Louis Bossart split_ext = strsep(&filename, "."); 4022aae447aSPierre-Louis Bossart if (split_ext) { 4032aae447aSPierre-Louis Bossart tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 4042aae447aSPierre-Louis Bossart "%s-%s.tplg", 4052aae447aSPierre-Louis Bossart split_ext, ssp_str); 4062aae447aSPierre-Louis Bossart if (!tplg_filename) 4072aae447aSPierre-Louis Bossart return NULL; 4082aae447aSPierre-Louis Bossart } 4092aae447aSPierre-Louis Bossart return tplg_filename; 4102aae447aSPierre-Louis Bossart } 4112aae447aSPierre-Louis Bossart 412285880a2SDaniel Baluta static void byt_machine_select(struct snd_sof_dev *sdev) 413285880a2SDaniel Baluta { 414285880a2SDaniel Baluta struct snd_sof_pdata *sof_pdata = sdev->pdata; 415285880a2SDaniel Baluta const struct sof_dev_desc *desc = sof_pdata->desc; 416285880a2SDaniel Baluta struct snd_soc_acpi_mach *mach; 4172aae447aSPierre-Louis Bossart struct platform_device *pdev; 4182aae447aSPierre-Louis Bossart const char *tplg_filename; 419285880a2SDaniel Baluta 420285880a2SDaniel Baluta mach = snd_soc_acpi_find_machine(desc->machines); 421285880a2SDaniel Baluta if (!mach) { 422285880a2SDaniel Baluta dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 423285880a2SDaniel Baluta return; 424285880a2SDaniel Baluta } 425285880a2SDaniel Baluta 4262aae447aSPierre-Louis Bossart pdev = to_platform_device(sdev->dev); 4272aae447aSPierre-Louis Bossart if (soc_intel_is_byt_cr(pdev)) { 4282aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4292aae447aSPierre-Louis Bossart "BYT-CR detected, SSP0 used instead of SSP2\n"); 4302aae447aSPierre-Louis Bossart 4312aae447aSPierre-Louis Bossart tplg_filename = fixup_tplg_name(sdev, 4322aae447aSPierre-Louis Bossart mach->sof_tplg_filename, 4332aae447aSPierre-Louis Bossart "ssp0"); 4342aae447aSPierre-Louis Bossart } else { 4352aae447aSPierre-Louis Bossart tplg_filename = mach->sof_tplg_filename; 4362aae447aSPierre-Louis Bossart } 4372aae447aSPierre-Louis Bossart 4382aae447aSPierre-Louis Bossart if (!tplg_filename) { 4392aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4402aae447aSPierre-Louis Bossart "error: no topology filename\n"); 4412aae447aSPierre-Louis Bossart return; 4422aae447aSPierre-Louis Bossart } 4432aae447aSPierre-Louis Bossart 4442aae447aSPierre-Louis Bossart sof_pdata->tplg_filename = tplg_filename; 445285880a2SDaniel Baluta mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 446285880a2SDaniel Baluta sof_pdata->machine = mach; 447285880a2SDaniel Baluta } 448285880a2SDaniel Baluta 449285880a2SDaniel Baluta static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 450285880a2SDaniel Baluta struct device *dev) 451285880a2SDaniel Baluta { 452285880a2SDaniel Baluta struct snd_soc_acpi_mach_params *mach_params; 453285880a2SDaniel Baluta 454285880a2SDaniel Baluta mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 455285880a2SDaniel Baluta mach_params->platform = dev_name(dev); 456285880a2SDaniel Baluta } 457285880a2SDaniel Baluta 4589e42c5caSLiam Girdwood /* Baytrail DAIs */ 4599e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = { 4609e42c5caSLiam Girdwood { 4619e42c5caSLiam Girdwood .name = "ssp0-port", 4628c05246cSPierre-Louis Bossart .playback = { 4638c05246cSPierre-Louis Bossart .channels_min = 1, 4648c05246cSPierre-Louis Bossart .channels_max = 8, 4658c05246cSPierre-Louis Bossart }, 4668c05246cSPierre-Louis Bossart .capture = { 4678c05246cSPierre-Louis Bossart .channels_min = 1, 4688c05246cSPierre-Louis Bossart .channels_max = 8, 4698c05246cSPierre-Louis Bossart }, 4709e42c5caSLiam Girdwood }, 4719e42c5caSLiam Girdwood { 4729e42c5caSLiam Girdwood .name = "ssp1-port", 4738c05246cSPierre-Louis Bossart .playback = { 4748c05246cSPierre-Louis Bossart .channels_min = 1, 4758c05246cSPierre-Louis Bossart .channels_max = 8, 4768c05246cSPierre-Louis Bossart }, 4778c05246cSPierre-Louis Bossart .capture = { 4788c05246cSPierre-Louis Bossart .channels_min = 1, 4798c05246cSPierre-Louis Bossart .channels_max = 8, 4808c05246cSPierre-Louis Bossart }, 4819e42c5caSLiam Girdwood }, 4829e42c5caSLiam Girdwood { 4839e42c5caSLiam Girdwood .name = "ssp2-port", 4848c05246cSPierre-Louis Bossart .playback = { 4858c05246cSPierre-Louis Bossart .channels_min = 1, 4868c05246cSPierre-Louis Bossart .channels_max = 8, 4878c05246cSPierre-Louis Bossart }, 4888c05246cSPierre-Louis Bossart .capture = { 4898c05246cSPierre-Louis Bossart .channels_min = 1, 4908c05246cSPierre-Louis Bossart .channels_max = 8, 4918c05246cSPierre-Louis Bossart } 4929e42c5caSLiam Girdwood }, 4939e42c5caSLiam Girdwood { 4949e42c5caSLiam Girdwood .name = "ssp3-port", 4958c05246cSPierre-Louis Bossart .playback = { 4968c05246cSPierre-Louis Bossart .channels_min = 1, 4978c05246cSPierre-Louis Bossart .channels_max = 8, 4988c05246cSPierre-Louis Bossart }, 4998c05246cSPierre-Louis Bossart .capture = { 5008c05246cSPierre-Louis Bossart .channels_min = 1, 5018c05246cSPierre-Louis Bossart .channels_max = 8, 5028c05246cSPierre-Louis Bossart }, 5039e42c5caSLiam Girdwood }, 5049e42c5caSLiam Girdwood { 5059e42c5caSLiam Girdwood .name = "ssp4-port", 5068c05246cSPierre-Louis Bossart .playback = { 5078c05246cSPierre-Louis Bossart .channels_min = 1, 5088c05246cSPierre-Louis Bossart .channels_max = 8, 5098c05246cSPierre-Louis Bossart }, 5108c05246cSPierre-Louis Bossart .capture = { 5118c05246cSPierre-Louis Bossart .channels_min = 1, 5128c05246cSPierre-Louis Bossart .channels_max = 8, 5138c05246cSPierre-Louis Bossart }, 5149e42c5caSLiam Girdwood }, 5159e42c5caSLiam Girdwood { 5169e42c5caSLiam Girdwood .name = "ssp5-port", 5178c05246cSPierre-Louis Bossart .playback = { 5188c05246cSPierre-Louis Bossart .channels_min = 1, 5198c05246cSPierre-Louis Bossart .channels_max = 8, 5208c05246cSPierre-Louis Bossart }, 5218c05246cSPierre-Louis Bossart .capture = { 5228c05246cSPierre-Louis Bossart .channels_min = 1, 5238c05246cSPierre-Louis Bossart .channels_max = 8, 5248c05246cSPierre-Louis Bossart }, 5259e42c5caSLiam Girdwood }, 5269e42c5caSLiam Girdwood }; 5279e42c5caSLiam Girdwood 5289e42c5caSLiam Girdwood /* 5299e42c5caSLiam Girdwood * Probe and remove. 5309e42c5caSLiam Girdwood */ 5319e42c5caSLiam Girdwood 5329e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 5339e42c5caSLiam Girdwood 5349e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 5359e42c5caSLiam Girdwood { 5369e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5379e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5389e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 5399e42c5caSLiam Girdwood u32 base, size; 5409e42c5caSLiam Girdwood int ret; 5419e42c5caSLiam Girdwood 5429e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5439e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 5449e42c5caSLiam Girdwood if (ret < 0) { 5459e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5469e42c5caSLiam Girdwood return ret; 5479e42c5caSLiam Girdwood } 5489e42c5caSLiam Girdwood 5499e42c5caSLiam Girdwood /* LPE base */ 5509e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 5519e42c5caSLiam Girdwood size = BYT_PCI_BAR_SIZE; 5529e42c5caSLiam Girdwood 5539e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 5549e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 5559e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 5569e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5579e42c5caSLiam Girdwood base, size); 5589e42c5caSLiam Girdwood return -ENODEV; 5599e42c5caSLiam Girdwood } 5609e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 5619e42c5caSLiam Girdwood 5629e42c5caSLiam Girdwood /* IMR base - optional */ 5639e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5649e42c5caSLiam Girdwood goto irq; 5659e42c5caSLiam Girdwood 5669e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 5679e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 5689e42c5caSLiam Girdwood 5699e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 5709e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 5719e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 5729e42c5caSLiam Girdwood goto irq; 5739e42c5caSLiam Girdwood } 5749e42c5caSLiam Girdwood 5759e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 5769e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 5779e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 5789e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 5799e42c5caSLiam Girdwood base, size); 5809e42c5caSLiam Girdwood return -ENODEV; 5819e42c5caSLiam Girdwood } 5829e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 5839e42c5caSLiam Girdwood 5849e42c5caSLiam Girdwood irq: 5859e42c5caSLiam Girdwood /* register our IRQ */ 5869e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 5879e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 5889e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 5899e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 5909e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 5919e42c5caSLiam Girdwood if (ret < 0) { 5929e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 5939e42c5caSLiam Girdwood sdev->ipc_irq); 5949e42c5caSLiam Girdwood return ret; 5959e42c5caSLiam Girdwood } 5969e42c5caSLiam Girdwood 5979e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 5989e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 5999e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 6009e42c5caSLiam Girdwood 6019e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 6029e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 6039e42c5caSLiam Girdwood 6049e42c5caSLiam Girdwood return ret; 6059e42c5caSLiam Girdwood } 6069e42c5caSLiam Girdwood 6079e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 6089e42c5caSLiam Girdwood /* device init */ 6099e42c5caSLiam Girdwood .probe = tangier_pci_probe, 6109e42c5caSLiam Girdwood 6119e42c5caSLiam Girdwood /* DSP core boot / reset */ 6129e42c5caSLiam Girdwood .run = byt_run, 6139e42c5caSLiam Girdwood .reset = byt_reset, 6149e42c5caSLiam Girdwood 6159e42c5caSLiam Girdwood /* Register IO */ 6169e42c5caSLiam Girdwood .write = sof_io_write, 6179e42c5caSLiam Girdwood .read = sof_io_read, 6189e42c5caSLiam Girdwood .write64 = sof_io_write64, 6199e42c5caSLiam Girdwood .read64 = sof_io_read64, 6209e42c5caSLiam Girdwood 6219e42c5caSLiam Girdwood /* Block IO */ 6229e42c5caSLiam Girdwood .block_read = sof_block_read, 6239e42c5caSLiam Girdwood .block_write = sof_block_write, 6249e42c5caSLiam Girdwood 6259e42c5caSLiam Girdwood /* doorbell */ 6269e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 6279e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 6289e42c5caSLiam Girdwood 6299e42c5caSLiam Girdwood /* ipc */ 6309e42c5caSLiam Girdwood .send_msg = byt_send_msg, 63183ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 63283ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 63383ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 6349e42c5caSLiam Girdwood 6359e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6369e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6379e42c5caSLiam Girdwood 638285880a2SDaniel Baluta /* machine driver */ 639285880a2SDaniel Baluta .machine_select = byt_machine_select, 640285880a2SDaniel Baluta .machine_register = sof_machine_register, 641285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 642285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 643285880a2SDaniel Baluta 6449e42c5caSLiam Girdwood /* debug */ 6459e42c5caSLiam Girdwood .debug_map = byt_debugfs, 6469e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 6479e42c5caSLiam Girdwood .dbg_dump = byt_dump, 6489e42c5caSLiam Girdwood 6499e42c5caSLiam Girdwood /* stream callbacks */ 6509e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6519e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6529e42c5caSLiam Girdwood 6539e42c5caSLiam Girdwood /* module loading */ 6549e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6559e42c5caSLiam Girdwood 6569e42c5caSLiam Girdwood /*Firmware loading */ 6579e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6589e42c5caSLiam Girdwood 6599e42c5caSLiam Girdwood /* DAI drivers */ 6609e42c5caSLiam Girdwood .drv = byt_dai, 6619e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 66227e322faSPierre-Louis Bossart 66327e322faSPierre-Louis Bossart /* ALSA HW info flags */ 66427e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 66527e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 66627e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 66727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 6684c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 6690f501c7cSPierre-Louis Bossart 6700f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 6719e42c5caSLiam Girdwood }; 672e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 6739e42c5caSLiam Girdwood 6749e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 6759e42c5caSLiam Girdwood .cores_num = 1, 6769e42c5caSLiam Girdwood .cores_mask = 1, 6779e42c5caSLiam Girdwood }; 678e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 6799e42c5caSLiam Girdwood 6809e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 6819e42c5caSLiam Girdwood 6829e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 6839e42c5caSLiam Girdwood 6849e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 6859e42c5caSLiam Girdwood { 6869e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 6879e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 6889e42c5caSLiam Girdwood struct platform_device *pdev = 6899e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 6909e42c5caSLiam Girdwood struct resource *mmio; 6919e42c5caSLiam Girdwood u32 base, size; 6929e42c5caSLiam Girdwood int ret; 6939e42c5caSLiam Girdwood 6949e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 6959e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 6969e42c5caSLiam Girdwood if (ret < 0) { 6979e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 6989e42c5caSLiam Girdwood return ret; 6999e42c5caSLiam Girdwood } 7009e42c5caSLiam Girdwood 7019e42c5caSLiam Girdwood /* LPE base */ 7029e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7039e42c5caSLiam Girdwood desc->resindex_lpe_base); 7049e42c5caSLiam Girdwood if (mmio) { 7059e42c5caSLiam Girdwood base = mmio->start; 7069e42c5caSLiam Girdwood size = resource_size(mmio); 7079e42c5caSLiam Girdwood } else { 7089e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 7099e42c5caSLiam Girdwood desc->resindex_lpe_base); 7109e42c5caSLiam Girdwood return -EINVAL; 7119e42c5caSLiam Girdwood } 7129e42c5caSLiam Girdwood 7139e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 7149e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 7159e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 7169e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 7179e42c5caSLiam Girdwood base, size); 7189e42c5caSLiam Girdwood return -ENODEV; 7199e42c5caSLiam Girdwood } 7209e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 7219e42c5caSLiam Girdwood 7229e42c5caSLiam Girdwood /* TODO: add offsets */ 7239e42c5caSLiam Girdwood sdev->mmio_bar = BYT_DSP_BAR; 7249e42c5caSLiam Girdwood sdev->mailbox_bar = BYT_DSP_BAR; 7259e42c5caSLiam Girdwood 7269e42c5caSLiam Girdwood /* IMR base - optional */ 7279e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 7289e42c5caSLiam Girdwood goto irq; 7299e42c5caSLiam Girdwood 7309e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7319e42c5caSLiam Girdwood desc->resindex_imr_base); 7329e42c5caSLiam Girdwood if (mmio) { 7339e42c5caSLiam Girdwood base = mmio->start; 7349e42c5caSLiam Girdwood size = resource_size(mmio); 7359e42c5caSLiam Girdwood } else { 7369e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 7379e42c5caSLiam Girdwood desc->resindex_imr_base); 7389e42c5caSLiam Girdwood return -ENODEV; 7399e42c5caSLiam Girdwood } 7409e42c5caSLiam Girdwood 7419e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 7429e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 7439e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 7449e42c5caSLiam Girdwood goto irq; 7459e42c5caSLiam Girdwood } 7469e42c5caSLiam Girdwood 7479e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 7489e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 7499e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 7509e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 7519e42c5caSLiam Girdwood base, size); 7529e42c5caSLiam Girdwood return -ENODEV; 7539e42c5caSLiam Girdwood } 7549e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 7559e42c5caSLiam Girdwood 7569e42c5caSLiam Girdwood irq: 7579e42c5caSLiam Girdwood /* register our IRQ */ 7589e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 759cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 7609e42c5caSLiam Girdwood return sdev->ipc_irq; 7619e42c5caSLiam Girdwood 7629e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 7639e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 7649e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 7659e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 7669e42c5caSLiam Girdwood if (ret < 0) { 7679e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 7689e42c5caSLiam Girdwood sdev->ipc_irq); 7699e42c5caSLiam Girdwood return ret; 7709e42c5caSLiam Girdwood } 7719e42c5caSLiam Girdwood 7729e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 7739e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 7749e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 7759e42c5caSLiam Girdwood 7769e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 7779e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 7789e42c5caSLiam Girdwood 7799e42c5caSLiam Girdwood return ret; 7809e42c5caSLiam Girdwood } 7819e42c5caSLiam Girdwood 7829e42c5caSLiam Girdwood /* baytrail ops */ 7839e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_byt_ops = { 7849e42c5caSLiam Girdwood /* device init */ 7859e42c5caSLiam Girdwood .probe = byt_acpi_probe, 7869e42c5caSLiam Girdwood 7879e42c5caSLiam Girdwood /* DSP core boot / reset */ 7889e42c5caSLiam Girdwood .run = byt_run, 7899e42c5caSLiam Girdwood .reset = byt_reset, 7909e42c5caSLiam Girdwood 7919e42c5caSLiam Girdwood /* Register IO */ 7929e42c5caSLiam Girdwood .write = sof_io_write, 7939e42c5caSLiam Girdwood .read = sof_io_read, 7949e42c5caSLiam Girdwood .write64 = sof_io_write64, 7959e42c5caSLiam Girdwood .read64 = sof_io_read64, 7969e42c5caSLiam Girdwood 7979e42c5caSLiam Girdwood /* Block IO */ 7989e42c5caSLiam Girdwood .block_read = sof_block_read, 7999e42c5caSLiam Girdwood .block_write = sof_block_write, 8009e42c5caSLiam Girdwood 8019e42c5caSLiam Girdwood /* doorbell */ 8029e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 8039e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 8049e42c5caSLiam Girdwood 8059e42c5caSLiam Girdwood /* ipc */ 8069e42c5caSLiam Girdwood .send_msg = byt_send_msg, 80783ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 80883ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 80983ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 8109e42c5caSLiam Girdwood 8119e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8129e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8139e42c5caSLiam Girdwood 814285880a2SDaniel Baluta /* machine driver */ 815285880a2SDaniel Baluta .machine_select = byt_machine_select, 816285880a2SDaniel Baluta .machine_register = sof_machine_register, 817285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 818285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 819285880a2SDaniel Baluta 8209e42c5caSLiam Girdwood /* debug */ 8219e42c5caSLiam Girdwood .debug_map = byt_debugfs, 8229e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 8239e42c5caSLiam Girdwood .dbg_dump = byt_dump, 8249e42c5caSLiam Girdwood 8259e42c5caSLiam Girdwood /* stream callbacks */ 8269e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 8279e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 8289e42c5caSLiam Girdwood 8299e42c5caSLiam Girdwood /* module loading */ 8309e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 8319e42c5caSLiam Girdwood 8329e42c5caSLiam Girdwood /*Firmware loading */ 8339e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 8349e42c5caSLiam Girdwood 8359e42c5caSLiam Girdwood /* DAI drivers */ 8369e42c5caSLiam Girdwood .drv = byt_dai, 8379e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 83827e322faSPierre-Louis Bossart 83927e322faSPierre-Louis Bossart /* ALSA HW info flags */ 84027e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 84127e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 84227e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 84327e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 8444c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 8450f501c7cSPierre-Louis Bossart 8460f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 8479e42c5caSLiam Girdwood }; 848e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 8499e42c5caSLiam Girdwood 8509e42c5caSLiam Girdwood const struct sof_intel_dsp_desc byt_chip_info = { 8519e42c5caSLiam Girdwood .cores_num = 1, 8529e42c5caSLiam Girdwood .cores_mask = 1, 8539e42c5caSLiam Girdwood }; 854e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 8559e42c5caSLiam Girdwood 8569e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 8579e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_cht_ops = { 8589e42c5caSLiam Girdwood /* device init */ 8599e42c5caSLiam Girdwood .probe = byt_acpi_probe, 8609e42c5caSLiam Girdwood 8619e42c5caSLiam Girdwood /* DSP core boot / reset */ 8629e42c5caSLiam Girdwood .run = byt_run, 8639e42c5caSLiam Girdwood .reset = byt_reset, 8649e42c5caSLiam Girdwood 8659e42c5caSLiam Girdwood /* Register IO */ 8669e42c5caSLiam Girdwood .write = sof_io_write, 8679e42c5caSLiam Girdwood .read = sof_io_read, 8689e42c5caSLiam Girdwood .write64 = sof_io_write64, 8699e42c5caSLiam Girdwood .read64 = sof_io_read64, 8709e42c5caSLiam Girdwood 8719e42c5caSLiam Girdwood /* Block IO */ 8729e42c5caSLiam Girdwood .block_read = sof_block_read, 8739e42c5caSLiam Girdwood .block_write = sof_block_write, 8749e42c5caSLiam Girdwood 8759e42c5caSLiam Girdwood /* doorbell */ 8769e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 8779e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 8789e42c5caSLiam Girdwood 8799e42c5caSLiam Girdwood /* ipc */ 8809e42c5caSLiam Girdwood .send_msg = byt_send_msg, 88183ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 88283ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 88383ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 8849e42c5caSLiam Girdwood 8859e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8869e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8879e42c5caSLiam Girdwood 888285880a2SDaniel Baluta /* machine driver */ 889285880a2SDaniel Baluta .machine_select = byt_machine_select, 890285880a2SDaniel Baluta .machine_register = sof_machine_register, 891285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 892285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 893285880a2SDaniel Baluta 8949e42c5caSLiam Girdwood /* debug */ 8959e42c5caSLiam Girdwood .debug_map = cht_debugfs, 8969e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 8979e42c5caSLiam Girdwood .dbg_dump = byt_dump, 8989e42c5caSLiam Girdwood 8999e42c5caSLiam Girdwood /* stream callbacks */ 9009e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 9019e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 9029e42c5caSLiam Girdwood 9039e42c5caSLiam Girdwood /* module loading */ 9049e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 9059e42c5caSLiam Girdwood 9069e42c5caSLiam Girdwood /*Firmware loading */ 9079e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 9089e42c5caSLiam Girdwood 9099e42c5caSLiam Girdwood /* DAI drivers */ 9109e42c5caSLiam Girdwood .drv = byt_dai, 9119e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 9129e42c5caSLiam Girdwood .num_drv = ARRAY_SIZE(byt_dai), 91327e322faSPierre-Louis Bossart 91427e322faSPierre-Louis Bossart /* ALSA HW info flags */ 91527e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 91627e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 91727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 91827e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 9194c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 9200f501c7cSPierre-Louis Bossart 9210f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 9229e42c5caSLiam Girdwood }; 923e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 9249e42c5caSLiam Girdwood 9259e42c5caSLiam Girdwood const struct sof_intel_dsp_desc cht_chip_info = { 9269e42c5caSLiam Girdwood .cores_num = 1, 9279e42c5caSLiam Girdwood .cores_mask = 1, 9289e42c5caSLiam Girdwood }; 929e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 9309e42c5caSLiam Girdwood 9319e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 9329e42c5caSLiam Girdwood 9339e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 934f4483a0fSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 935068ac0dbSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 936