1e149ca29SPierre-Louis Bossart // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 18*8a49cd11SArnd Bergmann #include <sound/soc-acpi.h> 19*8a49cd11SArnd Bergmann #include <sound/soc-acpi-intel-match.h> 20*8a49cd11SArnd Bergmann #include <sound/intel-dsp-config.h> 219e42c5caSLiam Girdwood #include "../ops.h" 229e42c5caSLiam Girdwood #include "shim.h" 23*8a49cd11SArnd Bergmann #include "../sof-acpi-dev.h" 24285880a2SDaniel Baluta #include "../sof-audio.h" 252aae447aSPierre-Louis Bossart #include "../../intel/common/soc-intel-quirks.h" 269e42c5caSLiam Girdwood 279e42c5caSLiam Girdwood /* DSP memories */ 289e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 299e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 309e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 319e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 329e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 33f84337c3SCurtis Malainey #define SHIM_SIZE_BYT 0x100 34f84337c3SCurtis Malainey #define SHIM_SIZE_CHT 0x118 359e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 369e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 379e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 38ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 399e42c5caSLiam Girdwood 409e42c5caSLiam Girdwood /* DSP peripherals */ 419e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 429e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 439e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 449e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 459e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 469e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 479e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 489e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 499e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 509e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 519e42c5caSLiam Girdwood #define SSP_SIZE 0x100 529e42c5caSLiam Girdwood 539e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE 32 549e42c5caSLiam Girdwood 559e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE 0x200000 569e42c5caSLiam Girdwood 579e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 589e42c5caSLiam Girdwood 599e42c5caSLiam Girdwood /* 609e42c5caSLiam Girdwood * Debug 619e42c5caSLiam Girdwood */ 629e42c5caSLiam Girdwood 639e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 649e42c5caSLiam Girdwood 659e42c5caSLiam Girdwood /* BARs */ 669e42c5caSLiam Girdwood #define BYT_DSP_BAR 0 679e42c5caSLiam Girdwood #define BYT_PCI_BAR 1 689e42c5caSLiam Girdwood #define BYT_IMR_BAR 2 699e42c5caSLiam Girdwood 709e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 719e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 739e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 759e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 779e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 799e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 809e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 819e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 829e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 839e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 849e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 85f84337c3SCurtis Malainey {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 869e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 879e42c5caSLiam Girdwood }; 889e42c5caSLiam Girdwood 899e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev); 909e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev); 919e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev); 929e42c5caSLiam Girdwood 939e42c5caSLiam Girdwood /* 949e42c5caSLiam Girdwood * Debug 959e42c5caSLiam Girdwood */ 969e42c5caSLiam Girdwood 979e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev, 989e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 999e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 1009e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 1019e42c5caSLiam Girdwood { 10214104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 10314104eb6SKai Vehmanen 1049e42c5caSLiam Girdwood /* first read regsisters */ 10514104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 10614104eb6SKai Vehmanen 10714104eb6SKai Vehmanen /* note: variable AR register array is not read */ 1089e42c5caSLiam Girdwood 1099e42c5caSLiam Girdwood /* then get panic info */ 110ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 111ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 112ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 113ff2be865SLiam Girdwood return; 114ff2be865SLiam Girdwood } 11514104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 11614104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 1179e42c5caSLiam Girdwood 1189e42c5caSLiam Girdwood /* then get the stack */ 11914104eb6SKai Vehmanen offset += sizeof(*panic_info); 12014104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 1219e42c5caSLiam Girdwood } 1229e42c5caSLiam Girdwood 1239e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 1249e42c5caSLiam Girdwood { 1259e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 1269e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 1279e42c5caSLiam Girdwood u32 stack[BYT_STACK_DUMP_SIZE]; 128b81eb73bSKeyon Jie u64 status, panic, imrd, imrx; 1299e42c5caSLiam Girdwood 1309e42c5caSLiam Girdwood /* now try generic SOF status messages */ 131b81eb73bSKeyon Jie status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 132b81eb73bSKeyon Jie panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1339e42c5caSLiam Girdwood byt_get_registers(sdev, &xoops, &panic_info, stack, 1349e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1359e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 1369e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1373a9e204dSLiam Girdwood 1383a9e204dSLiam Girdwood /* provide some context for firmware debug */ 139b81eb73bSKeyon Jie imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 140b81eb73bSKeyon Jie imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 1413a9e204dSLiam Girdwood dev_err(sdev->dev, 142b81eb73bSKeyon Jie "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 143f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 144f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 1453a9e204dSLiam Girdwood dev_err(sdev->dev, 146b81eb73bSKeyon Jie "error: mask host: pending %s complete %s raw 0x%llx\n", 147f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 148f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 1493a9e204dSLiam Girdwood dev_err(sdev->dev, 150b81eb73bSKeyon Jie "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 151f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_BUSY) ? "yes" : "no", 152f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 1533a9e204dSLiam Girdwood dev_err(sdev->dev, 154b81eb73bSKeyon Jie "error: mask DSP: pending %s complete %s raw 0x%llx\n", 155f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 156f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 1573a9e204dSLiam Girdwood 1589e42c5caSLiam Girdwood } 1599e42c5caSLiam Girdwood 1609e42c5caSLiam Girdwood /* 1619e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 1629e42c5caSLiam Girdwood */ 1639e42c5caSLiam Girdwood 1649e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context) 1659e42c5caSLiam Girdwood { 1669e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1673d3d1fb9SPierre-Louis Bossart u64 ipcx, ipcd; 1689e42c5caSLiam Girdwood int ret = IRQ_NONE; 1699e42c5caSLiam Girdwood 1703d3d1fb9SPierre-Louis Bossart ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1713d3d1fb9SPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 1723d3d1fb9SPierre-Louis Bossart 1733d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 1743d3d1fb9SPierre-Louis Bossart 1753d3d1fb9SPierre-Louis Bossart /* reply message from DSP, Mask Done interrupt first */ 1763d3d1fb9SPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 1773d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 1783d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE, 1793d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE); 1809e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 1813d3d1fb9SPierre-Louis Bossart } 1823d3d1fb9SPierre-Louis Bossart 1833d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 1843d3d1fb9SPierre-Louis Bossart 1853d3d1fb9SPierre-Louis Bossart /* new message from DSP, Mask Busy interrupt first */ 1863d3d1fb9SPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 1873d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 1883d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY, 1893d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY); 1903d3d1fb9SPierre-Louis Bossart ret = IRQ_WAKE_THREAD; 1913d3d1fb9SPierre-Louis Bossart } 1929e42c5caSLiam Girdwood 1939e42c5caSLiam Girdwood return ret; 1949e42c5caSLiam Girdwood } 1959e42c5caSLiam Girdwood 1969e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context) 1979e42c5caSLiam Girdwood { 1989e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1999e42c5caSLiam Girdwood u64 ipcx, ipcd; 2009e42c5caSLiam Girdwood 2019e42c5caSLiam Girdwood ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 2023d3d1fb9SPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 2039e42c5caSLiam Girdwood 2049e42c5caSLiam Girdwood /* reply message from DSP */ 2053d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 2061183e9a6SGuennadi Liakhovetski 2071183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2081183e9a6SGuennadi Liakhovetski 2099e42c5caSLiam Girdwood /* 2109e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 2119e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 2129e42c5caSLiam Girdwood * end of message processing function, else set it here 2139e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 2149e42c5caSLiam Girdwood * which is triggered by msg 2159e42c5caSLiam Girdwood */ 2169e42c5caSLiam Girdwood byt_get_reply(sdev); 2179e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 2189e42c5caSLiam Girdwood 2199e42c5caSLiam Girdwood byt_dsp_done(sdev); 2201183e9a6SGuennadi Liakhovetski 2211183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 2229e42c5caSLiam Girdwood } 2239e42c5caSLiam Girdwood 2249e42c5caSLiam Girdwood /* new message from DSP */ 2253d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 2269e42c5caSLiam Girdwood 2279e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 2289e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 2299e42c5caSLiam Girdwood snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 2309e42c5caSLiam Girdwood MBOX_OFFSET); 2319e42c5caSLiam Girdwood } else { 2329e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 2339e42c5caSLiam Girdwood } 2349e42c5caSLiam Girdwood 2359e42c5caSLiam Girdwood byt_host_done(sdev); 2369e42c5caSLiam Girdwood } 2379e42c5caSLiam Girdwood 2389e42c5caSLiam Girdwood return IRQ_HANDLED; 2399e42c5caSLiam Girdwood } 2409e42c5caSLiam Girdwood 2419e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 2429e42c5caSLiam Girdwood { 2433d2e5c48SKeyon Jie /* unmask and prepare to receive Done interrupt */ 2443d2e5c48SKeyon Jie snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 2453d2e5c48SKeyon Jie SHIM_IMRX_DONE, 0); 2463d2e5c48SKeyon Jie 2479e42c5caSLiam Girdwood /* send the message */ 2489e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 2499e42c5caSLiam Girdwood msg->msg_size); 2506fbbc18eSDaniel Baluta snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 2519e42c5caSLiam Girdwood 2529e42c5caSLiam Girdwood return 0; 2539e42c5caSLiam Girdwood } 2549e42c5caSLiam Girdwood 2559e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev) 2569e42c5caSLiam Girdwood { 2579e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 2589e42c5caSLiam Girdwood struct sof_ipc_reply reply; 2599e42c5caSLiam Girdwood int ret = 0; 2609e42c5caSLiam Girdwood 2619e42c5caSLiam Girdwood /* 2629e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 2639e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 2649e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 2659e42c5caSLiam Girdwood */ 2669e42c5caSLiam Girdwood if (!msg) { 2679e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 2689e42c5caSLiam Girdwood return; 2699e42c5caSLiam Girdwood } 2709e42c5caSLiam Girdwood 2719e42c5caSLiam Girdwood /* get reply */ 2729e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 2739e42c5caSLiam Girdwood 2749e42c5caSLiam Girdwood if (reply.error < 0) { 2759e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 2769e42c5caSLiam Girdwood ret = reply.error; 2779e42c5caSLiam Girdwood } else { 2789e42c5caSLiam Girdwood /* reply correct size ? */ 2799e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 2809e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 2819e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 2829e42c5caSLiam Girdwood ret = -EINVAL; 2839e42c5caSLiam Girdwood } 2849e42c5caSLiam Girdwood 2859e42c5caSLiam Girdwood /* read the message */ 2869e42c5caSLiam Girdwood if (msg->reply_size > 0) 2879e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 2889e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 2899e42c5caSLiam Girdwood } 2909e42c5caSLiam Girdwood 2919e42c5caSLiam Girdwood msg->reply_error = ret; 2929e42c5caSLiam Girdwood } 2939e42c5caSLiam Girdwood 29483ee7ab1SDaniel Baluta static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 29583ee7ab1SDaniel Baluta { 29683ee7ab1SDaniel Baluta return MBOX_OFFSET; 29783ee7ab1SDaniel Baluta } 29883ee7ab1SDaniel Baluta 29983ee7ab1SDaniel Baluta static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 30083ee7ab1SDaniel Baluta { 30183ee7ab1SDaniel Baluta return MBOX_OFFSET; 30283ee7ab1SDaniel Baluta } 30383ee7ab1SDaniel Baluta 3049e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev) 3059e42c5caSLiam Girdwood { 3069e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 3079e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 3089e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 3099e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 3109e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 3119e42c5caSLiam Girdwood 3123d2e5c48SKeyon Jie /* unmask and prepare to receive next new message */ 3139e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3149e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 3159e42c5caSLiam Girdwood } 3169e42c5caSLiam Girdwood 3179e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev) 3189e42c5caSLiam Girdwood { 3199e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 3209e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 3219e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 3229e42c5caSLiam Girdwood } 3239e42c5caSLiam Girdwood 3249e42c5caSLiam Girdwood /* 3259e42c5caSLiam Girdwood * DSP control. 3269e42c5caSLiam Girdwood */ 3279e42c5caSLiam Girdwood 3289e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev) 3299e42c5caSLiam Girdwood { 3309e42c5caSLiam Girdwood int tries = 10; 3319e42c5caSLiam Girdwood 3329e42c5caSLiam Girdwood /* release stall and wait to unstall */ 3339e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3349e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 3359e42c5caSLiam Girdwood while (tries--) { 3369e42c5caSLiam Girdwood if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 3379e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 3389e42c5caSLiam Girdwood break; 3399e42c5caSLiam Girdwood msleep(100); 3409e42c5caSLiam Girdwood } 3419e42c5caSLiam Girdwood if (tries < 0) { 3429e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 343fbfa22ecSRanjani Sridharan byt_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX); 3449e42c5caSLiam Girdwood return -ENODEV; 3459e42c5caSLiam Girdwood } 3469e42c5caSLiam Girdwood 3479e42c5caSLiam Girdwood /* return init core mask */ 3489e42c5caSLiam Girdwood return 1; 3499e42c5caSLiam Girdwood } 3509e42c5caSLiam Girdwood 3519e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev) 3529e42c5caSLiam Girdwood { 3539e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 3549e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3559e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3569e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 3579e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3589e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 3599e42c5caSLiam Girdwood 3609e42c5caSLiam Girdwood usleep_range(10, 15); 3619e42c5caSLiam Girdwood 3629e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 3639e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3649e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 3659e42c5caSLiam Girdwood 3669e42c5caSLiam Girdwood return 0; 3679e42c5caSLiam Girdwood } 3689e42c5caSLiam Girdwood 3692aae447aSPierre-Louis Bossart static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 3702aae447aSPierre-Louis Bossart const char *sof_tplg_filename, 3712aae447aSPierre-Louis Bossart const char *ssp_str) 3722aae447aSPierre-Louis Bossart { 3732aae447aSPierre-Louis Bossart const char *tplg_filename = NULL; 3742aae447aSPierre-Louis Bossart char *filename; 3752aae447aSPierre-Louis Bossart char *split_ext; 3762aae447aSPierre-Louis Bossart 3772aae447aSPierre-Louis Bossart filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 3782aae447aSPierre-Louis Bossart if (!filename) 3792aae447aSPierre-Louis Bossart return NULL; 3802aae447aSPierre-Louis Bossart 3812aae447aSPierre-Louis Bossart /* this assumes a .tplg extension */ 3822aae447aSPierre-Louis Bossart split_ext = strsep(&filename, "."); 3832aae447aSPierre-Louis Bossart if (split_ext) { 3842aae447aSPierre-Louis Bossart tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 3852aae447aSPierre-Louis Bossart "%s-%s.tplg", 3862aae447aSPierre-Louis Bossart split_ext, ssp_str); 3872aae447aSPierre-Louis Bossart if (!tplg_filename) 3882aae447aSPierre-Louis Bossart return NULL; 3892aae447aSPierre-Louis Bossart } 3902aae447aSPierre-Louis Bossart return tplg_filename; 3912aae447aSPierre-Louis Bossart } 3922aae447aSPierre-Louis Bossart 393285880a2SDaniel Baluta static void byt_machine_select(struct snd_sof_dev *sdev) 394285880a2SDaniel Baluta { 395285880a2SDaniel Baluta struct snd_sof_pdata *sof_pdata = sdev->pdata; 396285880a2SDaniel Baluta const struct sof_dev_desc *desc = sof_pdata->desc; 397285880a2SDaniel Baluta struct snd_soc_acpi_mach *mach; 3982aae447aSPierre-Louis Bossart struct platform_device *pdev; 3992aae447aSPierre-Louis Bossart const char *tplg_filename; 400285880a2SDaniel Baluta 401285880a2SDaniel Baluta mach = snd_soc_acpi_find_machine(desc->machines); 402285880a2SDaniel Baluta if (!mach) { 403285880a2SDaniel Baluta dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 404285880a2SDaniel Baluta return; 405285880a2SDaniel Baluta } 406285880a2SDaniel Baluta 4072aae447aSPierre-Louis Bossart pdev = to_platform_device(sdev->dev); 4082aae447aSPierre-Louis Bossart if (soc_intel_is_byt_cr(pdev)) { 4092aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4102aae447aSPierre-Louis Bossart "BYT-CR detected, SSP0 used instead of SSP2\n"); 4112aae447aSPierre-Louis Bossart 4122aae447aSPierre-Louis Bossart tplg_filename = fixup_tplg_name(sdev, 4132aae447aSPierre-Louis Bossart mach->sof_tplg_filename, 4142aae447aSPierre-Louis Bossart "ssp0"); 4152aae447aSPierre-Louis Bossart } else { 4162aae447aSPierre-Louis Bossart tplg_filename = mach->sof_tplg_filename; 4172aae447aSPierre-Louis Bossart } 4182aae447aSPierre-Louis Bossart 4192aae447aSPierre-Louis Bossart if (!tplg_filename) { 4202aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4212aae447aSPierre-Louis Bossart "error: no topology filename\n"); 4222aae447aSPierre-Louis Bossart return; 4232aae447aSPierre-Louis Bossart } 4242aae447aSPierre-Louis Bossart 4252aae447aSPierre-Louis Bossart sof_pdata->tplg_filename = tplg_filename; 426285880a2SDaniel Baluta mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 427285880a2SDaniel Baluta sof_pdata->machine = mach; 428285880a2SDaniel Baluta } 429285880a2SDaniel Baluta 430285880a2SDaniel Baluta static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 431285880a2SDaniel Baluta struct device *dev) 432285880a2SDaniel Baluta { 433285880a2SDaniel Baluta struct snd_soc_acpi_mach_params *mach_params; 434285880a2SDaniel Baluta 435285880a2SDaniel Baluta mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 436285880a2SDaniel Baluta mach_params->platform = dev_name(dev); 437285880a2SDaniel Baluta } 438285880a2SDaniel Baluta 4399e42c5caSLiam Girdwood /* Baytrail DAIs */ 4409e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = { 4419e42c5caSLiam Girdwood { 4429e42c5caSLiam Girdwood .name = "ssp0-port", 4438c05246cSPierre-Louis Bossart .playback = { 4448c05246cSPierre-Louis Bossart .channels_min = 1, 4458c05246cSPierre-Louis Bossart .channels_max = 8, 4468c05246cSPierre-Louis Bossart }, 4478c05246cSPierre-Louis Bossart .capture = { 4488c05246cSPierre-Louis Bossart .channels_min = 1, 4498c05246cSPierre-Louis Bossart .channels_max = 8, 4508c05246cSPierre-Louis Bossart }, 4519e42c5caSLiam Girdwood }, 4529e42c5caSLiam Girdwood { 4539e42c5caSLiam Girdwood .name = "ssp1-port", 4548c05246cSPierre-Louis Bossart .playback = { 4558c05246cSPierre-Louis Bossart .channels_min = 1, 4568c05246cSPierre-Louis Bossart .channels_max = 8, 4578c05246cSPierre-Louis Bossart }, 4588c05246cSPierre-Louis Bossart .capture = { 4598c05246cSPierre-Louis Bossart .channels_min = 1, 4608c05246cSPierre-Louis Bossart .channels_max = 8, 4618c05246cSPierre-Louis Bossart }, 4629e42c5caSLiam Girdwood }, 4639e42c5caSLiam Girdwood { 4649e42c5caSLiam Girdwood .name = "ssp2-port", 4658c05246cSPierre-Louis Bossart .playback = { 4668c05246cSPierre-Louis Bossart .channels_min = 1, 4678c05246cSPierre-Louis Bossart .channels_max = 8, 4688c05246cSPierre-Louis Bossart }, 4698c05246cSPierre-Louis Bossart .capture = { 4708c05246cSPierre-Louis Bossart .channels_min = 1, 4718c05246cSPierre-Louis Bossart .channels_max = 8, 4728c05246cSPierre-Louis Bossart } 4739e42c5caSLiam Girdwood }, 4749e42c5caSLiam Girdwood { 4759e42c5caSLiam Girdwood .name = "ssp3-port", 4768c05246cSPierre-Louis Bossart .playback = { 4778c05246cSPierre-Louis Bossart .channels_min = 1, 4788c05246cSPierre-Louis Bossart .channels_max = 8, 4798c05246cSPierre-Louis Bossart }, 4808c05246cSPierre-Louis Bossart .capture = { 4818c05246cSPierre-Louis Bossart .channels_min = 1, 4828c05246cSPierre-Louis Bossart .channels_max = 8, 4838c05246cSPierre-Louis Bossart }, 4849e42c5caSLiam Girdwood }, 4859e42c5caSLiam Girdwood { 4869e42c5caSLiam Girdwood .name = "ssp4-port", 4878c05246cSPierre-Louis Bossart .playback = { 4888c05246cSPierre-Louis Bossart .channels_min = 1, 4898c05246cSPierre-Louis Bossart .channels_max = 8, 4908c05246cSPierre-Louis Bossart }, 4918c05246cSPierre-Louis Bossart .capture = { 4928c05246cSPierre-Louis Bossart .channels_min = 1, 4938c05246cSPierre-Louis Bossart .channels_max = 8, 4948c05246cSPierre-Louis Bossart }, 4959e42c5caSLiam Girdwood }, 4969e42c5caSLiam Girdwood { 4979e42c5caSLiam Girdwood .name = "ssp5-port", 4988c05246cSPierre-Louis Bossart .playback = { 4998c05246cSPierre-Louis Bossart .channels_min = 1, 5008c05246cSPierre-Louis Bossart .channels_max = 8, 5018c05246cSPierre-Louis Bossart }, 5028c05246cSPierre-Louis Bossart .capture = { 5038c05246cSPierre-Louis Bossart .channels_min = 1, 5048c05246cSPierre-Louis Bossart .channels_max = 8, 5058c05246cSPierre-Louis Bossart }, 5069e42c5caSLiam Girdwood }, 5079e42c5caSLiam Girdwood }; 5089e42c5caSLiam Girdwood 5099e42c5caSLiam Girdwood /* 5109e42c5caSLiam Girdwood * Probe and remove. 5119e42c5caSLiam Girdwood */ 5129e42c5caSLiam Girdwood 5139e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 5149e42c5caSLiam Girdwood 5159e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 5169e42c5caSLiam Girdwood { 5179e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5189e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5199e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 5209e42c5caSLiam Girdwood u32 base, size; 5219e42c5caSLiam Girdwood int ret; 5229e42c5caSLiam Girdwood 5239e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5249e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 5259e42c5caSLiam Girdwood if (ret < 0) { 5269e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5279e42c5caSLiam Girdwood return ret; 5289e42c5caSLiam Girdwood } 5299e42c5caSLiam Girdwood 5309e42c5caSLiam Girdwood /* LPE base */ 5319e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 5329e42c5caSLiam Girdwood size = BYT_PCI_BAR_SIZE; 5339e42c5caSLiam Girdwood 5349e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 5359e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 5369e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 5379e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5389e42c5caSLiam Girdwood base, size); 5399e42c5caSLiam Girdwood return -ENODEV; 5409e42c5caSLiam Girdwood } 5419e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 5429e42c5caSLiam Girdwood 5439e42c5caSLiam Girdwood /* IMR base - optional */ 5449e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5459e42c5caSLiam Girdwood goto irq; 5469e42c5caSLiam Girdwood 5479e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 5489e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 5499e42c5caSLiam Girdwood 5509e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 5519e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 5529e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 5539e42c5caSLiam Girdwood goto irq; 5549e42c5caSLiam Girdwood } 5559e42c5caSLiam Girdwood 5569e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 5579e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 5589e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 5599e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 5609e42c5caSLiam Girdwood base, size); 5619e42c5caSLiam Girdwood return -ENODEV; 5629e42c5caSLiam Girdwood } 5639e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 5649e42c5caSLiam Girdwood 5659e42c5caSLiam Girdwood irq: 5669e42c5caSLiam Girdwood /* register our IRQ */ 5679e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 5689e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 5699e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 5709e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 5719e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 5729e42c5caSLiam Girdwood if (ret < 0) { 5739e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 5749e42c5caSLiam Girdwood sdev->ipc_irq); 5759e42c5caSLiam Girdwood return ret; 5769e42c5caSLiam Girdwood } 5779e42c5caSLiam Girdwood 5783d2e5c48SKeyon Jie /* enable BUSY and disable DONE Interrupt by default */ 5793d2e5c48SKeyon Jie snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 5803d2e5c48SKeyon Jie SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 5813d2e5c48SKeyon Jie SHIM_IMRX_DONE); 5829e42c5caSLiam Girdwood 5839e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 5849e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 5859e42c5caSLiam Girdwood 5869e42c5caSLiam Girdwood return ret; 5879e42c5caSLiam Girdwood } 5889e42c5caSLiam Girdwood 5899e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 5909e42c5caSLiam Girdwood /* device init */ 5919e42c5caSLiam Girdwood .probe = tangier_pci_probe, 5929e42c5caSLiam Girdwood 5939e42c5caSLiam Girdwood /* DSP core boot / reset */ 5949e42c5caSLiam Girdwood .run = byt_run, 5959e42c5caSLiam Girdwood .reset = byt_reset, 5969e42c5caSLiam Girdwood 5979e42c5caSLiam Girdwood /* Register IO */ 5989e42c5caSLiam Girdwood .write = sof_io_write, 5999e42c5caSLiam Girdwood .read = sof_io_read, 6009e42c5caSLiam Girdwood .write64 = sof_io_write64, 6019e42c5caSLiam Girdwood .read64 = sof_io_read64, 6029e42c5caSLiam Girdwood 6039e42c5caSLiam Girdwood /* Block IO */ 6049e42c5caSLiam Girdwood .block_read = sof_block_read, 6059e42c5caSLiam Girdwood .block_write = sof_block_write, 6069e42c5caSLiam Girdwood 6079e42c5caSLiam Girdwood /* doorbell */ 6089e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 6099e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 6109e42c5caSLiam Girdwood 6119e42c5caSLiam Girdwood /* ipc */ 6129e42c5caSLiam Girdwood .send_msg = byt_send_msg, 61383ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 61483ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 61583ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 6169e42c5caSLiam Girdwood 6179e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6189e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6199e42c5caSLiam Girdwood 620285880a2SDaniel Baluta /* machine driver */ 621285880a2SDaniel Baluta .machine_select = byt_machine_select, 622285880a2SDaniel Baluta .machine_register = sof_machine_register, 623285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 624285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 625285880a2SDaniel Baluta 6269e42c5caSLiam Girdwood /* debug */ 6279e42c5caSLiam Girdwood .debug_map = byt_debugfs, 6289e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 6299e42c5caSLiam Girdwood .dbg_dump = byt_dump, 6309e42c5caSLiam Girdwood 6319e42c5caSLiam Girdwood /* stream callbacks */ 6329e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6339e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6349e42c5caSLiam Girdwood 6359e42c5caSLiam Girdwood /* module loading */ 6369e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6379e42c5caSLiam Girdwood 6389e42c5caSLiam Girdwood /*Firmware loading */ 6399e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6409e42c5caSLiam Girdwood 6419e42c5caSLiam Girdwood /* DAI drivers */ 6429e42c5caSLiam Girdwood .drv = byt_dai, 6439e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 64427e322faSPierre-Louis Bossart 64527e322faSPierre-Louis Bossart /* ALSA HW info flags */ 64627e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 64727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 64827e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 64927e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 6504c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 6510f501c7cSPierre-Louis Bossart 6520f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 6539e42c5caSLiam Girdwood }; 654e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 6559e42c5caSLiam Girdwood 6569e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 6579e42c5caSLiam Girdwood .cores_num = 1, 65864b96917SRanjani Sridharan .host_managed_cores_mask = 1, 6599e42c5caSLiam Girdwood }; 660e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 6619e42c5caSLiam Girdwood 6629e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 6639e42c5caSLiam Girdwood 6649e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 6659e42c5caSLiam Girdwood 666af89e7daSPierre-Louis Bossart static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 667af89e7daSPierre-Louis Bossart { 668af89e7daSPierre-Louis Bossart /* Disable Interrupt from both sides */ 669af89e7daSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 670af89e7daSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 671af89e7daSPierre-Louis Bossart 672af89e7daSPierre-Louis Bossart /* Put DSP into reset, set reset vector */ 673af89e7daSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 674af89e7daSPierre-Louis Bossart SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 675af89e7daSPierre-Louis Bossart SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 676af89e7daSPierre-Louis Bossart } 677af89e7daSPierre-Louis Bossart 678af89e7daSPierre-Louis Bossart static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 679af89e7daSPierre-Louis Bossart { 680af89e7daSPierre-Louis Bossart byt_reset_dsp_disable_int(sdev); 681af89e7daSPierre-Louis Bossart 682af89e7daSPierre-Louis Bossart return 0; 683af89e7daSPierre-Louis Bossart } 684af89e7daSPierre-Louis Bossart 685af89e7daSPierre-Louis Bossart static int byt_resume(struct snd_sof_dev *sdev) 686af89e7daSPierre-Louis Bossart { 687af89e7daSPierre-Louis Bossart /* enable BUSY and disable DONE Interrupt by default */ 688af89e7daSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 689af89e7daSPierre-Louis Bossart SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 690af89e7daSPierre-Louis Bossart SHIM_IMRX_DONE); 691af89e7daSPierre-Louis Bossart 692af89e7daSPierre-Louis Bossart return 0; 693af89e7daSPierre-Louis Bossart } 694af89e7daSPierre-Louis Bossart 695af89e7daSPierre-Louis Bossart static int byt_remove(struct snd_sof_dev *sdev) 696af89e7daSPierre-Louis Bossart { 697af89e7daSPierre-Louis Bossart byt_reset_dsp_disable_int(sdev); 698af89e7daSPierre-Louis Bossart 699af89e7daSPierre-Louis Bossart return 0; 700af89e7daSPierre-Louis Bossart } 701af89e7daSPierre-Louis Bossart 70228d4adc4SYueHaibing static const struct snd_sof_debugfs_map cht_debugfs[] = { 70328d4adc4SYueHaibing {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 70428d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70528d4adc4SYueHaibing {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70628d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70728d4adc4SYueHaibing {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 70828d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70928d4adc4SYueHaibing {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 71028d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71128d4adc4SYueHaibing {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 71228d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71328d4adc4SYueHaibing {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 71428d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71528d4adc4SYueHaibing {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 71628d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71728d4adc4SYueHaibing {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 71828d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71928d4adc4SYueHaibing {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 72028d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 72128d4adc4SYueHaibing {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 72228d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 72328d4adc4SYueHaibing {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 72428d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 72528d4adc4SYueHaibing {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 72628d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 72728d4adc4SYueHaibing }; 72828d4adc4SYueHaibing 7299e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 7309e42c5caSLiam Girdwood { 7319e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 7329e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 7339e42c5caSLiam Girdwood struct platform_device *pdev = 7349e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 7359e42c5caSLiam Girdwood struct resource *mmio; 7369e42c5caSLiam Girdwood u32 base, size; 7379e42c5caSLiam Girdwood int ret; 7389e42c5caSLiam Girdwood 7399e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 7409e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 7419e42c5caSLiam Girdwood if (ret < 0) { 7429e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 7439e42c5caSLiam Girdwood return ret; 7449e42c5caSLiam Girdwood } 7459e42c5caSLiam Girdwood 7469e42c5caSLiam Girdwood /* LPE base */ 7479e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7489e42c5caSLiam Girdwood desc->resindex_lpe_base); 7499e42c5caSLiam Girdwood if (mmio) { 7509e42c5caSLiam Girdwood base = mmio->start; 7519e42c5caSLiam Girdwood size = resource_size(mmio); 7529e42c5caSLiam Girdwood } else { 7539e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 7549e42c5caSLiam Girdwood desc->resindex_lpe_base); 7559e42c5caSLiam Girdwood return -EINVAL; 7569e42c5caSLiam Girdwood } 7579e42c5caSLiam Girdwood 7589e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 7599e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 7609e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 7619e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 7629e42c5caSLiam Girdwood base, size); 7639e42c5caSLiam Girdwood return -ENODEV; 7649e42c5caSLiam Girdwood } 7659e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 7669e42c5caSLiam Girdwood 7679e42c5caSLiam Girdwood /* TODO: add offsets */ 7689e42c5caSLiam Girdwood sdev->mmio_bar = BYT_DSP_BAR; 7699e42c5caSLiam Girdwood sdev->mailbox_bar = BYT_DSP_BAR; 7709e42c5caSLiam Girdwood 7719e42c5caSLiam Girdwood /* IMR base - optional */ 7729e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 7739e42c5caSLiam Girdwood goto irq; 7749e42c5caSLiam Girdwood 7759e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7769e42c5caSLiam Girdwood desc->resindex_imr_base); 7779e42c5caSLiam Girdwood if (mmio) { 7789e42c5caSLiam Girdwood base = mmio->start; 7799e42c5caSLiam Girdwood size = resource_size(mmio); 7809e42c5caSLiam Girdwood } else { 7819e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 7829e42c5caSLiam Girdwood desc->resindex_imr_base); 7839e42c5caSLiam Girdwood return -ENODEV; 7849e42c5caSLiam Girdwood } 7859e42c5caSLiam Girdwood 7869e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 7879e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 7889e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 7899e42c5caSLiam Girdwood goto irq; 7909e42c5caSLiam Girdwood } 7919e42c5caSLiam Girdwood 7929e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 7939e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 7949e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 7959e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 7969e42c5caSLiam Girdwood base, size); 7979e42c5caSLiam Girdwood return -ENODEV; 7989e42c5caSLiam Girdwood } 7999e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 8009e42c5caSLiam Girdwood 8019e42c5caSLiam Girdwood irq: 8029e42c5caSLiam Girdwood /* register our IRQ */ 8039e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 804cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 8059e42c5caSLiam Girdwood return sdev->ipc_irq; 8069e42c5caSLiam Girdwood 8079e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 8089e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 8099e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 8109e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 8119e42c5caSLiam Girdwood if (ret < 0) { 8129e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 8139e42c5caSLiam Girdwood sdev->ipc_irq); 8149e42c5caSLiam Girdwood return ret; 8159e42c5caSLiam Girdwood } 8169e42c5caSLiam Girdwood 8173d2e5c48SKeyon Jie /* enable BUSY and disable DONE Interrupt by default */ 8183d2e5c48SKeyon Jie snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 8193d2e5c48SKeyon Jie SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 8203d2e5c48SKeyon Jie SHIM_IMRX_DONE); 8219e42c5caSLiam Girdwood 8229e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 8239e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 8249e42c5caSLiam Girdwood 8259e42c5caSLiam Girdwood return ret; 8269e42c5caSLiam Girdwood } 8279e42c5caSLiam Girdwood 8289e42c5caSLiam Girdwood /* baytrail ops */ 829*8a49cd11SArnd Bergmann static const struct snd_sof_dsp_ops sof_byt_ops = { 8309e42c5caSLiam Girdwood /* device init */ 8319e42c5caSLiam Girdwood .probe = byt_acpi_probe, 832c691f0c6SRanjani Sridharan .remove = byt_remove, 8339e42c5caSLiam Girdwood 8349e42c5caSLiam Girdwood /* DSP core boot / reset */ 8359e42c5caSLiam Girdwood .run = byt_run, 8369e42c5caSLiam Girdwood .reset = byt_reset, 8379e42c5caSLiam Girdwood 8389e42c5caSLiam Girdwood /* Register IO */ 8399e42c5caSLiam Girdwood .write = sof_io_write, 8409e42c5caSLiam Girdwood .read = sof_io_read, 8419e42c5caSLiam Girdwood .write64 = sof_io_write64, 8429e42c5caSLiam Girdwood .read64 = sof_io_read64, 8439e42c5caSLiam Girdwood 8449e42c5caSLiam Girdwood /* Block IO */ 8459e42c5caSLiam Girdwood .block_read = sof_block_read, 8469e42c5caSLiam Girdwood .block_write = sof_block_write, 8479e42c5caSLiam Girdwood 8489e42c5caSLiam Girdwood /* doorbell */ 8499e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 8509e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 8519e42c5caSLiam Girdwood 8529e42c5caSLiam Girdwood /* ipc */ 8539e42c5caSLiam Girdwood .send_msg = byt_send_msg, 85483ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 85583ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 85683ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 8579e42c5caSLiam Girdwood 8589e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8599e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8609e42c5caSLiam Girdwood 861285880a2SDaniel Baluta /* machine driver */ 862285880a2SDaniel Baluta .machine_select = byt_machine_select, 863285880a2SDaniel Baluta .machine_register = sof_machine_register, 864285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 865285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 866285880a2SDaniel Baluta 8679e42c5caSLiam Girdwood /* debug */ 8689e42c5caSLiam Girdwood .debug_map = byt_debugfs, 8699e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 8709e42c5caSLiam Girdwood .dbg_dump = byt_dump, 8719e42c5caSLiam Girdwood 8729e42c5caSLiam Girdwood /* stream callbacks */ 8739e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 8749e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 8759e42c5caSLiam Girdwood 8769e42c5caSLiam Girdwood /* module loading */ 8779e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 8789e42c5caSLiam Girdwood 8799e42c5caSLiam Girdwood /*Firmware loading */ 8809e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 8819e42c5caSLiam Girdwood 882ddcccd54SRanjani Sridharan /* PM */ 883ddcccd54SRanjani Sridharan .suspend = byt_suspend, 884ddcccd54SRanjani Sridharan .resume = byt_resume, 885ddcccd54SRanjani Sridharan 8869e42c5caSLiam Girdwood /* DAI drivers */ 8879e42c5caSLiam Girdwood .drv = byt_dai, 8889e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 88927e322faSPierre-Louis Bossart 89027e322faSPierre-Louis Bossart /* ALSA HW info flags */ 89127e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 89227e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 89327e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 89427e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 8954c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 8960f501c7cSPierre-Louis Bossart 8970f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 8989e42c5caSLiam Girdwood }; 8999e42c5caSLiam Girdwood 900*8a49cd11SArnd Bergmann static const struct sof_intel_dsp_desc byt_chip_info = { 9019e42c5caSLiam Girdwood .cores_num = 1, 90264b96917SRanjani Sridharan .host_managed_cores_mask = 1, 9039e42c5caSLiam Girdwood }; 9049e42c5caSLiam Girdwood 9059e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 906*8a49cd11SArnd Bergmann static const struct snd_sof_dsp_ops sof_cht_ops = { 9079e42c5caSLiam Girdwood /* device init */ 9089e42c5caSLiam Girdwood .probe = byt_acpi_probe, 909c691f0c6SRanjani Sridharan .remove = byt_remove, 9109e42c5caSLiam Girdwood 9119e42c5caSLiam Girdwood /* DSP core boot / reset */ 9129e42c5caSLiam Girdwood .run = byt_run, 9139e42c5caSLiam Girdwood .reset = byt_reset, 9149e42c5caSLiam Girdwood 9159e42c5caSLiam Girdwood /* Register IO */ 9169e42c5caSLiam Girdwood .write = sof_io_write, 9179e42c5caSLiam Girdwood .read = sof_io_read, 9189e42c5caSLiam Girdwood .write64 = sof_io_write64, 9199e42c5caSLiam Girdwood .read64 = sof_io_read64, 9209e42c5caSLiam Girdwood 9219e42c5caSLiam Girdwood /* Block IO */ 9229e42c5caSLiam Girdwood .block_read = sof_block_read, 9239e42c5caSLiam Girdwood .block_write = sof_block_write, 9249e42c5caSLiam Girdwood 9259e42c5caSLiam Girdwood /* doorbell */ 9269e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 9279e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 9289e42c5caSLiam Girdwood 9299e42c5caSLiam Girdwood /* ipc */ 9309e42c5caSLiam Girdwood .send_msg = byt_send_msg, 93183ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 93283ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 93383ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 9349e42c5caSLiam Girdwood 9359e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 9369e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 9379e42c5caSLiam Girdwood 938285880a2SDaniel Baluta /* machine driver */ 939285880a2SDaniel Baluta .machine_select = byt_machine_select, 940285880a2SDaniel Baluta .machine_register = sof_machine_register, 941285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 942285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 943285880a2SDaniel Baluta 9449e42c5caSLiam Girdwood /* debug */ 9459e42c5caSLiam Girdwood .debug_map = cht_debugfs, 9469e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 9479e42c5caSLiam Girdwood .dbg_dump = byt_dump, 9489e42c5caSLiam Girdwood 9499e42c5caSLiam Girdwood /* stream callbacks */ 9509e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 9519e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 9529e42c5caSLiam Girdwood 9539e42c5caSLiam Girdwood /* module loading */ 9549e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 9559e42c5caSLiam Girdwood 9569e42c5caSLiam Girdwood /*Firmware loading */ 9579e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 9589e42c5caSLiam Girdwood 959ddcccd54SRanjani Sridharan /* PM */ 960ddcccd54SRanjani Sridharan .suspend = byt_suspend, 961ddcccd54SRanjani Sridharan .resume = byt_resume, 962ddcccd54SRanjani Sridharan 9639e42c5caSLiam Girdwood /* DAI drivers */ 9649e42c5caSLiam Girdwood .drv = byt_dai, 9659e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 9669e42c5caSLiam Girdwood .num_drv = ARRAY_SIZE(byt_dai), 96727e322faSPierre-Louis Bossart 96827e322faSPierre-Louis Bossart /* ALSA HW info flags */ 96927e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 97027e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 97127e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 97227e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 9734c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 9740f501c7cSPierre-Louis Bossart 9750f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 9769e42c5caSLiam Girdwood }; 9779e42c5caSLiam Girdwood 978*8a49cd11SArnd Bergmann static const struct sof_intel_dsp_desc cht_chip_info = { 9799e42c5caSLiam Girdwood .cores_num = 1, 98064b96917SRanjani Sridharan .host_managed_cores_mask = 1, 9819e42c5caSLiam Girdwood }; 982*8a49cd11SArnd Bergmann 983*8a49cd11SArnd Bergmann /* BYTCR uses different IRQ index */ 984*8a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { 985*8a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_baytrail_machines, 986*8a49cd11SArnd Bergmann .resindex_lpe_base = 0, 987*8a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 988*8a49cd11SArnd Bergmann .resindex_imr_base = 2, 989*8a49cd11SArnd Bergmann .irqindex_host_ipc = 0, 990*8a49cd11SArnd Bergmann .chip_info = &byt_chip_info, 991*8a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 992*8a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 993*8a49cd11SArnd Bergmann .default_fw_filename = "sof-byt.ri", 994*8a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 995*8a49cd11SArnd Bergmann .ops = &sof_byt_ops, 996*8a49cd11SArnd Bergmann }; 997*8a49cd11SArnd Bergmann 998*8a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_baytrail_desc = { 999*8a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_baytrail_machines, 1000*8a49cd11SArnd Bergmann .resindex_lpe_base = 0, 1001*8a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 1002*8a49cd11SArnd Bergmann .resindex_imr_base = 2, 1003*8a49cd11SArnd Bergmann .irqindex_host_ipc = 5, 1004*8a49cd11SArnd Bergmann .chip_info = &byt_chip_info, 1005*8a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 1006*8a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 1007*8a49cd11SArnd Bergmann .default_fw_filename = "sof-byt.ri", 1008*8a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 1009*8a49cd11SArnd Bergmann .ops = &sof_byt_ops, 1010*8a49cd11SArnd Bergmann }; 1011*8a49cd11SArnd Bergmann 1012*8a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { 1013*8a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_cherrytrail_machines, 1014*8a49cd11SArnd Bergmann .resindex_lpe_base = 0, 1015*8a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 1016*8a49cd11SArnd Bergmann .resindex_imr_base = 2, 1017*8a49cd11SArnd Bergmann .irqindex_host_ipc = 5, 1018*8a49cd11SArnd Bergmann .chip_info = &cht_chip_info, 1019*8a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 1020*8a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 1021*8a49cd11SArnd Bergmann .default_fw_filename = "sof-cht.ri", 1022*8a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-cht-nocodec.tplg", 1023*8a49cd11SArnd Bergmann .ops = &sof_cht_ops, 1024*8a49cd11SArnd Bergmann }; 1025*8a49cd11SArnd Bergmann 1026*8a49cd11SArnd Bergmann static const struct acpi_device_id sof_baytrail_match[] = { 1027*8a49cd11SArnd Bergmann { "80860F28", (unsigned long)&sof_acpi_baytrail_desc }, 1028*8a49cd11SArnd Bergmann { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc }, 1029*8a49cd11SArnd Bergmann { } 1030*8a49cd11SArnd Bergmann }; 1031*8a49cd11SArnd Bergmann MODULE_DEVICE_TABLE(acpi, sof_baytrail_match); 1032*8a49cd11SArnd Bergmann 1033*8a49cd11SArnd Bergmann static int sof_baytrail_probe(struct platform_device *pdev) 1034*8a49cd11SArnd Bergmann { 1035*8a49cd11SArnd Bergmann struct device *dev = &pdev->dev; 1036*8a49cd11SArnd Bergmann const struct sof_dev_desc *desc; 1037*8a49cd11SArnd Bergmann const struct acpi_device_id *id; 1038*8a49cd11SArnd Bergmann int ret; 1039*8a49cd11SArnd Bergmann 1040*8a49cd11SArnd Bergmann id = acpi_match_device(dev->driver->acpi_match_table, dev); 1041*8a49cd11SArnd Bergmann if (!id) 1042*8a49cd11SArnd Bergmann return -ENODEV; 1043*8a49cd11SArnd Bergmann 1044*8a49cd11SArnd Bergmann ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 1045*8a49cd11SArnd Bergmann if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1046*8a49cd11SArnd Bergmann dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 1047*8a49cd11SArnd Bergmann return -ENODEV; 1048*8a49cd11SArnd Bergmann } 1049*8a49cd11SArnd Bergmann 1050*8a49cd11SArnd Bergmann desc = device_get_match_data(&pdev->dev); 1051*8a49cd11SArnd Bergmann if (!desc) 1052*8a49cd11SArnd Bergmann return -ENODEV; 1053*8a49cd11SArnd Bergmann 1054*8a49cd11SArnd Bergmann if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) 1055*8a49cd11SArnd Bergmann desc = &sof_acpi_baytrailcr_desc; 1056*8a49cd11SArnd Bergmann 1057*8a49cd11SArnd Bergmann return sof_acpi_probe(pdev, desc); 1058*8a49cd11SArnd Bergmann } 1059*8a49cd11SArnd Bergmann 1060*8a49cd11SArnd Bergmann /* acpi_driver definition */ 1061*8a49cd11SArnd Bergmann static struct platform_driver snd_sof_acpi_intel_byt_driver = { 1062*8a49cd11SArnd Bergmann .probe = sof_baytrail_probe, 1063*8a49cd11SArnd Bergmann .remove = sof_acpi_remove, 1064*8a49cd11SArnd Bergmann .driver = { 1065*8a49cd11SArnd Bergmann .name = "sof-audio-acpi-intel-byt", 1066*8a49cd11SArnd Bergmann .pm = &sof_acpi_pm, 1067*8a49cd11SArnd Bergmann .acpi_match_table = sof_baytrail_match, 1068*8a49cd11SArnd Bergmann }, 1069*8a49cd11SArnd Bergmann }; 1070*8a49cd11SArnd Bergmann module_platform_driver(snd_sof_acpi_intel_byt_driver); 10719e42c5caSLiam Girdwood 10729e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 10739e42c5caSLiam Girdwood 10749e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 1075f4483a0fSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 1076068ac0dbSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1077*8a49cd11SArnd Bergmann MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 1078