1e149ca29SPierre-Louis Bossart // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 189e42c5caSLiam Girdwood #include "../ops.h" 199e42c5caSLiam Girdwood #include "shim.h" 20285880a2SDaniel Baluta #include "../sof-audio.h" 212aae447aSPierre-Louis Bossart #include "../../intel/common/soc-intel-quirks.h" 229e42c5caSLiam Girdwood 239e42c5caSLiam Girdwood /* DSP memories */ 249e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 259e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 269e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 279e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 289e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 29f84337c3SCurtis Malainey #define SHIM_SIZE_BYT 0x100 30f84337c3SCurtis Malainey #define SHIM_SIZE_CHT 0x118 319e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 329e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 339e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 34ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 359e42c5caSLiam Girdwood 369e42c5caSLiam Girdwood /* DSP peripherals */ 379e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 389e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 399e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 409e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 419e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 429e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 439e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 449e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 459e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 469e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 479e42c5caSLiam Girdwood #define SSP_SIZE 0x100 489e42c5caSLiam Girdwood 499e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE 32 509e42c5caSLiam Girdwood 519e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE 0x200000 529e42c5caSLiam Girdwood 539e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 549e42c5caSLiam Girdwood 559e42c5caSLiam Girdwood /* 569e42c5caSLiam Girdwood * Debug 579e42c5caSLiam Girdwood */ 589e42c5caSLiam Girdwood 599e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 609e42c5caSLiam Girdwood 619e42c5caSLiam Girdwood /* BARs */ 629e42c5caSLiam Girdwood #define BYT_DSP_BAR 0 639e42c5caSLiam Girdwood #define BYT_PCI_BAR 1 649e42c5caSLiam Girdwood #define BYT_IMR_BAR 2 659e42c5caSLiam Girdwood 669e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 679e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 689e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 699e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 709e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 719e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 739e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 759e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 779e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 799e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 809e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 81f84337c3SCurtis Malainey {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 829e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 839e42c5caSLiam Girdwood }; 849e42c5caSLiam Girdwood 859e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev); 869e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev); 879e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev); 889e42c5caSLiam Girdwood 899e42c5caSLiam Girdwood /* 909e42c5caSLiam Girdwood * Debug 919e42c5caSLiam Girdwood */ 929e42c5caSLiam Girdwood 939e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev, 949e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 959e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 969e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 979e42c5caSLiam Girdwood { 9814104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 9914104eb6SKai Vehmanen 1009e42c5caSLiam Girdwood /* first read regsisters */ 10114104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 10214104eb6SKai Vehmanen 10314104eb6SKai Vehmanen /* note: variable AR register array is not read */ 1049e42c5caSLiam Girdwood 1059e42c5caSLiam Girdwood /* then get panic info */ 106ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 107ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 108ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 109ff2be865SLiam Girdwood return; 110ff2be865SLiam Girdwood } 11114104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 11214104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 1139e42c5caSLiam Girdwood 1149e42c5caSLiam Girdwood /* then get the stack */ 11514104eb6SKai Vehmanen offset += sizeof(*panic_info); 11614104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 1179e42c5caSLiam Girdwood } 1189e42c5caSLiam Girdwood 1199e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 1209e42c5caSLiam Girdwood { 1219e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 1229e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 1239e42c5caSLiam Girdwood u32 stack[BYT_STACK_DUMP_SIZE]; 124b81eb73bSKeyon Jie u64 status, panic, imrd, imrx; 1259e42c5caSLiam Girdwood 1269e42c5caSLiam Girdwood /* now try generic SOF status messages */ 127b81eb73bSKeyon Jie status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 128b81eb73bSKeyon Jie panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1299e42c5caSLiam Girdwood byt_get_registers(sdev, &xoops, &panic_info, stack, 1309e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1319e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 1329e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1333a9e204dSLiam Girdwood 1343a9e204dSLiam Girdwood /* provide some context for firmware debug */ 135b81eb73bSKeyon Jie imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 136b81eb73bSKeyon Jie imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 1373a9e204dSLiam Girdwood dev_err(sdev->dev, 138b81eb73bSKeyon Jie "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 139f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 140f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 1413a9e204dSLiam Girdwood dev_err(sdev->dev, 142b81eb73bSKeyon Jie "error: mask host: pending %s complete %s raw 0x%llx\n", 143f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 144f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 1453a9e204dSLiam Girdwood dev_err(sdev->dev, 146b81eb73bSKeyon Jie "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 147f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_BUSY) ? "yes" : "no", 148f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 1493a9e204dSLiam Girdwood dev_err(sdev->dev, 150b81eb73bSKeyon Jie "error: mask DSP: pending %s complete %s raw 0x%llx\n", 151f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 152f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 1533a9e204dSLiam Girdwood 1549e42c5caSLiam Girdwood } 1559e42c5caSLiam Girdwood 1569e42c5caSLiam Girdwood /* 1579e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 1589e42c5caSLiam Girdwood */ 1599e42c5caSLiam Girdwood 1609e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context) 1619e42c5caSLiam Girdwood { 1629e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1633d3d1fb9SPierre-Louis Bossart u64 ipcx, ipcd; 1649e42c5caSLiam Girdwood int ret = IRQ_NONE; 1659e42c5caSLiam Girdwood 1663d3d1fb9SPierre-Louis Bossart ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1673d3d1fb9SPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 1683d3d1fb9SPierre-Louis Bossart 1693d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 1703d3d1fb9SPierre-Louis Bossart 1713d3d1fb9SPierre-Louis Bossart /* reply message from DSP, Mask Done interrupt first */ 1723d3d1fb9SPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 1733d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 1743d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE, 1753d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE); 1769e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 1773d3d1fb9SPierre-Louis Bossart } 1783d3d1fb9SPierre-Louis Bossart 1793d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 1803d3d1fb9SPierre-Louis Bossart 1813d3d1fb9SPierre-Louis Bossart /* new message from DSP, Mask Busy interrupt first */ 1823d3d1fb9SPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 1833d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 1843d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY, 1853d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY); 1863d3d1fb9SPierre-Louis Bossart ret = IRQ_WAKE_THREAD; 1873d3d1fb9SPierre-Louis Bossart } 1889e42c5caSLiam Girdwood 1899e42c5caSLiam Girdwood return ret; 1909e42c5caSLiam Girdwood } 1919e42c5caSLiam Girdwood 1929e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context) 1939e42c5caSLiam Girdwood { 1949e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1959e42c5caSLiam Girdwood u64 ipcx, ipcd; 1969e42c5caSLiam Girdwood 1979e42c5caSLiam Girdwood ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 1983d3d1fb9SPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 1999e42c5caSLiam Girdwood 2009e42c5caSLiam Girdwood /* reply message from DSP */ 2013d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 2021183e9a6SGuennadi Liakhovetski 2031183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2041183e9a6SGuennadi Liakhovetski 2059e42c5caSLiam Girdwood /* 2069e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 2079e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 2089e42c5caSLiam Girdwood * end of message processing function, else set it here 2099e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 2109e42c5caSLiam Girdwood * which is triggered by msg 2119e42c5caSLiam Girdwood */ 2129e42c5caSLiam Girdwood byt_get_reply(sdev); 2139e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 2149e42c5caSLiam Girdwood 2159e42c5caSLiam Girdwood byt_dsp_done(sdev); 2161183e9a6SGuennadi Liakhovetski 2171183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 2189e42c5caSLiam Girdwood } 2199e42c5caSLiam Girdwood 2209e42c5caSLiam Girdwood /* new message from DSP */ 2213d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 2229e42c5caSLiam Girdwood 2239e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 2249e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 2259e42c5caSLiam Girdwood snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 2269e42c5caSLiam Girdwood MBOX_OFFSET); 2279e42c5caSLiam Girdwood } else { 2289e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 2299e42c5caSLiam Girdwood } 2309e42c5caSLiam Girdwood 2319e42c5caSLiam Girdwood byt_host_done(sdev); 2329e42c5caSLiam Girdwood } 2339e42c5caSLiam Girdwood 2349e42c5caSLiam Girdwood return IRQ_HANDLED; 2359e42c5caSLiam Girdwood } 2369e42c5caSLiam Girdwood 2379e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 2389e42c5caSLiam Girdwood { 2399e42c5caSLiam Girdwood /* send the message */ 2409e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 2419e42c5caSLiam Girdwood msg->msg_size); 2426fbbc18eSDaniel Baluta snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 2439e42c5caSLiam Girdwood 2449e42c5caSLiam Girdwood return 0; 2459e42c5caSLiam Girdwood } 2469e42c5caSLiam Girdwood 2479e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev) 2489e42c5caSLiam Girdwood { 2499e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 2509e42c5caSLiam Girdwood struct sof_ipc_reply reply; 2519e42c5caSLiam Girdwood int ret = 0; 2529e42c5caSLiam Girdwood 2539e42c5caSLiam Girdwood /* 2549e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 2559e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 2569e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 2579e42c5caSLiam Girdwood */ 2589e42c5caSLiam Girdwood if (!msg) { 2599e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 2609e42c5caSLiam Girdwood return; 2619e42c5caSLiam Girdwood } 2629e42c5caSLiam Girdwood 2639e42c5caSLiam Girdwood /* get reply */ 2649e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 2659e42c5caSLiam Girdwood 2669e42c5caSLiam Girdwood if (reply.error < 0) { 2679e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 2689e42c5caSLiam Girdwood ret = reply.error; 2699e42c5caSLiam Girdwood } else { 2709e42c5caSLiam Girdwood /* reply correct size ? */ 2719e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 2729e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 2739e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 2749e42c5caSLiam Girdwood ret = -EINVAL; 2759e42c5caSLiam Girdwood } 2769e42c5caSLiam Girdwood 2779e42c5caSLiam Girdwood /* read the message */ 2789e42c5caSLiam Girdwood if (msg->reply_size > 0) 2799e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 2809e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 2819e42c5caSLiam Girdwood } 2829e42c5caSLiam Girdwood 2839e42c5caSLiam Girdwood msg->reply_error = ret; 2849e42c5caSLiam Girdwood } 2859e42c5caSLiam Girdwood 28683ee7ab1SDaniel Baluta static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 28783ee7ab1SDaniel Baluta { 28883ee7ab1SDaniel Baluta return MBOX_OFFSET; 28983ee7ab1SDaniel Baluta } 29083ee7ab1SDaniel Baluta 29183ee7ab1SDaniel Baluta static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 29283ee7ab1SDaniel Baluta { 29383ee7ab1SDaniel Baluta return MBOX_OFFSET; 29483ee7ab1SDaniel Baluta } 29583ee7ab1SDaniel Baluta 2969e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev) 2979e42c5caSLiam Girdwood { 2989e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 2999e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 3009e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 3019e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 3029e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 3039e42c5caSLiam Girdwood 3049e42c5caSLiam Girdwood /* unmask busy interrupt */ 3059e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3069e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 3079e42c5caSLiam Girdwood } 3089e42c5caSLiam Girdwood 3099e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev) 3109e42c5caSLiam Girdwood { 3119e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 3129e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 3139e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 3149e42c5caSLiam Girdwood 3159e42c5caSLiam Girdwood /* unmask Done interrupt */ 3169e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3179e42c5caSLiam Girdwood SHIM_IMRX_DONE, 0); 3189e42c5caSLiam Girdwood } 3199e42c5caSLiam Girdwood 3209e42c5caSLiam Girdwood /* 3219e42c5caSLiam Girdwood * DSP control. 3229e42c5caSLiam Girdwood */ 3239e42c5caSLiam Girdwood 3249e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev) 3259e42c5caSLiam Girdwood { 3269e42c5caSLiam Girdwood int tries = 10; 3279e42c5caSLiam Girdwood 3289e42c5caSLiam Girdwood /* release stall and wait to unstall */ 3299e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3309e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 3319e42c5caSLiam Girdwood while (tries--) { 3329e42c5caSLiam Girdwood if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 3339e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 3349e42c5caSLiam Girdwood break; 3359e42c5caSLiam Girdwood msleep(100); 3369e42c5caSLiam Girdwood } 3379e42c5caSLiam Girdwood if (tries < 0) { 3389e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 3399e42c5caSLiam Girdwood byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 3409e42c5caSLiam Girdwood return -ENODEV; 3419e42c5caSLiam Girdwood } 3429e42c5caSLiam Girdwood 3439e42c5caSLiam Girdwood /* return init core mask */ 3449e42c5caSLiam Girdwood return 1; 3459e42c5caSLiam Girdwood } 3469e42c5caSLiam Girdwood 3479e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev) 3489e42c5caSLiam Girdwood { 3499e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 3509e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3519e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3529e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 3539e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3549e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 3559e42c5caSLiam Girdwood 3569e42c5caSLiam Girdwood usleep_range(10, 15); 3579e42c5caSLiam Girdwood 3589e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 3599e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3609e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 3619e42c5caSLiam Girdwood 3629e42c5caSLiam Girdwood return 0; 3639e42c5caSLiam Girdwood } 3649e42c5caSLiam Girdwood 3652aae447aSPierre-Louis Bossart static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 3662aae447aSPierre-Louis Bossart const char *sof_tplg_filename, 3672aae447aSPierre-Louis Bossart const char *ssp_str) 3682aae447aSPierre-Louis Bossart { 3692aae447aSPierre-Louis Bossart const char *tplg_filename = NULL; 3702aae447aSPierre-Louis Bossart char *filename; 3712aae447aSPierre-Louis Bossart char *split_ext; 3722aae447aSPierre-Louis Bossart 3732aae447aSPierre-Louis Bossart filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 3742aae447aSPierre-Louis Bossart if (!filename) 3752aae447aSPierre-Louis Bossart return NULL; 3762aae447aSPierre-Louis Bossart 3772aae447aSPierre-Louis Bossart /* this assumes a .tplg extension */ 3782aae447aSPierre-Louis Bossart split_ext = strsep(&filename, "."); 3792aae447aSPierre-Louis Bossart if (split_ext) { 3802aae447aSPierre-Louis Bossart tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 3812aae447aSPierre-Louis Bossart "%s-%s.tplg", 3822aae447aSPierre-Louis Bossart split_ext, ssp_str); 3832aae447aSPierre-Louis Bossart if (!tplg_filename) 3842aae447aSPierre-Louis Bossart return NULL; 3852aae447aSPierre-Louis Bossart } 3862aae447aSPierre-Louis Bossart return tplg_filename; 3872aae447aSPierre-Louis Bossart } 3882aae447aSPierre-Louis Bossart 389285880a2SDaniel Baluta static void byt_machine_select(struct snd_sof_dev *sdev) 390285880a2SDaniel Baluta { 391285880a2SDaniel Baluta struct snd_sof_pdata *sof_pdata = sdev->pdata; 392285880a2SDaniel Baluta const struct sof_dev_desc *desc = sof_pdata->desc; 393285880a2SDaniel Baluta struct snd_soc_acpi_mach *mach; 3942aae447aSPierre-Louis Bossart struct platform_device *pdev; 3952aae447aSPierre-Louis Bossart const char *tplg_filename; 396285880a2SDaniel Baluta 397285880a2SDaniel Baluta mach = snd_soc_acpi_find_machine(desc->machines); 398285880a2SDaniel Baluta if (!mach) { 399285880a2SDaniel Baluta dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 400285880a2SDaniel Baluta return; 401285880a2SDaniel Baluta } 402285880a2SDaniel Baluta 4032aae447aSPierre-Louis Bossart pdev = to_platform_device(sdev->dev); 4042aae447aSPierre-Louis Bossart if (soc_intel_is_byt_cr(pdev)) { 4052aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4062aae447aSPierre-Louis Bossart "BYT-CR detected, SSP0 used instead of SSP2\n"); 4072aae447aSPierre-Louis Bossart 4082aae447aSPierre-Louis Bossart tplg_filename = fixup_tplg_name(sdev, 4092aae447aSPierre-Louis Bossart mach->sof_tplg_filename, 4102aae447aSPierre-Louis Bossart "ssp0"); 4112aae447aSPierre-Louis Bossart } else { 4122aae447aSPierre-Louis Bossart tplg_filename = mach->sof_tplg_filename; 4132aae447aSPierre-Louis Bossart } 4142aae447aSPierre-Louis Bossart 4152aae447aSPierre-Louis Bossart if (!tplg_filename) { 4162aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4172aae447aSPierre-Louis Bossart "error: no topology filename\n"); 4182aae447aSPierre-Louis Bossart return; 4192aae447aSPierre-Louis Bossart } 4202aae447aSPierre-Louis Bossart 4212aae447aSPierre-Louis Bossart sof_pdata->tplg_filename = tplg_filename; 422285880a2SDaniel Baluta mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 423285880a2SDaniel Baluta sof_pdata->machine = mach; 424285880a2SDaniel Baluta } 425285880a2SDaniel Baluta 426285880a2SDaniel Baluta static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 427285880a2SDaniel Baluta struct device *dev) 428285880a2SDaniel Baluta { 429285880a2SDaniel Baluta struct snd_soc_acpi_mach_params *mach_params; 430285880a2SDaniel Baluta 431285880a2SDaniel Baluta mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 432285880a2SDaniel Baluta mach_params->platform = dev_name(dev); 433285880a2SDaniel Baluta } 434285880a2SDaniel Baluta 435ddcccd54SRanjani Sridharan static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 436ddcccd54SRanjani Sridharan { 437ddcccd54SRanjani Sridharan /* Disable Interrupt from both sides */ 438ddcccd54SRanjani Sridharan snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 439ddcccd54SRanjani Sridharan snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 440ddcccd54SRanjani Sridharan 441ddcccd54SRanjani Sridharan /* Put DSP into reset, set reset vector */ 442ddcccd54SRanjani Sridharan snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 443ddcccd54SRanjani Sridharan SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 444ddcccd54SRanjani Sridharan SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 445ddcccd54SRanjani Sridharan } 446ddcccd54SRanjani Sridharan 447ddcccd54SRanjani Sridharan static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 448ddcccd54SRanjani Sridharan { 449ddcccd54SRanjani Sridharan byt_reset_dsp_disable_int(sdev); 450ddcccd54SRanjani Sridharan 451ddcccd54SRanjani Sridharan return 0; 452ddcccd54SRanjani Sridharan } 453ddcccd54SRanjani Sridharan 454ddcccd54SRanjani Sridharan static int byt_resume(struct snd_sof_dev *sdev) 455ddcccd54SRanjani Sridharan { 456ddcccd54SRanjani Sridharan /* Enable Interrupt from both sides */ 457ddcccd54SRanjani Sridharan snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 458ddcccd54SRanjani Sridharan snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 459ddcccd54SRanjani Sridharan 460ddcccd54SRanjani Sridharan return 0; 461ddcccd54SRanjani Sridharan } 462ddcccd54SRanjani Sridharan 463c691f0c6SRanjani Sridharan static int byt_remove(struct snd_sof_dev *sdev) 464c691f0c6SRanjani Sridharan { 465c691f0c6SRanjani Sridharan byt_reset_dsp_disable_int(sdev); 466c691f0c6SRanjani Sridharan 467c691f0c6SRanjani Sridharan return 0; 468c691f0c6SRanjani Sridharan } 469c691f0c6SRanjani Sridharan 4709e42c5caSLiam Girdwood /* Baytrail DAIs */ 4719e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = { 4729e42c5caSLiam Girdwood { 4739e42c5caSLiam Girdwood .name = "ssp0-port", 4748c05246cSPierre-Louis Bossart .playback = { 4758c05246cSPierre-Louis Bossart .channels_min = 1, 4768c05246cSPierre-Louis Bossart .channels_max = 8, 4778c05246cSPierre-Louis Bossart }, 4788c05246cSPierre-Louis Bossart .capture = { 4798c05246cSPierre-Louis Bossart .channels_min = 1, 4808c05246cSPierre-Louis Bossart .channels_max = 8, 4818c05246cSPierre-Louis Bossart }, 4829e42c5caSLiam Girdwood }, 4839e42c5caSLiam Girdwood { 4849e42c5caSLiam Girdwood .name = "ssp1-port", 4858c05246cSPierre-Louis Bossart .playback = { 4868c05246cSPierre-Louis Bossart .channels_min = 1, 4878c05246cSPierre-Louis Bossart .channels_max = 8, 4888c05246cSPierre-Louis Bossart }, 4898c05246cSPierre-Louis Bossart .capture = { 4908c05246cSPierre-Louis Bossart .channels_min = 1, 4918c05246cSPierre-Louis Bossart .channels_max = 8, 4928c05246cSPierre-Louis Bossart }, 4939e42c5caSLiam Girdwood }, 4949e42c5caSLiam Girdwood { 4959e42c5caSLiam Girdwood .name = "ssp2-port", 4968c05246cSPierre-Louis Bossart .playback = { 4978c05246cSPierre-Louis Bossart .channels_min = 1, 4988c05246cSPierre-Louis Bossart .channels_max = 8, 4998c05246cSPierre-Louis Bossart }, 5008c05246cSPierre-Louis Bossart .capture = { 5018c05246cSPierre-Louis Bossart .channels_min = 1, 5028c05246cSPierre-Louis Bossart .channels_max = 8, 5038c05246cSPierre-Louis Bossart } 5049e42c5caSLiam Girdwood }, 5059e42c5caSLiam Girdwood { 5069e42c5caSLiam Girdwood .name = "ssp3-port", 5078c05246cSPierre-Louis Bossart .playback = { 5088c05246cSPierre-Louis Bossart .channels_min = 1, 5098c05246cSPierre-Louis Bossart .channels_max = 8, 5108c05246cSPierre-Louis Bossart }, 5118c05246cSPierre-Louis Bossart .capture = { 5128c05246cSPierre-Louis Bossart .channels_min = 1, 5138c05246cSPierre-Louis Bossart .channels_max = 8, 5148c05246cSPierre-Louis Bossart }, 5159e42c5caSLiam Girdwood }, 5169e42c5caSLiam Girdwood { 5179e42c5caSLiam Girdwood .name = "ssp4-port", 5188c05246cSPierre-Louis Bossart .playback = { 5198c05246cSPierre-Louis Bossart .channels_min = 1, 5208c05246cSPierre-Louis Bossart .channels_max = 8, 5218c05246cSPierre-Louis Bossart }, 5228c05246cSPierre-Louis Bossart .capture = { 5238c05246cSPierre-Louis Bossart .channels_min = 1, 5248c05246cSPierre-Louis Bossart .channels_max = 8, 5258c05246cSPierre-Louis Bossart }, 5269e42c5caSLiam Girdwood }, 5279e42c5caSLiam Girdwood { 5289e42c5caSLiam Girdwood .name = "ssp5-port", 5298c05246cSPierre-Louis Bossart .playback = { 5308c05246cSPierre-Louis Bossart .channels_min = 1, 5318c05246cSPierre-Louis Bossart .channels_max = 8, 5328c05246cSPierre-Louis Bossart }, 5338c05246cSPierre-Louis Bossart .capture = { 5348c05246cSPierre-Louis Bossart .channels_min = 1, 5358c05246cSPierre-Louis Bossart .channels_max = 8, 5368c05246cSPierre-Louis Bossart }, 5379e42c5caSLiam Girdwood }, 5389e42c5caSLiam Girdwood }; 5399e42c5caSLiam Girdwood 5409e42c5caSLiam Girdwood /* 5419e42c5caSLiam Girdwood * Probe and remove. 5429e42c5caSLiam Girdwood */ 5439e42c5caSLiam Girdwood 5449e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 5459e42c5caSLiam Girdwood 5469e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 5479e42c5caSLiam Girdwood { 5489e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5499e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5509e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 5519e42c5caSLiam Girdwood u32 base, size; 5529e42c5caSLiam Girdwood int ret; 5539e42c5caSLiam Girdwood 5549e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5559e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 5569e42c5caSLiam Girdwood if (ret < 0) { 5579e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5589e42c5caSLiam Girdwood return ret; 5599e42c5caSLiam Girdwood } 5609e42c5caSLiam Girdwood 5619e42c5caSLiam Girdwood /* LPE base */ 5629e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 5639e42c5caSLiam Girdwood size = BYT_PCI_BAR_SIZE; 5649e42c5caSLiam Girdwood 5659e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 5669e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 5679e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 5689e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5699e42c5caSLiam Girdwood base, size); 5709e42c5caSLiam Girdwood return -ENODEV; 5719e42c5caSLiam Girdwood } 5729e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 5739e42c5caSLiam Girdwood 5749e42c5caSLiam Girdwood /* IMR base - optional */ 5759e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5769e42c5caSLiam Girdwood goto irq; 5779e42c5caSLiam Girdwood 5789e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 5799e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 5809e42c5caSLiam Girdwood 5819e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 5829e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 5839e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 5849e42c5caSLiam Girdwood goto irq; 5859e42c5caSLiam Girdwood } 5869e42c5caSLiam Girdwood 5879e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 5889e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 5899e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 5909e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 5919e42c5caSLiam Girdwood base, size); 5929e42c5caSLiam Girdwood return -ENODEV; 5939e42c5caSLiam Girdwood } 5949e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 5959e42c5caSLiam Girdwood 5969e42c5caSLiam Girdwood irq: 5979e42c5caSLiam Girdwood /* register our IRQ */ 5989e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 5999e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 6009e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 6019e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 6029e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 6039e42c5caSLiam Girdwood if (ret < 0) { 6049e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 6059e42c5caSLiam Girdwood sdev->ipc_irq); 6069e42c5caSLiam Girdwood return ret; 6079e42c5caSLiam Girdwood } 6089e42c5caSLiam Girdwood 6099e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 6109e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 6119e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 6129e42c5caSLiam Girdwood 6139e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 6149e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 6159e42c5caSLiam Girdwood 6169e42c5caSLiam Girdwood return ret; 6179e42c5caSLiam Girdwood } 6189e42c5caSLiam Girdwood 6199e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 6209e42c5caSLiam Girdwood /* device init */ 6219e42c5caSLiam Girdwood .probe = tangier_pci_probe, 6229e42c5caSLiam Girdwood 6239e42c5caSLiam Girdwood /* DSP core boot / reset */ 6249e42c5caSLiam Girdwood .run = byt_run, 6259e42c5caSLiam Girdwood .reset = byt_reset, 6269e42c5caSLiam Girdwood 6279e42c5caSLiam Girdwood /* Register IO */ 6289e42c5caSLiam Girdwood .write = sof_io_write, 6299e42c5caSLiam Girdwood .read = sof_io_read, 6309e42c5caSLiam Girdwood .write64 = sof_io_write64, 6319e42c5caSLiam Girdwood .read64 = sof_io_read64, 6329e42c5caSLiam Girdwood 6339e42c5caSLiam Girdwood /* Block IO */ 6349e42c5caSLiam Girdwood .block_read = sof_block_read, 6359e42c5caSLiam Girdwood .block_write = sof_block_write, 6369e42c5caSLiam Girdwood 6379e42c5caSLiam Girdwood /* doorbell */ 6389e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 6399e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 6409e42c5caSLiam Girdwood 6419e42c5caSLiam Girdwood /* ipc */ 6429e42c5caSLiam Girdwood .send_msg = byt_send_msg, 64383ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 64483ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 64583ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 6469e42c5caSLiam Girdwood 6479e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6489e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6499e42c5caSLiam Girdwood 650285880a2SDaniel Baluta /* machine driver */ 651285880a2SDaniel Baluta .machine_select = byt_machine_select, 652285880a2SDaniel Baluta .machine_register = sof_machine_register, 653285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 654285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 655285880a2SDaniel Baluta 6569e42c5caSLiam Girdwood /* debug */ 6579e42c5caSLiam Girdwood .debug_map = byt_debugfs, 6589e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 6599e42c5caSLiam Girdwood .dbg_dump = byt_dump, 6609e42c5caSLiam Girdwood 6619e42c5caSLiam Girdwood /* stream callbacks */ 6629e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6639e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6649e42c5caSLiam Girdwood 6659e42c5caSLiam Girdwood /* module loading */ 6669e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6679e42c5caSLiam Girdwood 6689e42c5caSLiam Girdwood /*Firmware loading */ 6699e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6709e42c5caSLiam Girdwood 6719e42c5caSLiam Girdwood /* DAI drivers */ 6729e42c5caSLiam Girdwood .drv = byt_dai, 6739e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 67427e322faSPierre-Louis Bossart 67527e322faSPierre-Louis Bossart /* ALSA HW info flags */ 67627e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 67727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 67827e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 67927e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 6804c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 6810f501c7cSPierre-Louis Bossart 6820f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 6839e42c5caSLiam Girdwood }; 684e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 6859e42c5caSLiam Girdwood 6869e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 6879e42c5caSLiam Girdwood .cores_num = 1, 6889e42c5caSLiam Girdwood .cores_mask = 1, 6899e42c5caSLiam Girdwood }; 690e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 6919e42c5caSLiam Girdwood 6929e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 6939e42c5caSLiam Girdwood 6949e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 6959e42c5caSLiam Girdwood 69628d4adc4SYueHaibing static const struct snd_sof_debugfs_map cht_debugfs[] = { 69728d4adc4SYueHaibing {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 69828d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 69928d4adc4SYueHaibing {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 70028d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70128d4adc4SYueHaibing {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 70228d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70328d4adc4SYueHaibing {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 70428d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70528d4adc4SYueHaibing {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 70628d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70728d4adc4SYueHaibing {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 70828d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 70928d4adc4SYueHaibing {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 71028d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71128d4adc4SYueHaibing {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 71228d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71328d4adc4SYueHaibing {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 71428d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 71528d4adc4SYueHaibing {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 71628d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 71728d4adc4SYueHaibing {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 71828d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 71928d4adc4SYueHaibing {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 72028d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 72128d4adc4SYueHaibing }; 72228d4adc4SYueHaibing 7239e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 7249e42c5caSLiam Girdwood { 7259e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 7269e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 7279e42c5caSLiam Girdwood struct platform_device *pdev = 7289e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 7299e42c5caSLiam Girdwood struct resource *mmio; 7309e42c5caSLiam Girdwood u32 base, size; 7319e42c5caSLiam Girdwood int ret; 7329e42c5caSLiam Girdwood 7339e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 7349e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 7359e42c5caSLiam Girdwood if (ret < 0) { 7369e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 7379e42c5caSLiam Girdwood return ret; 7389e42c5caSLiam Girdwood } 7399e42c5caSLiam Girdwood 7409e42c5caSLiam Girdwood /* LPE base */ 7419e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7429e42c5caSLiam Girdwood desc->resindex_lpe_base); 7439e42c5caSLiam Girdwood if (mmio) { 7449e42c5caSLiam Girdwood base = mmio->start; 7459e42c5caSLiam Girdwood size = resource_size(mmio); 7469e42c5caSLiam Girdwood } else { 7479e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 7489e42c5caSLiam Girdwood desc->resindex_lpe_base); 7499e42c5caSLiam Girdwood return -EINVAL; 7509e42c5caSLiam Girdwood } 7519e42c5caSLiam Girdwood 7529e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 7539e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 7549e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 7559e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 7569e42c5caSLiam Girdwood base, size); 7579e42c5caSLiam Girdwood return -ENODEV; 7589e42c5caSLiam Girdwood } 7599e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 7609e42c5caSLiam Girdwood 7619e42c5caSLiam Girdwood /* TODO: add offsets */ 7629e42c5caSLiam Girdwood sdev->mmio_bar = BYT_DSP_BAR; 7639e42c5caSLiam Girdwood sdev->mailbox_bar = BYT_DSP_BAR; 7649e42c5caSLiam Girdwood 7659e42c5caSLiam Girdwood /* IMR base - optional */ 7669e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 7679e42c5caSLiam Girdwood goto irq; 7689e42c5caSLiam Girdwood 7699e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7709e42c5caSLiam Girdwood desc->resindex_imr_base); 7719e42c5caSLiam Girdwood if (mmio) { 7729e42c5caSLiam Girdwood base = mmio->start; 7739e42c5caSLiam Girdwood size = resource_size(mmio); 7749e42c5caSLiam Girdwood } else { 7759e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 7769e42c5caSLiam Girdwood desc->resindex_imr_base); 7779e42c5caSLiam Girdwood return -ENODEV; 7789e42c5caSLiam Girdwood } 7799e42c5caSLiam Girdwood 7809e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 7819e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 7829e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 7839e42c5caSLiam Girdwood goto irq; 7849e42c5caSLiam Girdwood } 7859e42c5caSLiam Girdwood 7869e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 7879e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 7889e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 7899e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 7909e42c5caSLiam Girdwood base, size); 7919e42c5caSLiam Girdwood return -ENODEV; 7929e42c5caSLiam Girdwood } 7939e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 7949e42c5caSLiam Girdwood 7959e42c5caSLiam Girdwood irq: 7969e42c5caSLiam Girdwood /* register our IRQ */ 7979e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 798cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 7999e42c5caSLiam Girdwood return sdev->ipc_irq; 8009e42c5caSLiam Girdwood 8019e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 8029e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 8039e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 8049e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 8059e42c5caSLiam Girdwood if (ret < 0) { 8069e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 8079e42c5caSLiam Girdwood sdev->ipc_irq); 8089e42c5caSLiam Girdwood return ret; 8099e42c5caSLiam Girdwood } 8109e42c5caSLiam Girdwood 8119e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 8129e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 8139e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 8149e42c5caSLiam Girdwood 8159e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 8169e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 8179e42c5caSLiam Girdwood 8189e42c5caSLiam Girdwood return ret; 8199e42c5caSLiam Girdwood } 8209e42c5caSLiam Girdwood 8219e42c5caSLiam Girdwood /* baytrail ops */ 8229e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_byt_ops = { 8239e42c5caSLiam Girdwood /* device init */ 8249e42c5caSLiam Girdwood .probe = byt_acpi_probe, 825c691f0c6SRanjani Sridharan .remove = byt_remove, 8269e42c5caSLiam Girdwood 8279e42c5caSLiam Girdwood /* DSP core boot / reset */ 8289e42c5caSLiam Girdwood .run = byt_run, 8299e42c5caSLiam Girdwood .reset = byt_reset, 8309e42c5caSLiam Girdwood 8319e42c5caSLiam Girdwood /* Register IO */ 8329e42c5caSLiam Girdwood .write = sof_io_write, 8339e42c5caSLiam Girdwood .read = sof_io_read, 8349e42c5caSLiam Girdwood .write64 = sof_io_write64, 8359e42c5caSLiam Girdwood .read64 = sof_io_read64, 8369e42c5caSLiam Girdwood 8379e42c5caSLiam Girdwood /* Block IO */ 8389e42c5caSLiam Girdwood .block_read = sof_block_read, 8399e42c5caSLiam Girdwood .block_write = sof_block_write, 8409e42c5caSLiam Girdwood 8419e42c5caSLiam Girdwood /* doorbell */ 8429e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 8439e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 8449e42c5caSLiam Girdwood 8459e42c5caSLiam Girdwood /* ipc */ 8469e42c5caSLiam Girdwood .send_msg = byt_send_msg, 84783ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 84883ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 84983ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 8509e42c5caSLiam Girdwood 8519e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8529e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8539e42c5caSLiam Girdwood 854285880a2SDaniel Baluta /* machine driver */ 855285880a2SDaniel Baluta .machine_select = byt_machine_select, 856285880a2SDaniel Baluta .machine_register = sof_machine_register, 857285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 858285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 859285880a2SDaniel Baluta 8609e42c5caSLiam Girdwood /* debug */ 8619e42c5caSLiam Girdwood .debug_map = byt_debugfs, 8629e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 8639e42c5caSLiam Girdwood .dbg_dump = byt_dump, 8649e42c5caSLiam Girdwood 8659e42c5caSLiam Girdwood /* stream callbacks */ 8669e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 8679e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 8689e42c5caSLiam Girdwood 8699e42c5caSLiam Girdwood /* module loading */ 8709e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 8719e42c5caSLiam Girdwood 8729e42c5caSLiam Girdwood /*Firmware loading */ 8739e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 8749e42c5caSLiam Girdwood 875ddcccd54SRanjani Sridharan /* PM */ 876ddcccd54SRanjani Sridharan .suspend = byt_suspend, 877ddcccd54SRanjani Sridharan .resume = byt_resume, 878ddcccd54SRanjani Sridharan 8799e42c5caSLiam Girdwood /* DAI drivers */ 8809e42c5caSLiam Girdwood .drv = byt_dai, 8819e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 88227e322faSPierre-Louis Bossart 88327e322faSPierre-Louis Bossart /* ALSA HW info flags */ 88427e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 88527e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 88627e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 88727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 8884c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 8890f501c7cSPierre-Louis Bossart 8900f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 8919e42c5caSLiam Girdwood }; 892e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); 8939e42c5caSLiam Girdwood 8949e42c5caSLiam Girdwood const struct sof_intel_dsp_desc byt_chip_info = { 8959e42c5caSLiam Girdwood .cores_num = 1, 8969e42c5caSLiam Girdwood .cores_mask = 1, 8979e42c5caSLiam Girdwood }; 898e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); 8999e42c5caSLiam Girdwood 9009e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 9019e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_cht_ops = { 9029e42c5caSLiam Girdwood /* device init */ 9039e42c5caSLiam Girdwood .probe = byt_acpi_probe, 904c691f0c6SRanjani Sridharan .remove = byt_remove, 9059e42c5caSLiam Girdwood 9069e42c5caSLiam Girdwood /* DSP core boot / reset */ 9079e42c5caSLiam Girdwood .run = byt_run, 9089e42c5caSLiam Girdwood .reset = byt_reset, 9099e42c5caSLiam Girdwood 9109e42c5caSLiam Girdwood /* Register IO */ 9119e42c5caSLiam Girdwood .write = sof_io_write, 9129e42c5caSLiam Girdwood .read = sof_io_read, 9139e42c5caSLiam Girdwood .write64 = sof_io_write64, 9149e42c5caSLiam Girdwood .read64 = sof_io_read64, 9159e42c5caSLiam Girdwood 9169e42c5caSLiam Girdwood /* Block IO */ 9179e42c5caSLiam Girdwood .block_read = sof_block_read, 9189e42c5caSLiam Girdwood .block_write = sof_block_write, 9199e42c5caSLiam Girdwood 9209e42c5caSLiam Girdwood /* doorbell */ 9219e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 9229e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 9239e42c5caSLiam Girdwood 9249e42c5caSLiam Girdwood /* ipc */ 9259e42c5caSLiam Girdwood .send_msg = byt_send_msg, 92683ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 92783ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 92883ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 9299e42c5caSLiam Girdwood 9309e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 9319e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 9329e42c5caSLiam Girdwood 933285880a2SDaniel Baluta /* machine driver */ 934285880a2SDaniel Baluta .machine_select = byt_machine_select, 935285880a2SDaniel Baluta .machine_register = sof_machine_register, 936285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 937285880a2SDaniel Baluta .set_mach_params = byt_set_mach_params, 938285880a2SDaniel Baluta 9399e42c5caSLiam Girdwood /* debug */ 9409e42c5caSLiam Girdwood .debug_map = cht_debugfs, 9419e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 9429e42c5caSLiam Girdwood .dbg_dump = byt_dump, 9439e42c5caSLiam Girdwood 9449e42c5caSLiam Girdwood /* stream callbacks */ 9459e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 9469e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 9479e42c5caSLiam Girdwood 9489e42c5caSLiam Girdwood /* module loading */ 9499e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 9509e42c5caSLiam Girdwood 9519e42c5caSLiam Girdwood /*Firmware loading */ 9529e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 9539e42c5caSLiam Girdwood 954ddcccd54SRanjani Sridharan /* PM */ 955ddcccd54SRanjani Sridharan .suspend = byt_suspend, 956ddcccd54SRanjani Sridharan .resume = byt_resume, 957ddcccd54SRanjani Sridharan 9589e42c5caSLiam Girdwood /* DAI drivers */ 9599e42c5caSLiam Girdwood .drv = byt_dai, 9609e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 9619e42c5caSLiam Girdwood .num_drv = ARRAY_SIZE(byt_dai), 96227e322faSPierre-Louis Bossart 96327e322faSPierre-Louis Bossart /* ALSA HW info flags */ 96427e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 96527e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 96627e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 96727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 9684c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 9690f501c7cSPierre-Louis Bossart 9700f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 9719e42c5caSLiam Girdwood }; 972e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); 9739e42c5caSLiam Girdwood 9749e42c5caSLiam Girdwood const struct sof_intel_dsp_desc cht_chip_info = { 9759e42c5caSLiam Girdwood .cores_num = 1, 9769e42c5caSLiam Girdwood .cores_mask = 1, 9779e42c5caSLiam Girdwood }; 978e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); 9799e42c5caSLiam Girdwood 9809e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 9819e42c5caSLiam Girdwood 9829e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 983f4483a0fSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 984068ac0dbSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 985