19e42c5caSLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 189e42c5caSLiam Girdwood #include "../ops.h" 199e42c5caSLiam Girdwood #include "shim.h" 209e42c5caSLiam Girdwood 219e42c5caSLiam Girdwood /* DSP memories */ 229e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 239e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 249e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 259e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 269e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 279e42c5caSLiam Girdwood #define SHIM_SIZE 0x100 289e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 299e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 309e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 319e42c5caSLiam Girdwood 329e42c5caSLiam Girdwood /* DSP peripherals */ 339e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 349e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 359e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 369e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 379e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 389e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 399e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 409e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 419e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 429e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 439e42c5caSLiam Girdwood #define SSP_SIZE 0x100 449e42c5caSLiam Girdwood 459e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE 32 469e42c5caSLiam Girdwood 479e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE 0x200000 489e42c5caSLiam Girdwood 499e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 509e42c5caSLiam Girdwood 519e42c5caSLiam Girdwood /* 529e42c5caSLiam Girdwood * Debug 539e42c5caSLiam Girdwood */ 549e42c5caSLiam Girdwood 559e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 569e42c5caSLiam Girdwood 579e42c5caSLiam Girdwood /* BARs */ 589e42c5caSLiam Girdwood #define BYT_DSP_BAR 0 599e42c5caSLiam Girdwood #define BYT_PCI_BAR 1 609e42c5caSLiam Girdwood #define BYT_IMR_BAR 2 619e42c5caSLiam Girdwood 629e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 639e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 649e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 659e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 669e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 679e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 689e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 699e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 709e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 719e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 739e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 759e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 779e42c5caSLiam Girdwood {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 799e42c5caSLiam Girdwood }; 809e42c5caSLiam Girdwood 819e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map cht_debugfs[] = { 829e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 839e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 849e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 859e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 869e42c5caSLiam Girdwood {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 879e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 889e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 899e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 909e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 919e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 929e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 939e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 949e42c5caSLiam Girdwood {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 959e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 969e42c5caSLiam Girdwood {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 979e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 989e42c5caSLiam Girdwood {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 999e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1009e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 1019e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 1029e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 1039e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 1049e42c5caSLiam Girdwood {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 1059e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1069e42c5caSLiam Girdwood }; 1079e42c5caSLiam Girdwood 1089e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev); 1099e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev); 1109e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev); 1119e42c5caSLiam Girdwood 1129e42c5caSLiam Girdwood /* 1139e42c5caSLiam Girdwood * Debug 1149e42c5caSLiam Girdwood */ 1159e42c5caSLiam Girdwood 1169e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev, 1179e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 1189e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 1199e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 1209e42c5caSLiam Girdwood { 12114104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 12214104eb6SKai Vehmanen 1239e42c5caSLiam Girdwood /* first read regsisters */ 12414104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 12514104eb6SKai Vehmanen 12614104eb6SKai Vehmanen /* note: variable AR register array is not read */ 1279e42c5caSLiam Girdwood 1289e42c5caSLiam Girdwood /* then get panic info */ 12914104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 13014104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 1319e42c5caSLiam Girdwood 1329e42c5caSLiam Girdwood /* then get the stack */ 13314104eb6SKai Vehmanen offset += sizeof(*panic_info); 13414104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 1359e42c5caSLiam Girdwood } 1369e42c5caSLiam Girdwood 1379e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 1389e42c5caSLiam Girdwood { 1399e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 1409e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 1419e42c5caSLiam Girdwood u32 stack[BYT_STACK_DUMP_SIZE]; 1423a9e204dSLiam Girdwood u32 status, panic, imrd, imrx; 1439e42c5caSLiam Girdwood 1449e42c5caSLiam Girdwood /* now try generic SOF status messages */ 1459e42c5caSLiam Girdwood status = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCD); 1469e42c5caSLiam Girdwood panic = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCX); 1479e42c5caSLiam Girdwood byt_get_registers(sdev, &xoops, &panic_info, stack, 1489e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1499e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 1509e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 1513a9e204dSLiam Girdwood 1523a9e204dSLiam Girdwood /* provide some context for firmware debug */ 1533a9e204dSLiam Girdwood imrx = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IMRX); 1543a9e204dSLiam Girdwood imrd = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IMRD); 1553a9e204dSLiam Girdwood dev_err(sdev->dev, 1563a9e204dSLiam Girdwood "error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n", 1573a9e204dSLiam Girdwood panic & SHIM_IPCX_BUSY ? "yes" : "no", 1583a9e204dSLiam Girdwood panic & SHIM_IPCX_DONE ? "yes" : "no", panic); 1593a9e204dSLiam Girdwood dev_err(sdev->dev, 1603a9e204dSLiam Girdwood "error: mask host: pending %s complete %s raw 0x%8.8x\n", 1613a9e204dSLiam Girdwood imrx & SHIM_IMRX_BUSY ? "yes" : "no", 1623a9e204dSLiam Girdwood imrx & SHIM_IMRX_DONE ? "yes" : "no", imrx); 1633a9e204dSLiam Girdwood dev_err(sdev->dev, 1643a9e204dSLiam Girdwood "error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n", 1653a9e204dSLiam Girdwood status & SHIM_IPCD_BUSY ? "yes" : "no", 1663a9e204dSLiam Girdwood status & SHIM_IPCD_DONE ? "yes" : "no", status); 1673a9e204dSLiam Girdwood dev_err(sdev->dev, 1683a9e204dSLiam Girdwood "error: mask DSP: pending %s complete %s raw 0x%8.8x\n", 1693a9e204dSLiam Girdwood imrd & SHIM_IMRD_BUSY ? "yes" : "no", 1703a9e204dSLiam Girdwood imrd & SHIM_IMRD_DONE ? "yes" : "no", imrd); 1713a9e204dSLiam Girdwood 1729e42c5caSLiam Girdwood } 1739e42c5caSLiam Girdwood 1749e42c5caSLiam Girdwood /* 1759e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 1769e42c5caSLiam Girdwood */ 1779e42c5caSLiam Girdwood 1789e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context) 1799e42c5caSLiam Girdwood { 1809e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1819e42c5caSLiam Girdwood u64 isr; 1829e42c5caSLiam Girdwood int ret = IRQ_NONE; 1839e42c5caSLiam Girdwood 1849e42c5caSLiam Girdwood /* Interrupt arrived, check src */ 1859e42c5caSLiam Girdwood isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX); 1869e42c5caSLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 1879e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 1889e42c5caSLiam Girdwood 1899e42c5caSLiam Girdwood return ret; 1909e42c5caSLiam Girdwood } 1919e42c5caSLiam Girdwood 1929e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context) 1939e42c5caSLiam Girdwood { 1949e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1959e42c5caSLiam Girdwood u64 ipcx, ipcd; 1969e42c5caSLiam Girdwood u64 imrx; 1979e42c5caSLiam Girdwood 1989e42c5caSLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 1999e42c5caSLiam Girdwood ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 2009e42c5caSLiam Girdwood 2019e42c5caSLiam Girdwood /* reply message from DSP */ 2029e42c5caSLiam Girdwood if (ipcx & SHIM_BYT_IPCX_DONE && 2039e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 2049e42c5caSLiam Girdwood /* Mask Done interrupt before first */ 2059e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 2069e42c5caSLiam Girdwood SHIM_IMRX, 2079e42c5caSLiam Girdwood SHIM_IMRX_DONE, 2089e42c5caSLiam Girdwood SHIM_IMRX_DONE); 2091183e9a6SGuennadi Liakhovetski 2101183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2111183e9a6SGuennadi Liakhovetski 2129e42c5caSLiam Girdwood /* 2139e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 2149e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 2159e42c5caSLiam Girdwood * end of message processing function, else set it here 2169e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 2179e42c5caSLiam Girdwood * which is triggered by msg 2189e42c5caSLiam Girdwood */ 2199e42c5caSLiam Girdwood byt_get_reply(sdev); 2209e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 2219e42c5caSLiam Girdwood 2229e42c5caSLiam Girdwood byt_dsp_done(sdev); 2231183e9a6SGuennadi Liakhovetski 2241183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 2259e42c5caSLiam Girdwood } 2269e42c5caSLiam Girdwood 2279e42c5caSLiam Girdwood /* new message from DSP */ 2289e42c5caSLiam Girdwood ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 2299e42c5caSLiam Girdwood if (ipcd & SHIM_BYT_IPCD_BUSY && 2309e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 2319e42c5caSLiam Girdwood /* Mask Busy interrupt before return */ 2329e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 2339e42c5caSLiam Girdwood SHIM_IMRX, 2349e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 2359e42c5caSLiam Girdwood SHIM_IMRX_BUSY); 2369e42c5caSLiam Girdwood 2379e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 2389e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 2399e42c5caSLiam Girdwood snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 2409e42c5caSLiam Girdwood MBOX_OFFSET); 2419e42c5caSLiam Girdwood } else { 2429e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 2439e42c5caSLiam Girdwood } 2449e42c5caSLiam Girdwood 2459e42c5caSLiam Girdwood byt_host_done(sdev); 2469e42c5caSLiam Girdwood } 2479e42c5caSLiam Girdwood 2489e42c5caSLiam Girdwood return IRQ_HANDLED; 2499e42c5caSLiam Girdwood } 2509e42c5caSLiam Girdwood 2519e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 2529e42c5caSLiam Girdwood { 2539e42c5caSLiam Girdwood /* send the message */ 2549e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 2559e42c5caSLiam Girdwood msg->msg_size); 2566fbbc18eSDaniel Baluta snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 2579e42c5caSLiam Girdwood 2589e42c5caSLiam Girdwood return 0; 2599e42c5caSLiam Girdwood } 2609e42c5caSLiam Girdwood 2619e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev) 2629e42c5caSLiam Girdwood { 2639e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 2649e42c5caSLiam Girdwood struct sof_ipc_reply reply; 2659e42c5caSLiam Girdwood int ret = 0; 2669e42c5caSLiam Girdwood 2679e42c5caSLiam Girdwood /* 2689e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 2699e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 2709e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 2719e42c5caSLiam Girdwood */ 2729e42c5caSLiam Girdwood if (!msg) { 2739e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 2749e42c5caSLiam Girdwood return; 2759e42c5caSLiam Girdwood } 2769e42c5caSLiam Girdwood 2779e42c5caSLiam Girdwood /* get reply */ 2789e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 2799e42c5caSLiam Girdwood 2809e42c5caSLiam Girdwood if (reply.error < 0) { 2819e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 2829e42c5caSLiam Girdwood ret = reply.error; 2839e42c5caSLiam Girdwood } else { 2849e42c5caSLiam Girdwood /* reply correct size ? */ 2859e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 2869e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 2879e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 2889e42c5caSLiam Girdwood ret = -EINVAL; 2899e42c5caSLiam Girdwood } 2909e42c5caSLiam Girdwood 2919e42c5caSLiam Girdwood /* read the message */ 2929e42c5caSLiam Girdwood if (msg->reply_size > 0) 2939e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 2949e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 2959e42c5caSLiam Girdwood } 2969e42c5caSLiam Girdwood 2979e42c5caSLiam Girdwood msg->reply_error = ret; 2989e42c5caSLiam Girdwood } 2999e42c5caSLiam Girdwood 30083ee7ab1SDaniel Baluta static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 30183ee7ab1SDaniel Baluta { 30283ee7ab1SDaniel Baluta return MBOX_OFFSET; 30383ee7ab1SDaniel Baluta } 30483ee7ab1SDaniel Baluta 30583ee7ab1SDaniel Baluta static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 30683ee7ab1SDaniel Baluta { 30783ee7ab1SDaniel Baluta return MBOX_OFFSET; 30883ee7ab1SDaniel Baluta } 30983ee7ab1SDaniel Baluta 3109e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev) 3119e42c5caSLiam Girdwood { 3129e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 3139e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 3149e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 3159e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 3169e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 3179e42c5caSLiam Girdwood 3189e42c5caSLiam Girdwood /* unmask busy interrupt */ 3199e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3209e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 3219e42c5caSLiam Girdwood } 3229e42c5caSLiam Girdwood 3239e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev) 3249e42c5caSLiam Girdwood { 3259e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 3269e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 3279e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 3289e42c5caSLiam Girdwood 3299e42c5caSLiam Girdwood /* unmask Done interrupt */ 3309e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 3319e42c5caSLiam Girdwood SHIM_IMRX_DONE, 0); 3329e42c5caSLiam Girdwood } 3339e42c5caSLiam Girdwood 3349e42c5caSLiam Girdwood /* 3359e42c5caSLiam Girdwood * DSP control. 3369e42c5caSLiam Girdwood */ 3379e42c5caSLiam Girdwood 3389e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev) 3399e42c5caSLiam Girdwood { 3409e42c5caSLiam Girdwood int tries = 10; 3419e42c5caSLiam Girdwood 3429e42c5caSLiam Girdwood /* release stall and wait to unstall */ 3439e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3449e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 3459e42c5caSLiam Girdwood while (tries--) { 3469e42c5caSLiam Girdwood if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 3479e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 3489e42c5caSLiam Girdwood break; 3499e42c5caSLiam Girdwood msleep(100); 3509e42c5caSLiam Girdwood } 3519e42c5caSLiam Girdwood if (tries < 0) { 3529e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 3539e42c5caSLiam Girdwood byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 3549e42c5caSLiam Girdwood return -ENODEV; 3559e42c5caSLiam Girdwood } 3569e42c5caSLiam Girdwood 3579e42c5caSLiam Girdwood /* return init core mask */ 3589e42c5caSLiam Girdwood return 1; 3599e42c5caSLiam Girdwood } 3609e42c5caSLiam Girdwood 3619e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev) 3629e42c5caSLiam Girdwood { 3639e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 3649e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3659e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3669e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 3679e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3689e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 3699e42c5caSLiam Girdwood 3709e42c5caSLiam Girdwood usleep_range(10, 15); 3719e42c5caSLiam Girdwood 3729e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 3739e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 3749e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 3759e42c5caSLiam Girdwood 3769e42c5caSLiam Girdwood return 0; 3779e42c5caSLiam Girdwood } 3789e42c5caSLiam Girdwood 3799e42c5caSLiam Girdwood /* Baytrail DAIs */ 3809e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = { 3819e42c5caSLiam Girdwood { 3829e42c5caSLiam Girdwood .name = "ssp0-port", 3839e42c5caSLiam Girdwood }, 3849e42c5caSLiam Girdwood { 3859e42c5caSLiam Girdwood .name = "ssp1-port", 3869e42c5caSLiam Girdwood }, 3879e42c5caSLiam Girdwood { 3889e42c5caSLiam Girdwood .name = "ssp2-port", 3899e42c5caSLiam Girdwood }, 3909e42c5caSLiam Girdwood { 3919e42c5caSLiam Girdwood .name = "ssp3-port", 3929e42c5caSLiam Girdwood }, 3939e42c5caSLiam Girdwood { 3949e42c5caSLiam Girdwood .name = "ssp4-port", 3959e42c5caSLiam Girdwood }, 3969e42c5caSLiam Girdwood { 3979e42c5caSLiam Girdwood .name = "ssp5-port", 3989e42c5caSLiam Girdwood }, 3999e42c5caSLiam Girdwood }; 4009e42c5caSLiam Girdwood 4019e42c5caSLiam Girdwood /* 4029e42c5caSLiam Girdwood * Probe and remove. 4039e42c5caSLiam Girdwood */ 4049e42c5caSLiam Girdwood 4059e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 4069e42c5caSLiam Girdwood 4079e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 4089e42c5caSLiam Girdwood { 4099e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 4109e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 4119e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 4129e42c5caSLiam Girdwood u32 base, size; 4139e42c5caSLiam Girdwood int ret; 4149e42c5caSLiam Girdwood 4159e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 4169e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 4179e42c5caSLiam Girdwood if (ret < 0) { 4189e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 4199e42c5caSLiam Girdwood return ret; 4209e42c5caSLiam Girdwood } 4219e42c5caSLiam Girdwood 4229e42c5caSLiam Girdwood /* LPE base */ 4239e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 4249e42c5caSLiam Girdwood size = BYT_PCI_BAR_SIZE; 4259e42c5caSLiam Girdwood 4269e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 4279e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 4289e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 4299e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 4309e42c5caSLiam Girdwood base, size); 4319e42c5caSLiam Girdwood return -ENODEV; 4329e42c5caSLiam Girdwood } 4339e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 4349e42c5caSLiam Girdwood 4359e42c5caSLiam Girdwood /* IMR base - optional */ 4369e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 4379e42c5caSLiam Girdwood goto irq; 4389e42c5caSLiam Girdwood 4399e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 4409e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 4419e42c5caSLiam Girdwood 4429e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 4439e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 4449e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 4459e42c5caSLiam Girdwood goto irq; 4469e42c5caSLiam Girdwood } 4479e42c5caSLiam Girdwood 4489e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 4499e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 4509e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 4519e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 4529e42c5caSLiam Girdwood base, size); 4539e42c5caSLiam Girdwood return -ENODEV; 4549e42c5caSLiam Girdwood } 4559e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 4569e42c5caSLiam Girdwood 4579e42c5caSLiam Girdwood irq: 4589e42c5caSLiam Girdwood /* register our IRQ */ 4599e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 4609e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 4619e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 4629e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 4639e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 4649e42c5caSLiam Girdwood if (ret < 0) { 4659e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 4669e42c5caSLiam Girdwood sdev->ipc_irq); 4679e42c5caSLiam Girdwood return ret; 4689e42c5caSLiam Girdwood } 4699e42c5caSLiam Girdwood 4709e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 4719e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 4729e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 4739e42c5caSLiam Girdwood 4749e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 4759e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 4769e42c5caSLiam Girdwood 4779e42c5caSLiam Girdwood return ret; 4789e42c5caSLiam Girdwood } 4799e42c5caSLiam Girdwood 4809e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 4819e42c5caSLiam Girdwood /* device init */ 4829e42c5caSLiam Girdwood .probe = tangier_pci_probe, 4839e42c5caSLiam Girdwood 4849e42c5caSLiam Girdwood /* DSP core boot / reset */ 4859e42c5caSLiam Girdwood .run = byt_run, 4869e42c5caSLiam Girdwood .reset = byt_reset, 4879e42c5caSLiam Girdwood 4889e42c5caSLiam Girdwood /* Register IO */ 4899e42c5caSLiam Girdwood .write = sof_io_write, 4909e42c5caSLiam Girdwood .read = sof_io_read, 4919e42c5caSLiam Girdwood .write64 = sof_io_write64, 4929e42c5caSLiam Girdwood .read64 = sof_io_read64, 4939e42c5caSLiam Girdwood 4949e42c5caSLiam Girdwood /* Block IO */ 4959e42c5caSLiam Girdwood .block_read = sof_block_read, 4969e42c5caSLiam Girdwood .block_write = sof_block_write, 4979e42c5caSLiam Girdwood 4989e42c5caSLiam Girdwood /* doorbell */ 4999e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 5009e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 5019e42c5caSLiam Girdwood 5029e42c5caSLiam Girdwood /* ipc */ 5039e42c5caSLiam Girdwood .send_msg = byt_send_msg, 50483ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 50583ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 50683ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 5079e42c5caSLiam Girdwood 5089e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 5099e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 5109e42c5caSLiam Girdwood 5119e42c5caSLiam Girdwood /* debug */ 5129e42c5caSLiam Girdwood .debug_map = byt_debugfs, 5139e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 5149e42c5caSLiam Girdwood .dbg_dump = byt_dump, 5159e42c5caSLiam Girdwood 5169e42c5caSLiam Girdwood /* stream callbacks */ 5179e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 5189e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 5199e42c5caSLiam Girdwood 5209e42c5caSLiam Girdwood /* module loading */ 5219e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 5229e42c5caSLiam Girdwood 5239e42c5caSLiam Girdwood /*Firmware loading */ 5249e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 5259e42c5caSLiam Girdwood 5269e42c5caSLiam Girdwood /* DAI drivers */ 5279e42c5caSLiam Girdwood .drv = byt_dai, 5289e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 5299e42c5caSLiam Girdwood }; 5309e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_tng_ops); 5319e42c5caSLiam Girdwood 5329e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 5339e42c5caSLiam Girdwood .cores_num = 1, 5349e42c5caSLiam Girdwood .cores_mask = 1, 5359e42c5caSLiam Girdwood }; 5369e42c5caSLiam Girdwood EXPORT_SYMBOL(tng_chip_info); 5379e42c5caSLiam Girdwood 5389e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 5399e42c5caSLiam Girdwood 5409e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 5419e42c5caSLiam Girdwood 5429e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 5439e42c5caSLiam Girdwood { 5449e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5459e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5469e42c5caSLiam Girdwood struct platform_device *pdev = 5479e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 5489e42c5caSLiam Girdwood struct resource *mmio; 5499e42c5caSLiam Girdwood u32 base, size; 5509e42c5caSLiam Girdwood int ret; 5519e42c5caSLiam Girdwood 5529e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5539e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 5549e42c5caSLiam Girdwood if (ret < 0) { 5559e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5569e42c5caSLiam Girdwood return ret; 5579e42c5caSLiam Girdwood } 5589e42c5caSLiam Girdwood 5599e42c5caSLiam Girdwood /* LPE base */ 5609e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 5619e42c5caSLiam Girdwood desc->resindex_lpe_base); 5629e42c5caSLiam Girdwood if (mmio) { 5639e42c5caSLiam Girdwood base = mmio->start; 5649e42c5caSLiam Girdwood size = resource_size(mmio); 5659e42c5caSLiam Girdwood } else { 5669e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 5679e42c5caSLiam Girdwood desc->resindex_lpe_base); 5689e42c5caSLiam Girdwood return -EINVAL; 5699e42c5caSLiam Girdwood } 5709e42c5caSLiam Girdwood 5719e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 5729e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 5739e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 5749e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5759e42c5caSLiam Girdwood base, size); 5769e42c5caSLiam Girdwood return -ENODEV; 5779e42c5caSLiam Girdwood } 5789e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 5799e42c5caSLiam Girdwood 5809e42c5caSLiam Girdwood /* TODO: add offsets */ 5819e42c5caSLiam Girdwood sdev->mmio_bar = BYT_DSP_BAR; 5829e42c5caSLiam Girdwood sdev->mailbox_bar = BYT_DSP_BAR; 5839e42c5caSLiam Girdwood 5849e42c5caSLiam Girdwood /* IMR base - optional */ 5859e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5869e42c5caSLiam Girdwood goto irq; 5879e42c5caSLiam Girdwood 5889e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 5899e42c5caSLiam Girdwood desc->resindex_imr_base); 5909e42c5caSLiam Girdwood if (mmio) { 5919e42c5caSLiam Girdwood base = mmio->start; 5929e42c5caSLiam Girdwood size = resource_size(mmio); 5939e42c5caSLiam Girdwood } else { 5949e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 5959e42c5caSLiam Girdwood desc->resindex_imr_base); 5969e42c5caSLiam Girdwood return -ENODEV; 5979e42c5caSLiam Girdwood } 5989e42c5caSLiam Girdwood 5999e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 6009e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 6019e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 6029e42c5caSLiam Girdwood goto irq; 6039e42c5caSLiam Girdwood } 6049e42c5caSLiam Girdwood 6059e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 6069e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 6079e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 6089e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 6099e42c5caSLiam Girdwood base, size); 6109e42c5caSLiam Girdwood return -ENODEV; 6119e42c5caSLiam Girdwood } 6129e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 6139e42c5caSLiam Girdwood 6149e42c5caSLiam Girdwood irq: 6159e42c5caSLiam Girdwood /* register our IRQ */ 6169e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 617cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 6189e42c5caSLiam Girdwood return sdev->ipc_irq; 6199e42c5caSLiam Girdwood 6209e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 6219e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 6229e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 6239e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 6249e42c5caSLiam Girdwood if (ret < 0) { 6259e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 6269e42c5caSLiam Girdwood sdev->ipc_irq); 6279e42c5caSLiam Girdwood return ret; 6289e42c5caSLiam Girdwood } 6299e42c5caSLiam Girdwood 6309e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 6319e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 6329e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 6339e42c5caSLiam Girdwood 6349e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 6359e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 6369e42c5caSLiam Girdwood 6379e42c5caSLiam Girdwood return ret; 6389e42c5caSLiam Girdwood } 6399e42c5caSLiam Girdwood 6409e42c5caSLiam Girdwood /* baytrail ops */ 6419e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_byt_ops = { 6429e42c5caSLiam Girdwood /* device init */ 6439e42c5caSLiam Girdwood .probe = byt_acpi_probe, 6449e42c5caSLiam Girdwood 6459e42c5caSLiam Girdwood /* DSP core boot / reset */ 6469e42c5caSLiam Girdwood .run = byt_run, 6479e42c5caSLiam Girdwood .reset = byt_reset, 6489e42c5caSLiam Girdwood 6499e42c5caSLiam Girdwood /* Register IO */ 6509e42c5caSLiam Girdwood .write = sof_io_write, 6519e42c5caSLiam Girdwood .read = sof_io_read, 6529e42c5caSLiam Girdwood .write64 = sof_io_write64, 6539e42c5caSLiam Girdwood .read64 = sof_io_read64, 6549e42c5caSLiam Girdwood 6559e42c5caSLiam Girdwood /* Block IO */ 6569e42c5caSLiam Girdwood .block_read = sof_block_read, 6579e42c5caSLiam Girdwood .block_write = sof_block_write, 6589e42c5caSLiam Girdwood 6599e42c5caSLiam Girdwood /* doorbell */ 6609e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 6619e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 6629e42c5caSLiam Girdwood 6639e42c5caSLiam Girdwood /* ipc */ 6649e42c5caSLiam Girdwood .send_msg = byt_send_msg, 66583ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 66683ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 66783ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 6689e42c5caSLiam Girdwood 6699e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6709e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6719e42c5caSLiam Girdwood 6729e42c5caSLiam Girdwood /* debug */ 6739e42c5caSLiam Girdwood .debug_map = byt_debugfs, 6749e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 6759e42c5caSLiam Girdwood .dbg_dump = byt_dump, 6769e42c5caSLiam Girdwood 6779e42c5caSLiam Girdwood /* stream callbacks */ 6789e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6799e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6809e42c5caSLiam Girdwood 6819e42c5caSLiam Girdwood /* module loading */ 6829e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6839e42c5caSLiam Girdwood 6849e42c5caSLiam Girdwood /*Firmware loading */ 6859e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6869e42c5caSLiam Girdwood 6879e42c5caSLiam Girdwood /* DAI drivers */ 6889e42c5caSLiam Girdwood .drv = byt_dai, 6899e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 6909e42c5caSLiam Girdwood }; 6919e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_byt_ops); 6929e42c5caSLiam Girdwood 6939e42c5caSLiam Girdwood const struct sof_intel_dsp_desc byt_chip_info = { 6949e42c5caSLiam Girdwood .cores_num = 1, 6959e42c5caSLiam Girdwood .cores_mask = 1, 6969e42c5caSLiam Girdwood }; 6979e42c5caSLiam Girdwood EXPORT_SYMBOL(byt_chip_info); 6989e42c5caSLiam Girdwood 6999e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 7009e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_cht_ops = { 7019e42c5caSLiam Girdwood /* device init */ 7029e42c5caSLiam Girdwood .probe = byt_acpi_probe, 7039e42c5caSLiam Girdwood 7049e42c5caSLiam Girdwood /* DSP core boot / reset */ 7059e42c5caSLiam Girdwood .run = byt_run, 7069e42c5caSLiam Girdwood .reset = byt_reset, 7079e42c5caSLiam Girdwood 7089e42c5caSLiam Girdwood /* Register IO */ 7099e42c5caSLiam Girdwood .write = sof_io_write, 7109e42c5caSLiam Girdwood .read = sof_io_read, 7119e42c5caSLiam Girdwood .write64 = sof_io_write64, 7129e42c5caSLiam Girdwood .read64 = sof_io_read64, 7139e42c5caSLiam Girdwood 7149e42c5caSLiam Girdwood /* Block IO */ 7159e42c5caSLiam Girdwood .block_read = sof_block_read, 7169e42c5caSLiam Girdwood .block_write = sof_block_write, 7179e42c5caSLiam Girdwood 7189e42c5caSLiam Girdwood /* doorbell */ 7199e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 7209e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 7219e42c5caSLiam Girdwood 7229e42c5caSLiam Girdwood /* ipc */ 7239e42c5caSLiam Girdwood .send_msg = byt_send_msg, 72483ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 72583ee7ab1SDaniel Baluta .get_mailbox_offset = byt_get_mailbox_offset, 72683ee7ab1SDaniel Baluta .get_window_offset = byt_get_window_offset, 7279e42c5caSLiam Girdwood 7289e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 7299e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 7309e42c5caSLiam Girdwood 7319e42c5caSLiam Girdwood /* debug */ 7329e42c5caSLiam Girdwood .debug_map = cht_debugfs, 7339e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 7349e42c5caSLiam Girdwood .dbg_dump = byt_dump, 7359e42c5caSLiam Girdwood 7369e42c5caSLiam Girdwood /* stream callbacks */ 7379e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 7389e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 7399e42c5caSLiam Girdwood 7409e42c5caSLiam Girdwood /* module loading */ 7419e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 7429e42c5caSLiam Girdwood 7439e42c5caSLiam Girdwood /*Firmware loading */ 7449e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 7459e42c5caSLiam Girdwood 7469e42c5caSLiam Girdwood /* DAI drivers */ 7479e42c5caSLiam Girdwood .drv = byt_dai, 7489e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 7499e42c5caSLiam Girdwood .num_drv = ARRAY_SIZE(byt_dai), 7509e42c5caSLiam Girdwood }; 7519e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_cht_ops); 7529e42c5caSLiam Girdwood 7539e42c5caSLiam Girdwood const struct sof_intel_dsp_desc cht_chip_info = { 7549e42c5caSLiam Girdwood .cores_num = 1, 7559e42c5caSLiam Girdwood .cores_mask = 1, 7569e42c5caSLiam Girdwood }; 7579e42c5caSLiam Girdwood EXPORT_SYMBOL(cht_chip_info); 7589e42c5caSLiam Girdwood 7599e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 7609e42c5caSLiam Girdwood 7619e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 762