xref: /openbmc/linux/sound/soc/sof/intel/byt.c (revision 27e322fa)
19e42c5caSLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
29e42c5caSLiam Girdwood //
39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license.  When using or
49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license.
59e42c5caSLiam Girdwood //
69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved.
79e42c5caSLiam Girdwood //
89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
99e42c5caSLiam Girdwood //
109e42c5caSLiam Girdwood 
119e42c5caSLiam Girdwood /*
129e42c5caSLiam Girdwood  * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
139e42c5caSLiam Girdwood  */
149e42c5caSLiam Girdwood 
159e42c5caSLiam Girdwood #include <linux/module.h>
169e42c5caSLiam Girdwood #include <sound/sof.h>
179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h>
189e42c5caSLiam Girdwood #include "../ops.h"
199e42c5caSLiam Girdwood #include "shim.h"
209e42c5caSLiam Girdwood 
219e42c5caSLiam Girdwood /* DSP memories */
229e42c5caSLiam Girdwood #define IRAM_OFFSET		0x0C0000
239e42c5caSLiam Girdwood #define IRAM_SIZE		(80 * 1024)
249e42c5caSLiam Girdwood #define DRAM_OFFSET		0x100000
259e42c5caSLiam Girdwood #define DRAM_SIZE		(160 * 1024)
269e42c5caSLiam Girdwood #define SHIM_OFFSET		0x140000
279e42c5caSLiam Girdwood #define SHIM_SIZE		0x100
289e42c5caSLiam Girdwood #define MBOX_OFFSET		0x144000
299e42c5caSLiam Girdwood #define MBOX_SIZE		0x1000
309e42c5caSLiam Girdwood #define EXCEPT_OFFSET		0x800
31ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE	0x400
329e42c5caSLiam Girdwood 
339e42c5caSLiam Girdwood /* DSP peripherals */
349e42c5caSLiam Girdwood #define DMAC0_OFFSET		0x098000
359e42c5caSLiam Girdwood #define DMAC1_OFFSET		0x09c000
369e42c5caSLiam Girdwood #define DMAC2_OFFSET		0x094000
379e42c5caSLiam Girdwood #define DMAC_SIZE		0x420
389e42c5caSLiam Girdwood #define SSP0_OFFSET		0x0a0000
399e42c5caSLiam Girdwood #define SSP1_OFFSET		0x0a1000
409e42c5caSLiam Girdwood #define SSP2_OFFSET		0x0a2000
419e42c5caSLiam Girdwood #define SSP3_OFFSET		0x0a4000
429e42c5caSLiam Girdwood #define SSP4_OFFSET		0x0a5000
439e42c5caSLiam Girdwood #define SSP5_OFFSET		0x0a6000
449e42c5caSLiam Girdwood #define SSP_SIZE		0x100
459e42c5caSLiam Girdwood 
469e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE	32
479e42c5caSLiam Girdwood 
489e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE	0x200000
499e42c5caSLiam Girdwood 
509e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x)	(((x) & GENMASK_ULL(47, 32)) >> 32)
519e42c5caSLiam Girdwood 
529e42c5caSLiam Girdwood /*
539e42c5caSLiam Girdwood  * Debug
549e42c5caSLiam Girdwood  */
559e42c5caSLiam Girdwood 
569e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE	0x30
579e42c5caSLiam Girdwood 
589e42c5caSLiam Girdwood /* BARs */
599e42c5caSLiam Girdwood #define BYT_DSP_BAR		0
609e42c5caSLiam Girdwood #define BYT_PCI_BAR		1
619e42c5caSLiam Girdwood #define BYT_IMR_BAR		2
629e42c5caSLiam Girdwood 
639e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = {
649e42c5caSLiam Girdwood 	{"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
659e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
669e42c5caSLiam Girdwood 	{"dmac1", BYT_DSP_BAR,  DMAC1_OFFSET, DMAC_SIZE,
679e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
689e42c5caSLiam Girdwood 	{"ssp0",  BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
699e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
709e42c5caSLiam Girdwood 	{"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
719e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
729e42c5caSLiam Girdwood 	{"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
739e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
749e42c5caSLiam Girdwood 	{"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
759e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_D0_ONLY},
769e42c5caSLiam Girdwood 	{"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
779e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_D0_ONLY},
789e42c5caSLiam Girdwood 	{"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
799e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
809e42c5caSLiam Girdwood };
819e42c5caSLiam Girdwood 
829e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map cht_debugfs[] = {
839e42c5caSLiam Girdwood 	{"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
849e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
859e42c5caSLiam Girdwood 	{"dmac1", BYT_DSP_BAR,  DMAC1_OFFSET, DMAC_SIZE,
869e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
879e42c5caSLiam Girdwood 	{"dmac2", BYT_DSP_BAR,  DMAC2_OFFSET, DMAC_SIZE,
889e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
899e42c5caSLiam Girdwood 	{"ssp0",  BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
909e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
919e42c5caSLiam Girdwood 	{"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
929e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
939e42c5caSLiam Girdwood 	{"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
949e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
959e42c5caSLiam Girdwood 	{"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE,
969e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
979e42c5caSLiam Girdwood 	{"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE,
989e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
999e42c5caSLiam Girdwood 	{"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE,
1009e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
1019e42c5caSLiam Girdwood 	{"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
1029e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_D0_ONLY},
1039e42c5caSLiam Girdwood 	{"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
1049e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_D0_ONLY},
1059e42c5caSLiam Girdwood 	{"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
1069e42c5caSLiam Girdwood 	 SOF_DEBUGFS_ACCESS_ALWAYS},
1079e42c5caSLiam Girdwood };
1089e42c5caSLiam Girdwood 
1099e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev);
1109e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev);
1119e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev);
1129e42c5caSLiam Girdwood 
1139e42c5caSLiam Girdwood /*
1149e42c5caSLiam Girdwood  * Debug
1159e42c5caSLiam Girdwood  */
1169e42c5caSLiam Girdwood 
1179e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev,
1189e42c5caSLiam Girdwood 			      struct sof_ipc_dsp_oops_xtensa *xoops,
1199e42c5caSLiam Girdwood 			      struct sof_ipc_panic_info *panic_info,
1209e42c5caSLiam Girdwood 			      u32 *stack, size_t stack_words)
1219e42c5caSLiam Girdwood {
12214104eb6SKai Vehmanen 	u32 offset = sdev->dsp_oops_offset;
12314104eb6SKai Vehmanen 
1249e42c5caSLiam Girdwood 	/* first read regsisters */
12514104eb6SKai Vehmanen 	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
12614104eb6SKai Vehmanen 
12714104eb6SKai Vehmanen 	/* note: variable AR register array is not read */
1289e42c5caSLiam Girdwood 
1299e42c5caSLiam Girdwood 	/* then get panic info */
130ff2be865SLiam Girdwood 	if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
131ff2be865SLiam Girdwood 		dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
132ff2be865SLiam Girdwood 			xoops->arch_hdr.totalsize);
133ff2be865SLiam Girdwood 		return;
134ff2be865SLiam Girdwood 	}
13514104eb6SKai Vehmanen 	offset += xoops->arch_hdr.totalsize;
13614104eb6SKai Vehmanen 	sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
1379e42c5caSLiam Girdwood 
1389e42c5caSLiam Girdwood 	/* then get the stack */
13914104eb6SKai Vehmanen 	offset += sizeof(*panic_info);
14014104eb6SKai Vehmanen 	sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
1419e42c5caSLiam Girdwood }
1429e42c5caSLiam Girdwood 
1439e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags)
1449e42c5caSLiam Girdwood {
1459e42c5caSLiam Girdwood 	struct sof_ipc_dsp_oops_xtensa xoops;
1469e42c5caSLiam Girdwood 	struct sof_ipc_panic_info panic_info;
1479e42c5caSLiam Girdwood 	u32 stack[BYT_STACK_DUMP_SIZE];
1483a9e204dSLiam Girdwood 	u32 status, panic, imrd, imrx;
1499e42c5caSLiam Girdwood 
1509e42c5caSLiam Girdwood 	/* now try generic SOF status messages */
1519e42c5caSLiam Girdwood 	status = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCD);
1529e42c5caSLiam Girdwood 	panic = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCX);
1539e42c5caSLiam Girdwood 	byt_get_registers(sdev, &xoops, &panic_info, stack,
1549e42c5caSLiam Girdwood 			  BYT_STACK_DUMP_SIZE);
1559e42c5caSLiam Girdwood 	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
1569e42c5caSLiam Girdwood 			   BYT_STACK_DUMP_SIZE);
1573a9e204dSLiam Girdwood 
1583a9e204dSLiam Girdwood 	/* provide some context for firmware debug */
1593a9e204dSLiam Girdwood 	imrx = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IMRX);
1603a9e204dSLiam Girdwood 	imrd = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IMRD);
1613a9e204dSLiam Girdwood 	dev_err(sdev->dev,
1623a9e204dSLiam Girdwood 		"error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",
163f9f618e7SPierre-Louis Bossart 		(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
164f9f618e7SPierre-Louis Bossart 		(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
1653a9e204dSLiam Girdwood 	dev_err(sdev->dev,
1663a9e204dSLiam Girdwood 		"error: mask host: pending %s complete %s raw 0x%8.8x\n",
167f9f618e7SPierre-Louis Bossart 		(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
168f9f618e7SPierre-Louis Bossart 		(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
1693a9e204dSLiam Girdwood 	dev_err(sdev->dev,
1703a9e204dSLiam Girdwood 		"error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",
171f9f618e7SPierre-Louis Bossart 		(status & SHIM_IPCD_BUSY) ? "yes" : "no",
172f9f618e7SPierre-Louis Bossart 		(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
1733a9e204dSLiam Girdwood 	dev_err(sdev->dev,
1743a9e204dSLiam Girdwood 		"error: mask DSP: pending %s complete %s raw 0x%8.8x\n",
175f9f618e7SPierre-Louis Bossart 		(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
176f9f618e7SPierre-Louis Bossart 		(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
1773a9e204dSLiam Girdwood 
1789e42c5caSLiam Girdwood }
1799e42c5caSLiam Girdwood 
1809e42c5caSLiam Girdwood /*
1819e42c5caSLiam Girdwood  * IPC Doorbell IRQ handler and thread.
1829e42c5caSLiam Girdwood  */
1839e42c5caSLiam Girdwood 
1849e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context)
1859e42c5caSLiam Girdwood {
1869e42c5caSLiam Girdwood 	struct snd_sof_dev *sdev = context;
1879e42c5caSLiam Girdwood 	u64 isr;
1889e42c5caSLiam Girdwood 	int ret = IRQ_NONE;
1899e42c5caSLiam Girdwood 
1909e42c5caSLiam Girdwood 	/* Interrupt arrived, check src */
1919e42c5caSLiam Girdwood 	isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX);
1929e42c5caSLiam Girdwood 	if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
1939e42c5caSLiam Girdwood 		ret = IRQ_WAKE_THREAD;
1949e42c5caSLiam Girdwood 
1959e42c5caSLiam Girdwood 	return ret;
1969e42c5caSLiam Girdwood }
1979e42c5caSLiam Girdwood 
1989e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context)
1999e42c5caSLiam Girdwood {
2009e42c5caSLiam Girdwood 	struct snd_sof_dev *sdev = context;
2019e42c5caSLiam Girdwood 	u64 ipcx, ipcd;
2029e42c5caSLiam Girdwood 	u64 imrx;
2039e42c5caSLiam Girdwood 
2049e42c5caSLiam Girdwood 	imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
2059e42c5caSLiam Girdwood 	ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
2069e42c5caSLiam Girdwood 
2079e42c5caSLiam Girdwood 	/* reply message from DSP */
2089e42c5caSLiam Girdwood 	if (ipcx & SHIM_BYT_IPCX_DONE &&
2099e42c5caSLiam Girdwood 	    !(imrx & SHIM_IMRX_DONE)) {
2109e42c5caSLiam Girdwood 		/* Mask Done interrupt before first */
2119e42c5caSLiam Girdwood 		snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
2129e42c5caSLiam Girdwood 						   SHIM_IMRX,
2139e42c5caSLiam Girdwood 						   SHIM_IMRX_DONE,
2149e42c5caSLiam Girdwood 						   SHIM_IMRX_DONE);
2151183e9a6SGuennadi Liakhovetski 
2161183e9a6SGuennadi Liakhovetski 		spin_lock_irq(&sdev->ipc_lock);
2171183e9a6SGuennadi Liakhovetski 
2189e42c5caSLiam Girdwood 		/*
2199e42c5caSLiam Girdwood 		 * handle immediate reply from DSP core. If the msg is
2209e42c5caSLiam Girdwood 		 * found, set done bit in cmd_done which is called at the
2219e42c5caSLiam Girdwood 		 * end of message processing function, else set it here
2229e42c5caSLiam Girdwood 		 * because the done bit can't be set in cmd_done function
2239e42c5caSLiam Girdwood 		 * which is triggered by msg
2249e42c5caSLiam Girdwood 		 */
2259e42c5caSLiam Girdwood 		byt_get_reply(sdev);
2269e42c5caSLiam Girdwood 		snd_sof_ipc_reply(sdev, ipcx);
2279e42c5caSLiam Girdwood 
2289e42c5caSLiam Girdwood 		byt_dsp_done(sdev);
2291183e9a6SGuennadi Liakhovetski 
2301183e9a6SGuennadi Liakhovetski 		spin_unlock_irq(&sdev->ipc_lock);
2319e42c5caSLiam Girdwood 	}
2329e42c5caSLiam Girdwood 
2339e42c5caSLiam Girdwood 	/* new message from DSP */
2349e42c5caSLiam Girdwood 	ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
2359e42c5caSLiam Girdwood 	if (ipcd & SHIM_BYT_IPCD_BUSY &&
2369e42c5caSLiam Girdwood 	    !(imrx & SHIM_IMRX_BUSY)) {
2379e42c5caSLiam Girdwood 		/* Mask Busy interrupt before return */
2389e42c5caSLiam Girdwood 		snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
2399e42c5caSLiam Girdwood 						   SHIM_IMRX,
2409e42c5caSLiam Girdwood 						   SHIM_IMRX_BUSY,
2419e42c5caSLiam Girdwood 						   SHIM_IMRX_BUSY);
2429e42c5caSLiam Girdwood 
2439e42c5caSLiam Girdwood 		/* Handle messages from DSP Core */
2449e42c5caSLiam Girdwood 		if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
2459e42c5caSLiam Girdwood 			snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) +
2469e42c5caSLiam Girdwood 					  MBOX_OFFSET);
2479e42c5caSLiam Girdwood 		} else {
2489e42c5caSLiam Girdwood 			snd_sof_ipc_msgs_rx(sdev);
2499e42c5caSLiam Girdwood 		}
2509e42c5caSLiam Girdwood 
2519e42c5caSLiam Girdwood 		byt_host_done(sdev);
2529e42c5caSLiam Girdwood 	}
2539e42c5caSLiam Girdwood 
2549e42c5caSLiam Girdwood 	return IRQ_HANDLED;
2559e42c5caSLiam Girdwood }
2569e42c5caSLiam Girdwood 
2579e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
2589e42c5caSLiam Girdwood {
2599e42c5caSLiam Girdwood 	/* send the message */
2609e42c5caSLiam Girdwood 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
2619e42c5caSLiam Girdwood 			  msg->msg_size);
2626fbbc18eSDaniel Baluta 	snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
2639e42c5caSLiam Girdwood 
2649e42c5caSLiam Girdwood 	return 0;
2659e42c5caSLiam Girdwood }
2669e42c5caSLiam Girdwood 
2679e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev)
2689e42c5caSLiam Girdwood {
2699e42c5caSLiam Girdwood 	struct snd_sof_ipc_msg *msg = sdev->msg;
2709e42c5caSLiam Girdwood 	struct sof_ipc_reply reply;
2719e42c5caSLiam Girdwood 	int ret = 0;
2729e42c5caSLiam Girdwood 
2739e42c5caSLiam Girdwood 	/*
2749e42c5caSLiam Girdwood 	 * Sometimes, there is unexpected reply ipc arriving. The reply
2759e42c5caSLiam Girdwood 	 * ipc belongs to none of the ipcs sent from driver.
2769e42c5caSLiam Girdwood 	 * In this case, the driver must ignore the ipc.
2779e42c5caSLiam Girdwood 	 */
2789e42c5caSLiam Girdwood 	if (!msg) {
2799e42c5caSLiam Girdwood 		dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
2809e42c5caSLiam Girdwood 		return;
2819e42c5caSLiam Girdwood 	}
2829e42c5caSLiam Girdwood 
2839e42c5caSLiam Girdwood 	/* get reply */
2849e42c5caSLiam Girdwood 	sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
2859e42c5caSLiam Girdwood 
2869e42c5caSLiam Girdwood 	if (reply.error < 0) {
2879e42c5caSLiam Girdwood 		memcpy(msg->reply_data, &reply, sizeof(reply));
2889e42c5caSLiam Girdwood 		ret = reply.error;
2899e42c5caSLiam Girdwood 	} else {
2909e42c5caSLiam Girdwood 		/* reply correct size ? */
2919e42c5caSLiam Girdwood 		if (reply.hdr.size != msg->reply_size) {
2929e42c5caSLiam Girdwood 			dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
2939e42c5caSLiam Girdwood 				msg->reply_size, reply.hdr.size);
2949e42c5caSLiam Girdwood 			ret = -EINVAL;
2959e42c5caSLiam Girdwood 		}
2969e42c5caSLiam Girdwood 
2979e42c5caSLiam Girdwood 		/* read the message */
2989e42c5caSLiam Girdwood 		if (msg->reply_size > 0)
2999e42c5caSLiam Girdwood 			sof_mailbox_read(sdev, sdev->host_box.offset,
3009e42c5caSLiam Girdwood 					 msg->reply_data, msg->reply_size);
3019e42c5caSLiam Girdwood 	}
3029e42c5caSLiam Girdwood 
3039e42c5caSLiam Girdwood 	msg->reply_error = ret;
3049e42c5caSLiam Girdwood }
3059e42c5caSLiam Girdwood 
30683ee7ab1SDaniel Baluta static int byt_get_mailbox_offset(struct snd_sof_dev *sdev)
30783ee7ab1SDaniel Baluta {
30883ee7ab1SDaniel Baluta 	return MBOX_OFFSET;
30983ee7ab1SDaniel Baluta }
31083ee7ab1SDaniel Baluta 
31183ee7ab1SDaniel Baluta static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id)
31283ee7ab1SDaniel Baluta {
31383ee7ab1SDaniel Baluta 	return MBOX_OFFSET;
31483ee7ab1SDaniel Baluta }
31583ee7ab1SDaniel Baluta 
3169e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev)
3179e42c5caSLiam Girdwood {
3189e42c5caSLiam Girdwood 	/* clear BUSY bit and set DONE bit - accept new messages */
3199e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,
3209e42c5caSLiam Girdwood 					   SHIM_BYT_IPCD_BUSY |
3219e42c5caSLiam Girdwood 					   SHIM_BYT_IPCD_DONE,
3229e42c5caSLiam Girdwood 					   SHIM_BYT_IPCD_DONE);
3239e42c5caSLiam Girdwood 
3249e42c5caSLiam Girdwood 	/* unmask busy interrupt */
3259e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
3269e42c5caSLiam Girdwood 					   SHIM_IMRX_BUSY, 0);
3279e42c5caSLiam Girdwood }
3289e42c5caSLiam Girdwood 
3299e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev)
3309e42c5caSLiam Girdwood {
3319e42c5caSLiam Girdwood 	/* clear DONE bit - tell DSP we have completed */
3329e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,
3339e42c5caSLiam Girdwood 					   SHIM_BYT_IPCX_DONE, 0);
3349e42c5caSLiam Girdwood 
3359e42c5caSLiam Girdwood 	/* unmask Done interrupt */
3369e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
3379e42c5caSLiam Girdwood 					   SHIM_IMRX_DONE, 0);
3389e42c5caSLiam Girdwood }
3399e42c5caSLiam Girdwood 
3409e42c5caSLiam Girdwood /*
3419e42c5caSLiam Girdwood  * DSP control.
3429e42c5caSLiam Girdwood  */
3439e42c5caSLiam Girdwood 
3449e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev)
3459e42c5caSLiam Girdwood {
3469e42c5caSLiam Girdwood 	int tries = 10;
3479e42c5caSLiam Girdwood 
3489e42c5caSLiam Girdwood 	/* release stall and wait to unstall */
3499e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
3509e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_STALL, 0x0);
3519e42c5caSLiam Girdwood 	while (tries--) {
3529e42c5caSLiam Girdwood 		if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &
3539e42c5caSLiam Girdwood 		      SHIM_BYT_CSR_PWAITMODE))
3549e42c5caSLiam Girdwood 			break;
3559e42c5caSLiam Girdwood 		msleep(100);
3569e42c5caSLiam Girdwood 	}
3579e42c5caSLiam Girdwood 	if (tries < 0) {
3589e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error:  unable to run DSP firmware\n");
3599e42c5caSLiam Girdwood 		byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX);
3609e42c5caSLiam Girdwood 		return -ENODEV;
3619e42c5caSLiam Girdwood 	}
3629e42c5caSLiam Girdwood 
3639e42c5caSLiam Girdwood 	/* return init core mask */
3649e42c5caSLiam Girdwood 	return 1;
3659e42c5caSLiam Girdwood }
3669e42c5caSLiam Girdwood 
3679e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev)
3689e42c5caSLiam Girdwood {
3699e42c5caSLiam Girdwood 	/* put DSP into reset, set reset vector and stall */
3709e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
3719e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
3729e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_STALL,
3739e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
3749e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_STALL);
3759e42c5caSLiam Girdwood 
3769e42c5caSLiam Girdwood 	usleep_range(10, 15);
3779e42c5caSLiam Girdwood 
3789e42c5caSLiam Girdwood 	/* take DSP out of reset and keep stalled for FW loading */
3799e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
3809e42c5caSLiam Girdwood 				  SHIM_BYT_CSR_RST, 0);
3819e42c5caSLiam Girdwood 
3829e42c5caSLiam Girdwood 	return 0;
3839e42c5caSLiam Girdwood }
3849e42c5caSLiam Girdwood 
3859e42c5caSLiam Girdwood /* Baytrail DAIs */
3869e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = {
3879e42c5caSLiam Girdwood {
3889e42c5caSLiam Girdwood 	.name = "ssp0-port",
3899e42c5caSLiam Girdwood },
3909e42c5caSLiam Girdwood {
3919e42c5caSLiam Girdwood 	.name = "ssp1-port",
3929e42c5caSLiam Girdwood },
3939e42c5caSLiam Girdwood {
3949e42c5caSLiam Girdwood 	.name = "ssp2-port",
3959e42c5caSLiam Girdwood },
3969e42c5caSLiam Girdwood {
3979e42c5caSLiam Girdwood 	.name = "ssp3-port",
3989e42c5caSLiam Girdwood },
3999e42c5caSLiam Girdwood {
4009e42c5caSLiam Girdwood 	.name = "ssp4-port",
4019e42c5caSLiam Girdwood },
4029e42c5caSLiam Girdwood {
4039e42c5caSLiam Girdwood 	.name = "ssp5-port",
4049e42c5caSLiam Girdwood },
4059e42c5caSLiam Girdwood };
4069e42c5caSLiam Girdwood 
4079e42c5caSLiam Girdwood /*
4089e42c5caSLiam Girdwood  * Probe and remove.
4099e42c5caSLiam Girdwood  */
4109e42c5caSLiam Girdwood 
4119e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD)
4129e42c5caSLiam Girdwood 
4139e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev)
4149e42c5caSLiam Girdwood {
4159e42c5caSLiam Girdwood 	struct snd_sof_pdata *pdata = sdev->pdata;
4169e42c5caSLiam Girdwood 	const struct sof_dev_desc *desc = pdata->desc;
4179e42c5caSLiam Girdwood 	struct pci_dev *pci = to_pci_dev(sdev->dev);
4189e42c5caSLiam Girdwood 	u32 base, size;
4199e42c5caSLiam Girdwood 	int ret;
4209e42c5caSLiam Girdwood 
4219e42c5caSLiam Girdwood 	/* DSP DMA can only access low 31 bits of host memory */
4229e42c5caSLiam Girdwood 	ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
4239e42c5caSLiam Girdwood 	if (ret < 0) {
4249e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
4259e42c5caSLiam Girdwood 		return ret;
4269e42c5caSLiam Girdwood 	}
4279e42c5caSLiam Girdwood 
4289e42c5caSLiam Girdwood 	/* LPE base */
4299e42c5caSLiam Girdwood 	base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
4309e42c5caSLiam Girdwood 	size = BYT_PCI_BAR_SIZE;
4319e42c5caSLiam Girdwood 
4329e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
4339e42c5caSLiam Girdwood 	sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
4349e42c5caSLiam Girdwood 	if (!sdev->bar[BYT_DSP_BAR]) {
4359e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
4369e42c5caSLiam Girdwood 			base, size);
4379e42c5caSLiam Girdwood 		return -ENODEV;
4389e42c5caSLiam Girdwood 	}
4399e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
4409e42c5caSLiam Girdwood 
4419e42c5caSLiam Girdwood 	/* IMR base - optional */
4429e42c5caSLiam Girdwood 	if (desc->resindex_imr_base == -1)
4439e42c5caSLiam Girdwood 		goto irq;
4449e42c5caSLiam Girdwood 
4459e42c5caSLiam Girdwood 	base = pci_resource_start(pci, desc->resindex_imr_base);
4469e42c5caSLiam Girdwood 	size = pci_resource_len(pci, desc->resindex_imr_base);
4479e42c5caSLiam Girdwood 
4489e42c5caSLiam Girdwood 	/* some BIOSes don't map IMR */
4499e42c5caSLiam Girdwood 	if (base == 0x55aa55aa || base == 0x0) {
4509e42c5caSLiam Girdwood 		dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
4519e42c5caSLiam Girdwood 		goto irq;
4529e42c5caSLiam Girdwood 	}
4539e42c5caSLiam Girdwood 
4549e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
4559e42c5caSLiam Girdwood 	sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
4569e42c5caSLiam Girdwood 	if (!sdev->bar[BYT_IMR_BAR]) {
4579e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
4589e42c5caSLiam Girdwood 			base, size);
4599e42c5caSLiam Girdwood 		return -ENODEV;
4609e42c5caSLiam Girdwood 	}
4619e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
4629e42c5caSLiam Girdwood 
4639e42c5caSLiam Girdwood irq:
4649e42c5caSLiam Girdwood 	/* register our IRQ */
4659e42c5caSLiam Girdwood 	sdev->ipc_irq = pci->irq;
4669e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
4679e42c5caSLiam Girdwood 	ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
4689e42c5caSLiam Girdwood 					byt_irq_handler, byt_irq_thread,
4699e42c5caSLiam Girdwood 					0, "AudioDSP", sdev);
4709e42c5caSLiam Girdwood 	if (ret < 0) {
4719e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to register IRQ %d\n",
4729e42c5caSLiam Girdwood 			sdev->ipc_irq);
4739e42c5caSLiam Girdwood 		return ret;
4749e42c5caSLiam Girdwood 	}
4759e42c5caSLiam Girdwood 
4769e42c5caSLiam Girdwood 	/* enable Interrupt from both sides */
4779e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
4789e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
4799e42c5caSLiam Girdwood 
4809e42c5caSLiam Girdwood 	/* set default mailbox offset for FW ready message */
4819e42c5caSLiam Girdwood 	sdev->dsp_box.offset = MBOX_OFFSET;
4829e42c5caSLiam Girdwood 
4839e42c5caSLiam Girdwood 	return ret;
4849e42c5caSLiam Girdwood }
4859e42c5caSLiam Girdwood 
4869e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = {
4879e42c5caSLiam Girdwood 	/* device init */
4889e42c5caSLiam Girdwood 	.probe		= tangier_pci_probe,
4899e42c5caSLiam Girdwood 
4909e42c5caSLiam Girdwood 	/* DSP core boot / reset */
4919e42c5caSLiam Girdwood 	.run		= byt_run,
4929e42c5caSLiam Girdwood 	.reset		= byt_reset,
4939e42c5caSLiam Girdwood 
4949e42c5caSLiam Girdwood 	/* Register IO */
4959e42c5caSLiam Girdwood 	.write		= sof_io_write,
4969e42c5caSLiam Girdwood 	.read		= sof_io_read,
4979e42c5caSLiam Girdwood 	.write64	= sof_io_write64,
4989e42c5caSLiam Girdwood 	.read64		= sof_io_read64,
4999e42c5caSLiam Girdwood 
5009e42c5caSLiam Girdwood 	/* Block IO */
5019e42c5caSLiam Girdwood 	.block_read	= sof_block_read,
5029e42c5caSLiam Girdwood 	.block_write	= sof_block_write,
5039e42c5caSLiam Girdwood 
5049e42c5caSLiam Girdwood 	/* doorbell */
5059e42c5caSLiam Girdwood 	.irq_handler	= byt_irq_handler,
5069e42c5caSLiam Girdwood 	.irq_thread	= byt_irq_thread,
5079e42c5caSLiam Girdwood 
5089e42c5caSLiam Girdwood 	/* ipc */
5099e42c5caSLiam Girdwood 	.send_msg	= byt_send_msg,
51083ee7ab1SDaniel Baluta 	.fw_ready	= sof_fw_ready,
51183ee7ab1SDaniel Baluta 	.get_mailbox_offset = byt_get_mailbox_offset,
51283ee7ab1SDaniel Baluta 	.get_window_offset = byt_get_window_offset,
5139e42c5caSLiam Girdwood 
5149e42c5caSLiam Girdwood 	.ipc_msg_data	= intel_ipc_msg_data,
5159e42c5caSLiam Girdwood 	.ipc_pcm_params	= intel_ipc_pcm_params,
5169e42c5caSLiam Girdwood 
5179e42c5caSLiam Girdwood 	/* debug */
5189e42c5caSLiam Girdwood 	.debug_map	= byt_debugfs,
5199e42c5caSLiam Girdwood 	.debug_map_count	= ARRAY_SIZE(byt_debugfs),
5209e42c5caSLiam Girdwood 	.dbg_dump	= byt_dump,
5219e42c5caSLiam Girdwood 
5229e42c5caSLiam Girdwood 	/* stream callbacks */
5239e42c5caSLiam Girdwood 	.pcm_open	= intel_pcm_open,
5249e42c5caSLiam Girdwood 	.pcm_close	= intel_pcm_close,
5259e42c5caSLiam Girdwood 
5269e42c5caSLiam Girdwood 	/* module loading */
5279e42c5caSLiam Girdwood 	.load_module	= snd_sof_parse_module_memcpy,
5289e42c5caSLiam Girdwood 
5299e42c5caSLiam Girdwood 	/*Firmware loading */
5309e42c5caSLiam Girdwood 	.load_firmware	= snd_sof_load_firmware_memcpy,
5319e42c5caSLiam Girdwood 
5329e42c5caSLiam Girdwood 	/* DAI drivers */
5339e42c5caSLiam Girdwood 	.drv = byt_dai,
5349e42c5caSLiam Girdwood 	.num_drv = 3, /* we have only 3 SSPs on byt*/
53527e322faSPierre-Louis Bossart 
53627e322faSPierre-Louis Bossart 	/* ALSA HW info flags */
53727e322faSPierre-Louis Bossart 	.hw_info =	SNDRV_PCM_INFO_MMAP |
53827e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_MMAP_VALID |
53927e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_INTERLEAVED |
54027e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_PAUSE |
54127e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
5429e42c5caSLiam Girdwood };
5439e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_tng_ops);
5449e42c5caSLiam Girdwood 
5459e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = {
5469e42c5caSLiam Girdwood 	.cores_num = 1,
5479e42c5caSLiam Girdwood 	.cores_mask = 1,
5489e42c5caSLiam Girdwood };
5499e42c5caSLiam Girdwood EXPORT_SYMBOL(tng_chip_info);
5509e42c5caSLiam Girdwood 
5519e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */
5529e42c5caSLiam Girdwood 
5539e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
5549e42c5caSLiam Girdwood 
5559e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev)
5569e42c5caSLiam Girdwood {
5579e42c5caSLiam Girdwood 	struct snd_sof_pdata *pdata = sdev->pdata;
5589e42c5caSLiam Girdwood 	const struct sof_dev_desc *desc = pdata->desc;
5599e42c5caSLiam Girdwood 	struct platform_device *pdev =
5609e42c5caSLiam Girdwood 		container_of(sdev->dev, struct platform_device, dev);
5619e42c5caSLiam Girdwood 	struct resource *mmio;
5629e42c5caSLiam Girdwood 	u32 base, size;
5639e42c5caSLiam Girdwood 	int ret;
5649e42c5caSLiam Girdwood 
5659e42c5caSLiam Girdwood 	/* DSP DMA can only access low 31 bits of host memory */
5669e42c5caSLiam Girdwood 	ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
5679e42c5caSLiam Girdwood 	if (ret < 0) {
5689e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
5699e42c5caSLiam Girdwood 		return ret;
5709e42c5caSLiam Girdwood 	}
5719e42c5caSLiam Girdwood 
5729e42c5caSLiam Girdwood 	/* LPE base */
5739e42c5caSLiam Girdwood 	mmio = platform_get_resource(pdev, IORESOURCE_MEM,
5749e42c5caSLiam Girdwood 				     desc->resindex_lpe_base);
5759e42c5caSLiam Girdwood 	if (mmio) {
5769e42c5caSLiam Girdwood 		base = mmio->start;
5779e42c5caSLiam Girdwood 		size = resource_size(mmio);
5789e42c5caSLiam Girdwood 	} else {
5799e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
5809e42c5caSLiam Girdwood 			desc->resindex_lpe_base);
5819e42c5caSLiam Girdwood 		return -EINVAL;
5829e42c5caSLiam Girdwood 	}
5839e42c5caSLiam Girdwood 
5849e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
5859e42c5caSLiam Girdwood 	sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
5869e42c5caSLiam Girdwood 	if (!sdev->bar[BYT_DSP_BAR]) {
5879e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
5889e42c5caSLiam Girdwood 			base, size);
5899e42c5caSLiam Girdwood 		return -ENODEV;
5909e42c5caSLiam Girdwood 	}
5919e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
5929e42c5caSLiam Girdwood 
5939e42c5caSLiam Girdwood 	/* TODO: add offsets */
5949e42c5caSLiam Girdwood 	sdev->mmio_bar = BYT_DSP_BAR;
5959e42c5caSLiam Girdwood 	sdev->mailbox_bar = BYT_DSP_BAR;
5969e42c5caSLiam Girdwood 
5979e42c5caSLiam Girdwood 	/* IMR base - optional */
5989e42c5caSLiam Girdwood 	if (desc->resindex_imr_base == -1)
5999e42c5caSLiam Girdwood 		goto irq;
6009e42c5caSLiam Girdwood 
6019e42c5caSLiam Girdwood 	mmio = platform_get_resource(pdev, IORESOURCE_MEM,
6029e42c5caSLiam Girdwood 				     desc->resindex_imr_base);
6039e42c5caSLiam Girdwood 	if (mmio) {
6049e42c5caSLiam Girdwood 		base = mmio->start;
6059e42c5caSLiam Girdwood 		size = resource_size(mmio);
6069e42c5caSLiam Girdwood 	} else {
6079e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
6089e42c5caSLiam Girdwood 			desc->resindex_imr_base);
6099e42c5caSLiam Girdwood 		return -ENODEV;
6109e42c5caSLiam Girdwood 	}
6119e42c5caSLiam Girdwood 
6129e42c5caSLiam Girdwood 	/* some BIOSes don't map IMR */
6139e42c5caSLiam Girdwood 	if (base == 0x55aa55aa || base == 0x0) {
6149e42c5caSLiam Girdwood 		dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
6159e42c5caSLiam Girdwood 		goto irq;
6169e42c5caSLiam Girdwood 	}
6179e42c5caSLiam Girdwood 
6189e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
6199e42c5caSLiam Girdwood 	sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
6209e42c5caSLiam Girdwood 	if (!sdev->bar[BYT_IMR_BAR]) {
6219e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
6229e42c5caSLiam Girdwood 			base, size);
6239e42c5caSLiam Girdwood 		return -ENODEV;
6249e42c5caSLiam Girdwood 	}
6259e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
6269e42c5caSLiam Girdwood 
6279e42c5caSLiam Girdwood irq:
6289e42c5caSLiam Girdwood 	/* register our IRQ */
6299e42c5caSLiam Girdwood 	sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
630cf9441adSStephen Boyd 	if (sdev->ipc_irq < 0)
6319e42c5caSLiam Girdwood 		return sdev->ipc_irq;
6329e42c5caSLiam Girdwood 
6339e42c5caSLiam Girdwood 	dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
6349e42c5caSLiam Girdwood 	ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
6359e42c5caSLiam Girdwood 					byt_irq_handler, byt_irq_thread,
6369e42c5caSLiam Girdwood 					IRQF_SHARED, "AudioDSP", sdev);
6379e42c5caSLiam Girdwood 	if (ret < 0) {
6389e42c5caSLiam Girdwood 		dev_err(sdev->dev, "error: failed to register IRQ %d\n",
6399e42c5caSLiam Girdwood 			sdev->ipc_irq);
6409e42c5caSLiam Girdwood 		return ret;
6419e42c5caSLiam Girdwood 	}
6429e42c5caSLiam Girdwood 
6439e42c5caSLiam Girdwood 	/* enable Interrupt from both sides */
6449e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
6459e42c5caSLiam Girdwood 	snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
6469e42c5caSLiam Girdwood 
6479e42c5caSLiam Girdwood 	/* set default mailbox offset for FW ready message */
6489e42c5caSLiam Girdwood 	sdev->dsp_box.offset = MBOX_OFFSET;
6499e42c5caSLiam Girdwood 
6509e42c5caSLiam Girdwood 	return ret;
6519e42c5caSLiam Girdwood }
6529e42c5caSLiam Girdwood 
6539e42c5caSLiam Girdwood /* baytrail ops */
6549e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_byt_ops = {
6559e42c5caSLiam Girdwood 	/* device init */
6569e42c5caSLiam Girdwood 	.probe		= byt_acpi_probe,
6579e42c5caSLiam Girdwood 
6589e42c5caSLiam Girdwood 	/* DSP core boot / reset */
6599e42c5caSLiam Girdwood 	.run		= byt_run,
6609e42c5caSLiam Girdwood 	.reset		= byt_reset,
6619e42c5caSLiam Girdwood 
6629e42c5caSLiam Girdwood 	/* Register IO */
6639e42c5caSLiam Girdwood 	.write		= sof_io_write,
6649e42c5caSLiam Girdwood 	.read		= sof_io_read,
6659e42c5caSLiam Girdwood 	.write64	= sof_io_write64,
6669e42c5caSLiam Girdwood 	.read64		= sof_io_read64,
6679e42c5caSLiam Girdwood 
6689e42c5caSLiam Girdwood 	/* Block IO */
6699e42c5caSLiam Girdwood 	.block_read	= sof_block_read,
6709e42c5caSLiam Girdwood 	.block_write	= sof_block_write,
6719e42c5caSLiam Girdwood 
6729e42c5caSLiam Girdwood 	/* doorbell */
6739e42c5caSLiam Girdwood 	.irq_handler	= byt_irq_handler,
6749e42c5caSLiam Girdwood 	.irq_thread	= byt_irq_thread,
6759e42c5caSLiam Girdwood 
6769e42c5caSLiam Girdwood 	/* ipc */
6779e42c5caSLiam Girdwood 	.send_msg	= byt_send_msg,
67883ee7ab1SDaniel Baluta 	.fw_ready	= sof_fw_ready,
67983ee7ab1SDaniel Baluta 	.get_mailbox_offset = byt_get_mailbox_offset,
68083ee7ab1SDaniel Baluta 	.get_window_offset = byt_get_window_offset,
6819e42c5caSLiam Girdwood 
6829e42c5caSLiam Girdwood 	.ipc_msg_data	= intel_ipc_msg_data,
6839e42c5caSLiam Girdwood 	.ipc_pcm_params	= intel_ipc_pcm_params,
6849e42c5caSLiam Girdwood 
6859e42c5caSLiam Girdwood 	/* debug */
6869e42c5caSLiam Girdwood 	.debug_map	= byt_debugfs,
6879e42c5caSLiam Girdwood 	.debug_map_count	= ARRAY_SIZE(byt_debugfs),
6889e42c5caSLiam Girdwood 	.dbg_dump	= byt_dump,
6899e42c5caSLiam Girdwood 
6909e42c5caSLiam Girdwood 	/* stream callbacks */
6919e42c5caSLiam Girdwood 	.pcm_open	= intel_pcm_open,
6929e42c5caSLiam Girdwood 	.pcm_close	= intel_pcm_close,
6939e42c5caSLiam Girdwood 
6949e42c5caSLiam Girdwood 	/* module loading */
6959e42c5caSLiam Girdwood 	.load_module	= snd_sof_parse_module_memcpy,
6969e42c5caSLiam Girdwood 
6979e42c5caSLiam Girdwood 	/*Firmware loading */
6989e42c5caSLiam Girdwood 	.load_firmware	= snd_sof_load_firmware_memcpy,
6999e42c5caSLiam Girdwood 
7009e42c5caSLiam Girdwood 	/* DAI drivers */
7019e42c5caSLiam Girdwood 	.drv = byt_dai,
7029e42c5caSLiam Girdwood 	.num_drv = 3, /* we have only 3 SSPs on byt*/
70327e322faSPierre-Louis Bossart 
70427e322faSPierre-Louis Bossart 	/* ALSA HW info flags */
70527e322faSPierre-Louis Bossart 	.hw_info =	SNDRV_PCM_INFO_MMAP |
70627e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_MMAP_VALID |
70727e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_INTERLEAVED |
70827e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_PAUSE |
70927e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
7109e42c5caSLiam Girdwood };
7119e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_byt_ops);
7129e42c5caSLiam Girdwood 
7139e42c5caSLiam Girdwood const struct sof_intel_dsp_desc byt_chip_info = {
7149e42c5caSLiam Girdwood 	.cores_num = 1,
7159e42c5caSLiam Girdwood 	.cores_mask = 1,
7169e42c5caSLiam Girdwood };
7179e42c5caSLiam Girdwood EXPORT_SYMBOL(byt_chip_info);
7189e42c5caSLiam Girdwood 
7199e42c5caSLiam Girdwood /* cherrytrail and braswell ops */
7209e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_cht_ops = {
7219e42c5caSLiam Girdwood 	/* device init */
7229e42c5caSLiam Girdwood 	.probe		= byt_acpi_probe,
7239e42c5caSLiam Girdwood 
7249e42c5caSLiam Girdwood 	/* DSP core boot / reset */
7259e42c5caSLiam Girdwood 	.run		= byt_run,
7269e42c5caSLiam Girdwood 	.reset		= byt_reset,
7279e42c5caSLiam Girdwood 
7289e42c5caSLiam Girdwood 	/* Register IO */
7299e42c5caSLiam Girdwood 	.write		= sof_io_write,
7309e42c5caSLiam Girdwood 	.read		= sof_io_read,
7319e42c5caSLiam Girdwood 	.write64	= sof_io_write64,
7329e42c5caSLiam Girdwood 	.read64		= sof_io_read64,
7339e42c5caSLiam Girdwood 
7349e42c5caSLiam Girdwood 	/* Block IO */
7359e42c5caSLiam Girdwood 	.block_read	= sof_block_read,
7369e42c5caSLiam Girdwood 	.block_write	= sof_block_write,
7379e42c5caSLiam Girdwood 
7389e42c5caSLiam Girdwood 	/* doorbell */
7399e42c5caSLiam Girdwood 	.irq_handler	= byt_irq_handler,
7409e42c5caSLiam Girdwood 	.irq_thread	= byt_irq_thread,
7419e42c5caSLiam Girdwood 
7429e42c5caSLiam Girdwood 	/* ipc */
7439e42c5caSLiam Girdwood 	.send_msg	= byt_send_msg,
74483ee7ab1SDaniel Baluta 	.fw_ready	= sof_fw_ready,
74583ee7ab1SDaniel Baluta 	.get_mailbox_offset = byt_get_mailbox_offset,
74683ee7ab1SDaniel Baluta 	.get_window_offset = byt_get_window_offset,
7479e42c5caSLiam Girdwood 
7489e42c5caSLiam Girdwood 	.ipc_msg_data	= intel_ipc_msg_data,
7499e42c5caSLiam Girdwood 	.ipc_pcm_params	= intel_ipc_pcm_params,
7509e42c5caSLiam Girdwood 
7519e42c5caSLiam Girdwood 	/* debug */
7529e42c5caSLiam Girdwood 	.debug_map	= cht_debugfs,
7539e42c5caSLiam Girdwood 	.debug_map_count	= ARRAY_SIZE(cht_debugfs),
7549e42c5caSLiam Girdwood 	.dbg_dump	= byt_dump,
7559e42c5caSLiam Girdwood 
7569e42c5caSLiam Girdwood 	/* stream callbacks */
7579e42c5caSLiam Girdwood 	.pcm_open	= intel_pcm_open,
7589e42c5caSLiam Girdwood 	.pcm_close	= intel_pcm_close,
7599e42c5caSLiam Girdwood 
7609e42c5caSLiam Girdwood 	/* module loading */
7619e42c5caSLiam Girdwood 	.load_module	= snd_sof_parse_module_memcpy,
7629e42c5caSLiam Girdwood 
7639e42c5caSLiam Girdwood 	/*Firmware loading */
7649e42c5caSLiam Girdwood 	.load_firmware	= snd_sof_load_firmware_memcpy,
7659e42c5caSLiam Girdwood 
7669e42c5caSLiam Girdwood 	/* DAI drivers */
7679e42c5caSLiam Girdwood 	.drv = byt_dai,
7689e42c5caSLiam Girdwood 	/* all 6 SSPs may be available for cherrytrail */
7699e42c5caSLiam Girdwood 	.num_drv = ARRAY_SIZE(byt_dai),
77027e322faSPierre-Louis Bossart 
77127e322faSPierre-Louis Bossart 	/* ALSA HW info flags */
77227e322faSPierre-Louis Bossart 	.hw_info =	SNDRV_PCM_INFO_MMAP |
77327e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_MMAP_VALID |
77427e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_INTERLEAVED |
77527e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_PAUSE |
77627e322faSPierre-Louis Bossart 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
7779e42c5caSLiam Girdwood };
7789e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_cht_ops);
7799e42c5caSLiam Girdwood 
7809e42c5caSLiam Girdwood const struct sof_intel_dsp_desc cht_chip_info = {
7819e42c5caSLiam Girdwood 	.cores_num = 1,
7829e42c5caSLiam Girdwood 	.cores_mask = 1,
7839e42c5caSLiam Girdwood };
7849e42c5caSLiam Girdwood EXPORT_SYMBOL(cht_chip_info);
7859e42c5caSLiam Girdwood 
7869e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */
7879e42c5caSLiam Girdwood 
7889e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL");
789