1e149ca29SPierre-Louis Bossart // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 188a49cd11SArnd Bergmann #include <sound/soc-acpi.h> 198a49cd11SArnd Bergmann #include <sound/soc-acpi-intel-match.h> 208a49cd11SArnd Bergmann #include <sound/intel-dsp-config.h> 219e42c5caSLiam Girdwood #include "../ops.h" 229e42c5caSLiam Girdwood #include "shim.h" 238a49cd11SArnd Bergmann #include "../sof-acpi-dev.h" 24285880a2SDaniel Baluta #include "../sof-audio.h" 252aae447aSPierre-Louis Bossart #include "../../intel/common/soc-intel-quirks.h" 269e42c5caSLiam Girdwood 279e42c5caSLiam Girdwood /* DSP memories */ 289e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 299e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 309e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 319e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 329e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 33f84337c3SCurtis Malainey #define SHIM_SIZE_BYT 0x100 34f84337c3SCurtis Malainey #define SHIM_SIZE_CHT 0x118 359e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 369e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 379e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 38ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 399e42c5caSLiam Girdwood 409e42c5caSLiam Girdwood /* DSP peripherals */ 419e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 429e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 439e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 449e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 459e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 469e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 479e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 489e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 499e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 509e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 519e42c5caSLiam Girdwood #define SSP_SIZE 0x100 529e42c5caSLiam Girdwood 53*1c5ab2dcSPierre-Louis Bossart #define STACK_DUMP_SIZE 32 549e42c5caSLiam Girdwood 55*1c5ab2dcSPierre-Louis Bossart #define PCI_BAR_SIZE 0x200000 569e42c5caSLiam Girdwood 57*1c5ab2dcSPierre-Louis Bossart #define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 589e42c5caSLiam Girdwood 599e42c5caSLiam Girdwood /* 609e42c5caSLiam Girdwood * Debug 619e42c5caSLiam Girdwood */ 629e42c5caSLiam Girdwood 639e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 649e42c5caSLiam Girdwood 659e42c5caSLiam Girdwood /* BARs */ 66*1c5ab2dcSPierre-Louis Bossart #define DSP_BAR 0 67*1c5ab2dcSPierre-Louis Bossart #define PCI_BAR 1 68*1c5ab2dcSPierre-Louis Bossart #define IMR_BAR 2 699e42c5caSLiam Girdwood 709e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 71*1c5ab2dcSPierre-Louis Bossart {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 73*1c5ab2dcSPierre-Louis Bossart {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 75*1c5ab2dcSPierre-Louis Bossart {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 77*1c5ab2dcSPierre-Louis Bossart {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 79*1c5ab2dcSPierre-Louis Bossart {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE, 809e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 81*1c5ab2dcSPierre-Louis Bossart {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 829e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 83*1c5ab2dcSPierre-Louis Bossart {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 849e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 85*1c5ab2dcSPierre-Louis Bossart {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 869e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 879e42c5caSLiam Girdwood }; 889e42c5caSLiam Girdwood 89*1c5ab2dcSPierre-Louis Bossart static const struct snd_sof_debugfs_map tng_debugfs[] = { 90*1c5ab2dcSPierre-Louis Bossart {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 91*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 92*1c5ab2dcSPierre-Louis Bossart {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 93*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 94*1c5ab2dcSPierre-Louis Bossart {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE, 95*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 96*1c5ab2dcSPierre-Louis Bossart {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE, 97*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 98*1c5ab2dcSPierre-Louis Bossart {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE, 99*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 100*1c5ab2dcSPierre-Louis Bossart {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 101*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_D0_ONLY}, 102*1c5ab2dcSPierre-Louis Bossart {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 103*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_D0_ONLY}, 104*1c5ab2dcSPierre-Louis Bossart {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 105*1c5ab2dcSPierre-Louis Bossart SOF_DEBUGFS_ACCESS_ALWAYS}, 106*1c5ab2dcSPierre-Louis Bossart }; 107*1c5ab2dcSPierre-Louis Bossart 108*1c5ab2dcSPierre-Louis Bossart static void atom_host_done(struct snd_sof_dev *sdev); 109*1c5ab2dcSPierre-Louis Bossart static void atom_dsp_done(struct snd_sof_dev *sdev); 110*1c5ab2dcSPierre-Louis Bossart static void atom_get_reply(struct snd_sof_dev *sdev); 1119e42c5caSLiam Girdwood 1129e42c5caSLiam Girdwood /* 1139e42c5caSLiam Girdwood * Debug 1149e42c5caSLiam Girdwood */ 1159e42c5caSLiam Girdwood 116*1c5ab2dcSPierre-Louis Bossart static void atom_get_registers(struct snd_sof_dev *sdev, 1179e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 1189e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 1199e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 1209e42c5caSLiam Girdwood { 12114104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 12214104eb6SKai Vehmanen 1239e42c5caSLiam Girdwood /* first read regsisters */ 12414104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 12514104eb6SKai Vehmanen 12614104eb6SKai Vehmanen /* note: variable AR register array is not read */ 1279e42c5caSLiam Girdwood 1289e42c5caSLiam Girdwood /* then get panic info */ 129ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 130ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 131ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 132ff2be865SLiam Girdwood return; 133ff2be865SLiam Girdwood } 13414104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 13514104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 1369e42c5caSLiam Girdwood 1379e42c5caSLiam Girdwood /* then get the stack */ 13814104eb6SKai Vehmanen offset += sizeof(*panic_info); 13914104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 1409e42c5caSLiam Girdwood } 1419e42c5caSLiam Girdwood 142*1c5ab2dcSPierre-Louis Bossart static void atom_dump(struct snd_sof_dev *sdev, u32 flags) 1439e42c5caSLiam Girdwood { 1449e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 1459e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 146*1c5ab2dcSPierre-Louis Bossart u32 stack[STACK_DUMP_SIZE]; 147b81eb73bSKeyon Jie u64 status, panic, imrd, imrx; 1489e42c5caSLiam Girdwood 1499e42c5caSLiam Girdwood /* now try generic SOF status messages */ 150*1c5ab2dcSPierre-Louis Bossart status = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD); 151*1c5ab2dcSPierre-Louis Bossart panic = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX); 152*1c5ab2dcSPierre-Louis Bossart atom_get_registers(sdev, &xoops, &panic_info, stack, 153*1c5ab2dcSPierre-Louis Bossart STACK_DUMP_SIZE); 1549e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 155*1c5ab2dcSPierre-Louis Bossart STACK_DUMP_SIZE); 1563a9e204dSLiam Girdwood 1573a9e204dSLiam Girdwood /* provide some context for firmware debug */ 158*1c5ab2dcSPierre-Louis Bossart imrx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRX); 159*1c5ab2dcSPierre-Louis Bossart imrd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRD); 1603a9e204dSLiam Girdwood dev_err(sdev->dev, 161b81eb73bSKeyon Jie "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 162f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 163f9f618e7SPierre-Louis Bossart (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 1643a9e204dSLiam Girdwood dev_err(sdev->dev, 165b81eb73bSKeyon Jie "error: mask host: pending %s complete %s raw 0x%llx\n", 166f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 167f9f618e7SPierre-Louis Bossart (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 1683a9e204dSLiam Girdwood dev_err(sdev->dev, 169b81eb73bSKeyon Jie "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 170f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_BUSY) ? "yes" : "no", 171f9f618e7SPierre-Louis Bossart (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 1723a9e204dSLiam Girdwood dev_err(sdev->dev, 173b81eb73bSKeyon Jie "error: mask DSP: pending %s complete %s raw 0x%llx\n", 174f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 175f9f618e7SPierre-Louis Bossart (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 1763a9e204dSLiam Girdwood 1779e42c5caSLiam Girdwood } 1789e42c5caSLiam Girdwood 1799e42c5caSLiam Girdwood /* 1809e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 1819e42c5caSLiam Girdwood */ 1829e42c5caSLiam Girdwood 183*1c5ab2dcSPierre-Louis Bossart static irqreturn_t atom_irq_handler(int irq, void *context) 1849e42c5caSLiam Girdwood { 1859e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 1863d3d1fb9SPierre-Louis Bossart u64 ipcx, ipcd; 1879e42c5caSLiam Girdwood int ret = IRQ_NONE; 1889e42c5caSLiam Girdwood 189*1c5ab2dcSPierre-Louis Bossart ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX); 190*1c5ab2dcSPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD); 1913d3d1fb9SPierre-Louis Bossart 1923d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 1933d3d1fb9SPierre-Louis Bossart 1943d3d1fb9SPierre-Louis Bossart /* reply message from DSP, Mask Done interrupt first */ 195*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, 1963d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 1973d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE, 1983d3d1fb9SPierre-Louis Bossart SHIM_IMRX_DONE); 1999e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 2003d3d1fb9SPierre-Louis Bossart } 2013d3d1fb9SPierre-Louis Bossart 2023d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 2033d3d1fb9SPierre-Louis Bossart 2043d3d1fb9SPierre-Louis Bossart /* new message from DSP, Mask Busy interrupt first */ 205*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, 2063d3d1fb9SPierre-Louis Bossart SHIM_IMRX, 2073d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY, 2083d3d1fb9SPierre-Louis Bossart SHIM_IMRX_BUSY); 2093d3d1fb9SPierre-Louis Bossart ret = IRQ_WAKE_THREAD; 2103d3d1fb9SPierre-Louis Bossart } 2119e42c5caSLiam Girdwood 2129e42c5caSLiam Girdwood return ret; 2139e42c5caSLiam Girdwood } 2149e42c5caSLiam Girdwood 215*1c5ab2dcSPierre-Louis Bossart static irqreturn_t atom_irq_thread(int irq, void *context) 2169e42c5caSLiam Girdwood { 2179e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 2189e42c5caSLiam Girdwood u64 ipcx, ipcd; 2199e42c5caSLiam Girdwood 220*1c5ab2dcSPierre-Louis Bossart ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX); 221*1c5ab2dcSPierre-Louis Bossart ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD); 2229e42c5caSLiam Girdwood 2239e42c5caSLiam Girdwood /* reply message from DSP */ 2243d3d1fb9SPierre-Louis Bossart if (ipcx & SHIM_BYT_IPCX_DONE) { 2251183e9a6SGuennadi Liakhovetski 2261183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2271183e9a6SGuennadi Liakhovetski 2289e42c5caSLiam Girdwood /* 2299e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 2309e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 2319e42c5caSLiam Girdwood * end of message processing function, else set it here 2329e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 2339e42c5caSLiam Girdwood * which is triggered by msg 2349e42c5caSLiam Girdwood */ 235*1c5ab2dcSPierre-Louis Bossart atom_get_reply(sdev); 2369e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 2379e42c5caSLiam Girdwood 238*1c5ab2dcSPierre-Louis Bossart atom_dsp_done(sdev); 2391183e9a6SGuennadi Liakhovetski 2401183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 2419e42c5caSLiam Girdwood } 2429e42c5caSLiam Girdwood 2439e42c5caSLiam Girdwood /* new message from DSP */ 2443d3d1fb9SPierre-Louis Bossart if (ipcd & SHIM_BYT_IPCD_BUSY) { 2459e42c5caSLiam Girdwood 2469e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 2479e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 248*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_panic(sdev, PANIC_OFFSET(ipcd) + 2499e42c5caSLiam Girdwood MBOX_OFFSET); 2509e42c5caSLiam Girdwood } else { 2519e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 2529e42c5caSLiam Girdwood } 2539e42c5caSLiam Girdwood 254*1c5ab2dcSPierre-Louis Bossart atom_host_done(sdev); 2559e42c5caSLiam Girdwood } 2569e42c5caSLiam Girdwood 2579e42c5caSLiam Girdwood return IRQ_HANDLED; 2589e42c5caSLiam Girdwood } 2599e42c5caSLiam Girdwood 260*1c5ab2dcSPierre-Louis Bossart static int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 2619e42c5caSLiam Girdwood { 2623d2e5c48SKeyon Jie /* unmask and prepare to receive Done interrupt */ 263*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX, 2643d2e5c48SKeyon Jie SHIM_IMRX_DONE, 0); 2653d2e5c48SKeyon Jie 2669e42c5caSLiam Girdwood /* send the message */ 2679e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 2689e42c5caSLiam Girdwood msg->msg_size); 269*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_write64(sdev, DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 2709e42c5caSLiam Girdwood 2719e42c5caSLiam Girdwood return 0; 2729e42c5caSLiam Girdwood } 2739e42c5caSLiam Girdwood 274*1c5ab2dcSPierre-Louis Bossart static void atom_get_reply(struct snd_sof_dev *sdev) 2759e42c5caSLiam Girdwood { 2769e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 2779e42c5caSLiam Girdwood struct sof_ipc_reply reply; 2789e42c5caSLiam Girdwood int ret = 0; 2799e42c5caSLiam Girdwood 2809e42c5caSLiam Girdwood /* 2819e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 2829e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 2839e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 2849e42c5caSLiam Girdwood */ 2859e42c5caSLiam Girdwood if (!msg) { 2869e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 2879e42c5caSLiam Girdwood return; 2889e42c5caSLiam Girdwood } 2899e42c5caSLiam Girdwood 2909e42c5caSLiam Girdwood /* get reply */ 2919e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 2929e42c5caSLiam Girdwood 2939e42c5caSLiam Girdwood if (reply.error < 0) { 2949e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 2959e42c5caSLiam Girdwood ret = reply.error; 2969e42c5caSLiam Girdwood } else { 2979e42c5caSLiam Girdwood /* reply correct size ? */ 2989e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 2999e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 3009e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 3019e42c5caSLiam Girdwood ret = -EINVAL; 3029e42c5caSLiam Girdwood } 3039e42c5caSLiam Girdwood 3049e42c5caSLiam Girdwood /* read the message */ 3059e42c5caSLiam Girdwood if (msg->reply_size > 0) 3069e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 3079e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 3089e42c5caSLiam Girdwood } 3099e42c5caSLiam Girdwood 3109e42c5caSLiam Girdwood msg->reply_error = ret; 3119e42c5caSLiam Girdwood } 3129e42c5caSLiam Girdwood 313*1c5ab2dcSPierre-Louis Bossart static int atom_get_mailbox_offset(struct snd_sof_dev *sdev) 31483ee7ab1SDaniel Baluta { 31583ee7ab1SDaniel Baluta return MBOX_OFFSET; 31683ee7ab1SDaniel Baluta } 31783ee7ab1SDaniel Baluta 318*1c5ab2dcSPierre-Louis Bossart static int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id) 31983ee7ab1SDaniel Baluta { 32083ee7ab1SDaniel Baluta return MBOX_OFFSET; 32183ee7ab1SDaniel Baluta } 32283ee7ab1SDaniel Baluta 323*1c5ab2dcSPierre-Louis Bossart static void atom_host_done(struct snd_sof_dev *sdev) 3249e42c5caSLiam Girdwood { 3259e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 326*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCD, 3279e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 3289e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 3299e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 3309e42c5caSLiam Girdwood 3313d2e5c48SKeyon Jie /* unmask and prepare to receive next new message */ 332*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX, 3339e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 3349e42c5caSLiam Girdwood } 3359e42c5caSLiam Girdwood 336*1c5ab2dcSPierre-Louis Bossart static void atom_dsp_done(struct snd_sof_dev *sdev) 3379e42c5caSLiam Girdwood { 3389e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 339*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCX, 3409e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 3419e42c5caSLiam Girdwood } 3429e42c5caSLiam Girdwood 3439e42c5caSLiam Girdwood /* 3449e42c5caSLiam Girdwood * DSP control. 3459e42c5caSLiam Girdwood */ 3469e42c5caSLiam Girdwood 347*1c5ab2dcSPierre-Louis Bossart static int atom_run(struct snd_sof_dev *sdev) 3489e42c5caSLiam Girdwood { 3499e42c5caSLiam Girdwood int tries = 10; 3509e42c5caSLiam Girdwood 3519e42c5caSLiam Girdwood /* release stall and wait to unstall */ 352*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR, 3539e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 3549e42c5caSLiam Girdwood while (tries--) { 355*1c5ab2dcSPierre-Louis Bossart if (!(snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_CSR) & 3569e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 3579e42c5caSLiam Girdwood break; 3589e42c5caSLiam Girdwood msleep(100); 3599e42c5caSLiam Girdwood } 3609e42c5caSLiam Girdwood if (tries < 0) { 3619e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 362*1c5ab2dcSPierre-Louis Bossart atom_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX); 3639e42c5caSLiam Girdwood return -ENODEV; 3649e42c5caSLiam Girdwood } 3659e42c5caSLiam Girdwood 3669e42c5caSLiam Girdwood /* return init core mask */ 3679e42c5caSLiam Girdwood return 1; 3689e42c5caSLiam Girdwood } 3699e42c5caSLiam Girdwood 370*1c5ab2dcSPierre-Louis Bossart static int atom_reset(struct snd_sof_dev *sdev) 3719e42c5caSLiam Girdwood { 3729e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 373*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR, 3749e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3759e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 3769e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 3779e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 3789e42c5caSLiam Girdwood 3799e42c5caSLiam Girdwood usleep_range(10, 15); 3809e42c5caSLiam Girdwood 3819e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 382*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR, 3839e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 3849e42c5caSLiam Girdwood 3859e42c5caSLiam Girdwood return 0; 3869e42c5caSLiam Girdwood } 3879e42c5caSLiam Girdwood 3882aae447aSPierre-Louis Bossart static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 3892aae447aSPierre-Louis Bossart const char *sof_tplg_filename, 3902aae447aSPierre-Louis Bossart const char *ssp_str) 3912aae447aSPierre-Louis Bossart { 3922aae447aSPierre-Louis Bossart const char *tplg_filename = NULL; 3932aae447aSPierre-Louis Bossart char *filename; 3942aae447aSPierre-Louis Bossart char *split_ext; 3952aae447aSPierre-Louis Bossart 3962aae447aSPierre-Louis Bossart filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 3972aae447aSPierre-Louis Bossart if (!filename) 3982aae447aSPierre-Louis Bossart return NULL; 3992aae447aSPierre-Louis Bossart 4002aae447aSPierre-Louis Bossart /* this assumes a .tplg extension */ 4012aae447aSPierre-Louis Bossart split_ext = strsep(&filename, "."); 4022aae447aSPierre-Louis Bossart if (split_ext) { 4032aae447aSPierre-Louis Bossart tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 4042aae447aSPierre-Louis Bossart "%s-%s.tplg", 4052aae447aSPierre-Louis Bossart split_ext, ssp_str); 4062aae447aSPierre-Louis Bossart if (!tplg_filename) 4072aae447aSPierre-Louis Bossart return NULL; 4082aae447aSPierre-Louis Bossart } 4092aae447aSPierre-Louis Bossart return tplg_filename; 4102aae447aSPierre-Louis Bossart } 4112aae447aSPierre-Louis Bossart 412*1c5ab2dcSPierre-Louis Bossart static void atom_machine_select(struct snd_sof_dev *sdev) 413285880a2SDaniel Baluta { 414285880a2SDaniel Baluta struct snd_sof_pdata *sof_pdata = sdev->pdata; 415285880a2SDaniel Baluta const struct sof_dev_desc *desc = sof_pdata->desc; 416285880a2SDaniel Baluta struct snd_soc_acpi_mach *mach; 4172aae447aSPierre-Louis Bossart struct platform_device *pdev; 4182aae447aSPierre-Louis Bossart const char *tplg_filename; 419285880a2SDaniel Baluta 420285880a2SDaniel Baluta mach = snd_soc_acpi_find_machine(desc->machines); 421285880a2SDaniel Baluta if (!mach) { 422285880a2SDaniel Baluta dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 423285880a2SDaniel Baluta return; 424285880a2SDaniel Baluta } 425285880a2SDaniel Baluta 4262aae447aSPierre-Louis Bossart pdev = to_platform_device(sdev->dev); 4272aae447aSPierre-Louis Bossart if (soc_intel_is_byt_cr(pdev)) { 4282aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4292aae447aSPierre-Louis Bossart "BYT-CR detected, SSP0 used instead of SSP2\n"); 4302aae447aSPierre-Louis Bossart 4312aae447aSPierre-Louis Bossart tplg_filename = fixup_tplg_name(sdev, 4322aae447aSPierre-Louis Bossart mach->sof_tplg_filename, 4332aae447aSPierre-Louis Bossart "ssp0"); 4342aae447aSPierre-Louis Bossart } else { 4352aae447aSPierre-Louis Bossart tplg_filename = mach->sof_tplg_filename; 4362aae447aSPierre-Louis Bossart } 4372aae447aSPierre-Louis Bossart 4382aae447aSPierre-Louis Bossart if (!tplg_filename) { 4392aae447aSPierre-Louis Bossart dev_dbg(sdev->dev, 4402aae447aSPierre-Louis Bossart "error: no topology filename\n"); 4412aae447aSPierre-Louis Bossart return; 4422aae447aSPierre-Louis Bossart } 4432aae447aSPierre-Louis Bossart 4442aae447aSPierre-Louis Bossart sof_pdata->tplg_filename = tplg_filename; 445285880a2SDaniel Baluta mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 446285880a2SDaniel Baluta sof_pdata->machine = mach; 447285880a2SDaniel Baluta } 448285880a2SDaniel Baluta 449*1c5ab2dcSPierre-Louis Bossart /* Atom DAIs */ 450*1c5ab2dcSPierre-Louis Bossart static struct snd_soc_dai_driver atom_dai[] = { 4519e42c5caSLiam Girdwood { 4529e42c5caSLiam Girdwood .name = "ssp0-port", 4538c05246cSPierre-Louis Bossart .playback = { 4548c05246cSPierre-Louis Bossart .channels_min = 1, 4558c05246cSPierre-Louis Bossart .channels_max = 8, 4568c05246cSPierre-Louis Bossart }, 4578c05246cSPierre-Louis Bossart .capture = { 4588c05246cSPierre-Louis Bossart .channels_min = 1, 4598c05246cSPierre-Louis Bossart .channels_max = 8, 4608c05246cSPierre-Louis Bossart }, 4619e42c5caSLiam Girdwood }, 4629e42c5caSLiam Girdwood { 4639e42c5caSLiam Girdwood .name = "ssp1-port", 4648c05246cSPierre-Louis Bossart .playback = { 4658c05246cSPierre-Louis Bossart .channels_min = 1, 4668c05246cSPierre-Louis Bossart .channels_max = 8, 4678c05246cSPierre-Louis Bossart }, 4688c05246cSPierre-Louis Bossart .capture = { 4698c05246cSPierre-Louis Bossart .channels_min = 1, 4708c05246cSPierre-Louis Bossart .channels_max = 8, 4718c05246cSPierre-Louis Bossart }, 4729e42c5caSLiam Girdwood }, 4739e42c5caSLiam Girdwood { 4749e42c5caSLiam Girdwood .name = "ssp2-port", 4758c05246cSPierre-Louis Bossart .playback = { 4768c05246cSPierre-Louis Bossart .channels_min = 1, 4778c05246cSPierre-Louis Bossart .channels_max = 8, 4788c05246cSPierre-Louis Bossart }, 4798c05246cSPierre-Louis Bossart .capture = { 4808c05246cSPierre-Louis Bossart .channels_min = 1, 4818c05246cSPierre-Louis Bossart .channels_max = 8, 4828c05246cSPierre-Louis Bossart } 4839e42c5caSLiam Girdwood }, 4849e42c5caSLiam Girdwood { 4859e42c5caSLiam Girdwood .name = "ssp3-port", 4868c05246cSPierre-Louis Bossart .playback = { 4878c05246cSPierre-Louis Bossart .channels_min = 1, 4888c05246cSPierre-Louis Bossart .channels_max = 8, 4898c05246cSPierre-Louis Bossart }, 4908c05246cSPierre-Louis Bossart .capture = { 4918c05246cSPierre-Louis Bossart .channels_min = 1, 4928c05246cSPierre-Louis Bossart .channels_max = 8, 4938c05246cSPierre-Louis Bossart }, 4949e42c5caSLiam Girdwood }, 4959e42c5caSLiam Girdwood { 4969e42c5caSLiam Girdwood .name = "ssp4-port", 4978c05246cSPierre-Louis Bossart .playback = { 4988c05246cSPierre-Louis Bossart .channels_min = 1, 4998c05246cSPierre-Louis Bossart .channels_max = 8, 5008c05246cSPierre-Louis Bossart }, 5018c05246cSPierre-Louis Bossart .capture = { 5028c05246cSPierre-Louis Bossart .channels_min = 1, 5038c05246cSPierre-Louis Bossart .channels_max = 8, 5048c05246cSPierre-Louis Bossart }, 5059e42c5caSLiam Girdwood }, 5069e42c5caSLiam Girdwood { 5079e42c5caSLiam Girdwood .name = "ssp5-port", 5088c05246cSPierre-Louis Bossart .playback = { 5098c05246cSPierre-Louis Bossart .channels_min = 1, 5108c05246cSPierre-Louis Bossart .channels_max = 8, 5118c05246cSPierre-Louis Bossart }, 5128c05246cSPierre-Louis Bossart .capture = { 5138c05246cSPierre-Louis Bossart .channels_min = 1, 5148c05246cSPierre-Louis Bossart .channels_max = 8, 5158c05246cSPierre-Louis Bossart }, 5169e42c5caSLiam Girdwood }, 5179e42c5caSLiam Girdwood }; 5189e42c5caSLiam Girdwood 519*1c5ab2dcSPierre-Louis Bossart static void atom_set_mach_params(const struct snd_soc_acpi_mach *mach, 52017e9d6b0SPierre-Louis Bossart struct snd_sof_dev *sdev) 52117e9d6b0SPierre-Louis Bossart { 522974cccf4SPierre-Louis Bossart struct snd_sof_pdata *pdata = sdev->pdata; 523974cccf4SPierre-Louis Bossart const struct sof_dev_desc *desc = pdata->desc; 52417e9d6b0SPierre-Louis Bossart struct snd_soc_acpi_mach_params *mach_params; 52517e9d6b0SPierre-Louis Bossart 52617e9d6b0SPierre-Louis Bossart mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 52717e9d6b0SPierre-Louis Bossart mach_params->platform = dev_name(sdev->dev); 528974cccf4SPierre-Louis Bossart mach_params->num_dai_drivers = desc->ops->num_drv; 529974cccf4SPierre-Louis Bossart mach_params->dai_drivers = desc->ops->drv; 53017e9d6b0SPierre-Louis Bossart } 53117e9d6b0SPierre-Louis Bossart 5329e42c5caSLiam Girdwood /* 5339e42c5caSLiam Girdwood * Probe and remove. 5349e42c5caSLiam Girdwood */ 5359e42c5caSLiam Girdwood 5369e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 5379e42c5caSLiam Girdwood 5389e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 5399e42c5caSLiam Girdwood { 5409e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5419e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5429e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 5439e42c5caSLiam Girdwood u32 base, size; 5449e42c5caSLiam Girdwood int ret; 5459e42c5caSLiam Girdwood 5469e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5479e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 5489e42c5caSLiam Girdwood if (ret < 0) { 5499e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5509e42c5caSLiam Girdwood return ret; 5519e42c5caSLiam Girdwood } 5529e42c5caSLiam Girdwood 5539e42c5caSLiam Girdwood /* LPE base */ 5549e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 555*1c5ab2dcSPierre-Louis Bossart size = PCI_BAR_SIZE; 5569e42c5caSLiam Girdwood 5579e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 558*1c5ab2dcSPierre-Louis Bossart sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size); 559*1c5ab2dcSPierre-Louis Bossart if (!sdev->bar[DSP_BAR]) { 5609e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5619e42c5caSLiam Girdwood base, size); 5629e42c5caSLiam Girdwood return -ENODEV; 5639e42c5caSLiam Girdwood } 564*1c5ab2dcSPierre-Louis Bossart dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]); 5659e42c5caSLiam Girdwood 5669e42c5caSLiam Girdwood /* IMR base - optional */ 5679e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5689e42c5caSLiam Girdwood goto irq; 5699e42c5caSLiam Girdwood 5709e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 5719e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 5729e42c5caSLiam Girdwood 5739e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 5749e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 5759e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 5769e42c5caSLiam Girdwood goto irq; 5779e42c5caSLiam Girdwood } 5789e42c5caSLiam Girdwood 5799e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 580*1c5ab2dcSPierre-Louis Bossart sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size); 581*1c5ab2dcSPierre-Louis Bossart if (!sdev->bar[IMR_BAR]) { 5829e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 5839e42c5caSLiam Girdwood base, size); 5849e42c5caSLiam Girdwood return -ENODEV; 5859e42c5caSLiam Girdwood } 586*1c5ab2dcSPierre-Louis Bossart dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]); 5879e42c5caSLiam Girdwood 5889e42c5caSLiam Girdwood irq: 5899e42c5caSLiam Girdwood /* register our IRQ */ 5909e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 5919e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 5929e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 593*1c5ab2dcSPierre-Louis Bossart atom_irq_handler, atom_irq_thread, 5949e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 5959e42c5caSLiam Girdwood if (ret < 0) { 5969e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 5979e42c5caSLiam Girdwood sdev->ipc_irq); 5989e42c5caSLiam Girdwood return ret; 5999e42c5caSLiam Girdwood } 6009e42c5caSLiam Girdwood 6013d2e5c48SKeyon Jie /* enable BUSY and disable DONE Interrupt by default */ 602*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 6033d2e5c48SKeyon Jie SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 6043d2e5c48SKeyon Jie SHIM_IMRX_DONE); 6059e42c5caSLiam Girdwood 6069e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 6079e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 6089e42c5caSLiam Girdwood 6099e42c5caSLiam Girdwood return ret; 6109e42c5caSLiam Girdwood } 6119e42c5caSLiam Girdwood 6129e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 6139e42c5caSLiam Girdwood /* device init */ 6149e42c5caSLiam Girdwood .probe = tangier_pci_probe, 6159e42c5caSLiam Girdwood 6169e42c5caSLiam Girdwood /* DSP core boot / reset */ 617*1c5ab2dcSPierre-Louis Bossart .run = atom_run, 618*1c5ab2dcSPierre-Louis Bossart .reset = atom_reset, 6199e42c5caSLiam Girdwood 6209e42c5caSLiam Girdwood /* Register IO */ 6219e42c5caSLiam Girdwood .write = sof_io_write, 6229e42c5caSLiam Girdwood .read = sof_io_read, 6239e42c5caSLiam Girdwood .write64 = sof_io_write64, 6249e42c5caSLiam Girdwood .read64 = sof_io_read64, 6259e42c5caSLiam Girdwood 6269e42c5caSLiam Girdwood /* Block IO */ 6279e42c5caSLiam Girdwood .block_read = sof_block_read, 6289e42c5caSLiam Girdwood .block_write = sof_block_write, 6299e42c5caSLiam Girdwood 6309e42c5caSLiam Girdwood /* doorbell */ 631*1c5ab2dcSPierre-Louis Bossart .irq_handler = atom_irq_handler, 632*1c5ab2dcSPierre-Louis Bossart .irq_thread = atom_irq_thread, 6339e42c5caSLiam Girdwood 6349e42c5caSLiam Girdwood /* ipc */ 635*1c5ab2dcSPierre-Louis Bossart .send_msg = atom_send_msg, 63683ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 637*1c5ab2dcSPierre-Louis Bossart .get_mailbox_offset = atom_get_mailbox_offset, 638*1c5ab2dcSPierre-Louis Bossart .get_window_offset = atom_get_window_offset, 6399e42c5caSLiam Girdwood 6409e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6419e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6429e42c5caSLiam Girdwood 643285880a2SDaniel Baluta /* machine driver */ 644*1c5ab2dcSPierre-Louis Bossart .machine_select = atom_machine_select, 645285880a2SDaniel Baluta .machine_register = sof_machine_register, 646285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 647*1c5ab2dcSPierre-Louis Bossart .set_mach_params = atom_set_mach_params, 648285880a2SDaniel Baluta 6499e42c5caSLiam Girdwood /* debug */ 650*1c5ab2dcSPierre-Louis Bossart .debug_map = tng_debugfs, 651*1c5ab2dcSPierre-Louis Bossart .debug_map_count = ARRAY_SIZE(tng_debugfs), 652*1c5ab2dcSPierre-Louis Bossart .dbg_dump = atom_dump, 6539e42c5caSLiam Girdwood 6549e42c5caSLiam Girdwood /* stream callbacks */ 6559e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6569e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6579e42c5caSLiam Girdwood 6589e42c5caSLiam Girdwood /* module loading */ 6599e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6609e42c5caSLiam Girdwood 6619e42c5caSLiam Girdwood /*Firmware loading */ 6629e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6639e42c5caSLiam Girdwood 6649e42c5caSLiam Girdwood /* DAI drivers */ 665*1c5ab2dcSPierre-Louis Bossart .drv = atom_dai, 6669e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 66727e322faSPierre-Louis Bossart 66827e322faSPierre-Louis Bossart /* ALSA HW info flags */ 66927e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 67027e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 67127e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 67227e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 6734c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 6740f501c7cSPierre-Louis Bossart 6750f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 6769e42c5caSLiam Girdwood }; 677e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 6789e42c5caSLiam Girdwood 6799e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 6809e42c5caSLiam Girdwood .cores_num = 1, 68164b96917SRanjani Sridharan .host_managed_cores_mask = 1, 6829e42c5caSLiam Girdwood }; 683e42b1945SPierre-Louis Bossart EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 6849e42c5caSLiam Girdwood 6859e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 6869e42c5caSLiam Girdwood 6879e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 6889e42c5caSLiam Girdwood 689af89e7daSPierre-Louis Bossart static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 690af89e7daSPierre-Louis Bossart { 691af89e7daSPierre-Louis Bossart /* Disable Interrupt from both sides */ 692*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3); 693*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3); 694af89e7daSPierre-Louis Bossart 695af89e7daSPierre-Louis Bossart /* Put DSP into reset, set reset vector */ 696*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR, 697af89e7daSPierre-Louis Bossart SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 698af89e7daSPierre-Louis Bossart SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 699af89e7daSPierre-Louis Bossart } 700af89e7daSPierre-Louis Bossart 701af89e7daSPierre-Louis Bossart static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 702af89e7daSPierre-Louis Bossart { 703af89e7daSPierre-Louis Bossart byt_reset_dsp_disable_int(sdev); 704af89e7daSPierre-Louis Bossart 705af89e7daSPierre-Louis Bossart return 0; 706af89e7daSPierre-Louis Bossart } 707af89e7daSPierre-Louis Bossart 708af89e7daSPierre-Louis Bossart static int byt_resume(struct snd_sof_dev *sdev) 709af89e7daSPierre-Louis Bossart { 710af89e7daSPierre-Louis Bossart /* enable BUSY and disable DONE Interrupt by default */ 711*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 712af89e7daSPierre-Louis Bossart SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 713af89e7daSPierre-Louis Bossart SHIM_IMRX_DONE); 714af89e7daSPierre-Louis Bossart 715af89e7daSPierre-Louis Bossart return 0; 716af89e7daSPierre-Louis Bossart } 717af89e7daSPierre-Louis Bossart 718af89e7daSPierre-Louis Bossart static int byt_remove(struct snd_sof_dev *sdev) 719af89e7daSPierre-Louis Bossart { 720af89e7daSPierre-Louis Bossart byt_reset_dsp_disable_int(sdev); 721af89e7daSPierre-Louis Bossart 722af89e7daSPierre-Louis Bossart return 0; 723af89e7daSPierre-Louis Bossart } 724af89e7daSPierre-Louis Bossart 72528d4adc4SYueHaibing static const struct snd_sof_debugfs_map cht_debugfs[] = { 726*1c5ab2dcSPierre-Louis Bossart {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 72728d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 728*1c5ab2dcSPierre-Louis Bossart {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 72928d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 730*1c5ab2dcSPierre-Louis Bossart {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 73128d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 732*1c5ab2dcSPierre-Louis Bossart {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE, 73328d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 734*1c5ab2dcSPierre-Louis Bossart {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE, 73528d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 736*1c5ab2dcSPierre-Louis Bossart {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE, 73728d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 738*1c5ab2dcSPierre-Louis Bossart {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE, 73928d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 740*1c5ab2dcSPierre-Louis Bossart {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE, 74128d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 742*1c5ab2dcSPierre-Louis Bossart {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE, 74328d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 744*1c5ab2dcSPierre-Louis Bossart {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 74528d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 746*1c5ab2dcSPierre-Louis Bossart {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 74728d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_D0_ONLY}, 748*1c5ab2dcSPierre-Louis Bossart {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 74928d4adc4SYueHaibing SOF_DEBUGFS_ACCESS_ALWAYS}, 75028d4adc4SYueHaibing }; 75128d4adc4SYueHaibing 7529e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 7539e42c5caSLiam Girdwood { 7549e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 7559e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 7569e42c5caSLiam Girdwood struct platform_device *pdev = 7579e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 7589e42c5caSLiam Girdwood struct resource *mmio; 7599e42c5caSLiam Girdwood u32 base, size; 7609e42c5caSLiam Girdwood int ret; 7619e42c5caSLiam Girdwood 7629e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 7639e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 7649e42c5caSLiam Girdwood if (ret < 0) { 7659e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 7669e42c5caSLiam Girdwood return ret; 7679e42c5caSLiam Girdwood } 7689e42c5caSLiam Girdwood 7699e42c5caSLiam Girdwood /* LPE base */ 7709e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7719e42c5caSLiam Girdwood desc->resindex_lpe_base); 7729e42c5caSLiam Girdwood if (mmio) { 7739e42c5caSLiam Girdwood base = mmio->start; 7749e42c5caSLiam Girdwood size = resource_size(mmio); 7759e42c5caSLiam Girdwood } else { 7769e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 7779e42c5caSLiam Girdwood desc->resindex_lpe_base); 7789e42c5caSLiam Girdwood return -EINVAL; 7799e42c5caSLiam Girdwood } 7809e42c5caSLiam Girdwood 7819e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 782*1c5ab2dcSPierre-Louis Bossart sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size); 783*1c5ab2dcSPierre-Louis Bossart if (!sdev->bar[DSP_BAR]) { 7849e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 7859e42c5caSLiam Girdwood base, size); 7869e42c5caSLiam Girdwood return -ENODEV; 7879e42c5caSLiam Girdwood } 788*1c5ab2dcSPierre-Louis Bossart dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]); 7899e42c5caSLiam Girdwood 7909e42c5caSLiam Girdwood /* TODO: add offsets */ 791*1c5ab2dcSPierre-Louis Bossart sdev->mmio_bar = DSP_BAR; 792*1c5ab2dcSPierre-Louis Bossart sdev->mailbox_bar = DSP_BAR; 7939e42c5caSLiam Girdwood 7949e42c5caSLiam Girdwood /* IMR base - optional */ 7959e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 7969e42c5caSLiam Girdwood goto irq; 7979e42c5caSLiam Girdwood 7989e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7999e42c5caSLiam Girdwood desc->resindex_imr_base); 8009e42c5caSLiam Girdwood if (mmio) { 8019e42c5caSLiam Girdwood base = mmio->start; 8029e42c5caSLiam Girdwood size = resource_size(mmio); 8039e42c5caSLiam Girdwood } else { 8049e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 8059e42c5caSLiam Girdwood desc->resindex_imr_base); 8069e42c5caSLiam Girdwood return -ENODEV; 8079e42c5caSLiam Girdwood } 8089e42c5caSLiam Girdwood 8099e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 8109e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 8119e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 8129e42c5caSLiam Girdwood goto irq; 8139e42c5caSLiam Girdwood } 8149e42c5caSLiam Girdwood 8159e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 816*1c5ab2dcSPierre-Louis Bossart sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size); 817*1c5ab2dcSPierre-Louis Bossart if (!sdev->bar[IMR_BAR]) { 8189e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 8199e42c5caSLiam Girdwood base, size); 8209e42c5caSLiam Girdwood return -ENODEV; 8219e42c5caSLiam Girdwood } 822*1c5ab2dcSPierre-Louis Bossart dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]); 8239e42c5caSLiam Girdwood 8249e42c5caSLiam Girdwood irq: 8259e42c5caSLiam Girdwood /* register our IRQ */ 8269e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 827cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 8289e42c5caSLiam Girdwood return sdev->ipc_irq; 8299e42c5caSLiam Girdwood 8309e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 8319e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 832*1c5ab2dcSPierre-Louis Bossart atom_irq_handler, atom_irq_thread, 8339e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 8349e42c5caSLiam Girdwood if (ret < 0) { 8359e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 8369e42c5caSLiam Girdwood sdev->ipc_irq); 8379e42c5caSLiam Girdwood return ret; 8389e42c5caSLiam Girdwood } 8399e42c5caSLiam Girdwood 8403d2e5c48SKeyon Jie /* enable BUSY and disable DONE Interrupt by default */ 841*1c5ab2dcSPierre-Louis Bossart snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 8423d2e5c48SKeyon Jie SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 8433d2e5c48SKeyon Jie SHIM_IMRX_DONE); 8449e42c5caSLiam Girdwood 8459e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 8469e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 8479e42c5caSLiam Girdwood 8489e42c5caSLiam Girdwood return ret; 8499e42c5caSLiam Girdwood } 8509e42c5caSLiam Girdwood 8519e42c5caSLiam Girdwood /* baytrail ops */ 8528a49cd11SArnd Bergmann static const struct snd_sof_dsp_ops sof_byt_ops = { 8539e42c5caSLiam Girdwood /* device init */ 8549e42c5caSLiam Girdwood .probe = byt_acpi_probe, 855c691f0c6SRanjani Sridharan .remove = byt_remove, 8569e42c5caSLiam Girdwood 8579e42c5caSLiam Girdwood /* DSP core boot / reset */ 858*1c5ab2dcSPierre-Louis Bossart .run = atom_run, 859*1c5ab2dcSPierre-Louis Bossart .reset = atom_reset, 8609e42c5caSLiam Girdwood 8619e42c5caSLiam Girdwood /* Register IO */ 8629e42c5caSLiam Girdwood .write = sof_io_write, 8639e42c5caSLiam Girdwood .read = sof_io_read, 8649e42c5caSLiam Girdwood .write64 = sof_io_write64, 8659e42c5caSLiam Girdwood .read64 = sof_io_read64, 8669e42c5caSLiam Girdwood 8679e42c5caSLiam Girdwood /* Block IO */ 8689e42c5caSLiam Girdwood .block_read = sof_block_read, 8699e42c5caSLiam Girdwood .block_write = sof_block_write, 8709e42c5caSLiam Girdwood 8719e42c5caSLiam Girdwood /* doorbell */ 872*1c5ab2dcSPierre-Louis Bossart .irq_handler = atom_irq_handler, 873*1c5ab2dcSPierre-Louis Bossart .irq_thread = atom_irq_thread, 8749e42c5caSLiam Girdwood 8759e42c5caSLiam Girdwood /* ipc */ 876*1c5ab2dcSPierre-Louis Bossart .send_msg = atom_send_msg, 87783ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 878*1c5ab2dcSPierre-Louis Bossart .get_mailbox_offset = atom_get_mailbox_offset, 879*1c5ab2dcSPierre-Louis Bossart .get_window_offset = atom_get_window_offset, 8809e42c5caSLiam Girdwood 8819e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8829e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8839e42c5caSLiam Girdwood 884285880a2SDaniel Baluta /* machine driver */ 885*1c5ab2dcSPierre-Louis Bossart .machine_select = atom_machine_select, 886285880a2SDaniel Baluta .machine_register = sof_machine_register, 887285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 888*1c5ab2dcSPierre-Louis Bossart .set_mach_params = atom_set_mach_params, 889285880a2SDaniel Baluta 8909e42c5caSLiam Girdwood /* debug */ 8919e42c5caSLiam Girdwood .debug_map = byt_debugfs, 8929e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 893*1c5ab2dcSPierre-Louis Bossart .dbg_dump = atom_dump, 8949e42c5caSLiam Girdwood 8959e42c5caSLiam Girdwood /* stream callbacks */ 8969e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 8979e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 8989e42c5caSLiam Girdwood 8999e42c5caSLiam Girdwood /* module loading */ 9009e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 9019e42c5caSLiam Girdwood 9029e42c5caSLiam Girdwood /*Firmware loading */ 9039e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 9049e42c5caSLiam Girdwood 905ddcccd54SRanjani Sridharan /* PM */ 906ddcccd54SRanjani Sridharan .suspend = byt_suspend, 907ddcccd54SRanjani Sridharan .resume = byt_resume, 908ddcccd54SRanjani Sridharan 9099e42c5caSLiam Girdwood /* DAI drivers */ 910*1c5ab2dcSPierre-Louis Bossart .drv = atom_dai, 9119e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 91227e322faSPierre-Louis Bossart 91327e322faSPierre-Louis Bossart /* ALSA HW info flags */ 91427e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 91527e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 91627e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 91727e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 9184c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 9190f501c7cSPierre-Louis Bossart 9200f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 9219e42c5caSLiam Girdwood }; 9229e42c5caSLiam Girdwood 9238a49cd11SArnd Bergmann static const struct sof_intel_dsp_desc byt_chip_info = { 9249e42c5caSLiam Girdwood .cores_num = 1, 92564b96917SRanjani Sridharan .host_managed_cores_mask = 1, 9269e42c5caSLiam Girdwood }; 9279e42c5caSLiam Girdwood 9289e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 9298a49cd11SArnd Bergmann static const struct snd_sof_dsp_ops sof_cht_ops = { 9309e42c5caSLiam Girdwood /* device init */ 9319e42c5caSLiam Girdwood .probe = byt_acpi_probe, 932c691f0c6SRanjani Sridharan .remove = byt_remove, 9339e42c5caSLiam Girdwood 9349e42c5caSLiam Girdwood /* DSP core boot / reset */ 935*1c5ab2dcSPierre-Louis Bossart .run = atom_run, 936*1c5ab2dcSPierre-Louis Bossart .reset = atom_reset, 9379e42c5caSLiam Girdwood 9389e42c5caSLiam Girdwood /* Register IO */ 9399e42c5caSLiam Girdwood .write = sof_io_write, 9409e42c5caSLiam Girdwood .read = sof_io_read, 9419e42c5caSLiam Girdwood .write64 = sof_io_write64, 9429e42c5caSLiam Girdwood .read64 = sof_io_read64, 9439e42c5caSLiam Girdwood 9449e42c5caSLiam Girdwood /* Block IO */ 9459e42c5caSLiam Girdwood .block_read = sof_block_read, 9469e42c5caSLiam Girdwood .block_write = sof_block_write, 9479e42c5caSLiam Girdwood 9489e42c5caSLiam Girdwood /* doorbell */ 949*1c5ab2dcSPierre-Louis Bossart .irq_handler = atom_irq_handler, 950*1c5ab2dcSPierre-Louis Bossart .irq_thread = atom_irq_thread, 9519e42c5caSLiam Girdwood 9529e42c5caSLiam Girdwood /* ipc */ 953*1c5ab2dcSPierre-Louis Bossart .send_msg = atom_send_msg, 95483ee7ab1SDaniel Baluta .fw_ready = sof_fw_ready, 955*1c5ab2dcSPierre-Louis Bossart .get_mailbox_offset = atom_get_mailbox_offset, 956*1c5ab2dcSPierre-Louis Bossart .get_window_offset = atom_get_window_offset, 9579e42c5caSLiam Girdwood 9589e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 9599e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 9609e42c5caSLiam Girdwood 961285880a2SDaniel Baluta /* machine driver */ 962*1c5ab2dcSPierre-Louis Bossart .machine_select = atom_machine_select, 963285880a2SDaniel Baluta .machine_register = sof_machine_register, 964285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 965*1c5ab2dcSPierre-Louis Bossart .set_mach_params = atom_set_mach_params, 966285880a2SDaniel Baluta 9679e42c5caSLiam Girdwood /* debug */ 9689e42c5caSLiam Girdwood .debug_map = cht_debugfs, 9699e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 970*1c5ab2dcSPierre-Louis Bossart .dbg_dump = atom_dump, 9719e42c5caSLiam Girdwood 9729e42c5caSLiam Girdwood /* stream callbacks */ 9739e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 9749e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 9759e42c5caSLiam Girdwood 9769e42c5caSLiam Girdwood /* module loading */ 9779e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 9789e42c5caSLiam Girdwood 9799e42c5caSLiam Girdwood /*Firmware loading */ 9809e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 9819e42c5caSLiam Girdwood 982ddcccd54SRanjani Sridharan /* PM */ 983ddcccd54SRanjani Sridharan .suspend = byt_suspend, 984ddcccd54SRanjani Sridharan .resume = byt_resume, 985ddcccd54SRanjani Sridharan 9869e42c5caSLiam Girdwood /* DAI drivers */ 987*1c5ab2dcSPierre-Louis Bossart .drv = atom_dai, 9889e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 989*1c5ab2dcSPierre-Louis Bossart .num_drv = 6, 99027e322faSPierre-Louis Bossart 99127e322faSPierre-Louis Bossart /* ALSA HW info flags */ 99227e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 99327e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 99427e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 99527e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 9964c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 9970f501c7cSPierre-Louis Bossart 9980f501c7cSPierre-Louis Bossart .arch_ops = &sof_xtensa_arch_ops, 9999e42c5caSLiam Girdwood }; 10009e42c5caSLiam Girdwood 10018a49cd11SArnd Bergmann static const struct sof_intel_dsp_desc cht_chip_info = { 10029e42c5caSLiam Girdwood .cores_num = 1, 100364b96917SRanjani Sridharan .host_managed_cores_mask = 1, 10049e42c5caSLiam Girdwood }; 10058a49cd11SArnd Bergmann 10068a49cd11SArnd Bergmann /* BYTCR uses different IRQ index */ 10078a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { 10088a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_baytrail_machines, 10098a49cd11SArnd Bergmann .resindex_lpe_base = 0, 10108a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 10118a49cd11SArnd Bergmann .resindex_imr_base = 2, 10128a49cd11SArnd Bergmann .irqindex_host_ipc = 0, 10138a49cd11SArnd Bergmann .chip_info = &byt_chip_info, 10148a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 10158a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 10168a49cd11SArnd Bergmann .default_fw_filename = "sof-byt.ri", 10178a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 10188a49cd11SArnd Bergmann .ops = &sof_byt_ops, 10198a49cd11SArnd Bergmann }; 10208a49cd11SArnd Bergmann 10218a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_baytrail_desc = { 10228a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_baytrail_machines, 10238a49cd11SArnd Bergmann .resindex_lpe_base = 0, 10248a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 10258a49cd11SArnd Bergmann .resindex_imr_base = 2, 10268a49cd11SArnd Bergmann .irqindex_host_ipc = 5, 10278a49cd11SArnd Bergmann .chip_info = &byt_chip_info, 10288a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 10298a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 10308a49cd11SArnd Bergmann .default_fw_filename = "sof-byt.ri", 10318a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 10328a49cd11SArnd Bergmann .ops = &sof_byt_ops, 10338a49cd11SArnd Bergmann }; 10348a49cd11SArnd Bergmann 10358a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { 10368a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_cherrytrail_machines, 10378a49cd11SArnd Bergmann .resindex_lpe_base = 0, 10388a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 10398a49cd11SArnd Bergmann .resindex_imr_base = 2, 10408a49cd11SArnd Bergmann .irqindex_host_ipc = 5, 10418a49cd11SArnd Bergmann .chip_info = &cht_chip_info, 10428a49cd11SArnd Bergmann .default_fw_path = "intel/sof", 10438a49cd11SArnd Bergmann .default_tplg_path = "intel/sof-tplg", 10448a49cd11SArnd Bergmann .default_fw_filename = "sof-cht.ri", 10458a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-cht-nocodec.tplg", 10468a49cd11SArnd Bergmann .ops = &sof_cht_ops, 10478a49cd11SArnd Bergmann }; 10488a49cd11SArnd Bergmann 10498a49cd11SArnd Bergmann static const struct acpi_device_id sof_baytrail_match[] = { 10508a49cd11SArnd Bergmann { "80860F28", (unsigned long)&sof_acpi_baytrail_desc }, 10518a49cd11SArnd Bergmann { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc }, 10528a49cd11SArnd Bergmann { } 10538a49cd11SArnd Bergmann }; 10548a49cd11SArnd Bergmann MODULE_DEVICE_TABLE(acpi, sof_baytrail_match); 10558a49cd11SArnd Bergmann 10568a49cd11SArnd Bergmann static int sof_baytrail_probe(struct platform_device *pdev) 10578a49cd11SArnd Bergmann { 10588a49cd11SArnd Bergmann struct device *dev = &pdev->dev; 10598a49cd11SArnd Bergmann const struct sof_dev_desc *desc; 10608a49cd11SArnd Bergmann const struct acpi_device_id *id; 10618a49cd11SArnd Bergmann int ret; 10628a49cd11SArnd Bergmann 10638a49cd11SArnd Bergmann id = acpi_match_device(dev->driver->acpi_match_table, dev); 10648a49cd11SArnd Bergmann if (!id) 10658a49cd11SArnd Bergmann return -ENODEV; 10668a49cd11SArnd Bergmann 10678a49cd11SArnd Bergmann ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 10688a49cd11SArnd Bergmann if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 10698a49cd11SArnd Bergmann dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 10708a49cd11SArnd Bergmann return -ENODEV; 10718a49cd11SArnd Bergmann } 10728a49cd11SArnd Bergmann 10738a49cd11SArnd Bergmann desc = device_get_match_data(&pdev->dev); 10748a49cd11SArnd Bergmann if (!desc) 10758a49cd11SArnd Bergmann return -ENODEV; 10768a49cd11SArnd Bergmann 10778a49cd11SArnd Bergmann if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) 10788a49cd11SArnd Bergmann desc = &sof_acpi_baytrailcr_desc; 10798a49cd11SArnd Bergmann 10808a49cd11SArnd Bergmann return sof_acpi_probe(pdev, desc); 10818a49cd11SArnd Bergmann } 10828a49cd11SArnd Bergmann 10838a49cd11SArnd Bergmann /* acpi_driver definition */ 10848a49cd11SArnd Bergmann static struct platform_driver snd_sof_acpi_intel_byt_driver = { 10858a49cd11SArnd Bergmann .probe = sof_baytrail_probe, 10868a49cd11SArnd Bergmann .remove = sof_acpi_remove, 10878a49cd11SArnd Bergmann .driver = { 10888a49cd11SArnd Bergmann .name = "sof-audio-acpi-intel-byt", 10898a49cd11SArnd Bergmann .pm = &sof_acpi_pm, 10908a49cd11SArnd Bergmann .acpi_match_table = sof_baytrail_match, 10918a49cd11SArnd Bergmann }, 10928a49cd11SArnd Bergmann }; 10938a49cd11SArnd Bergmann module_platform_driver(snd_sof_acpi_intel_byt_driver); 10949e42c5caSLiam Girdwood 10959e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 10969e42c5caSLiam Girdwood 10979e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 1098f4483a0fSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 1099068ac0dbSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 11008a49cd11SArnd Bergmann MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 1101