19e42c5caSLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 29e42c5caSLiam Girdwood // 39e42c5caSLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 49e42c5caSLiam Girdwood // redistributing this file, you may do so under either license. 59e42c5caSLiam Girdwood // 69e42c5caSLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 79e42c5caSLiam Girdwood // 89e42c5caSLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 99e42c5caSLiam Girdwood // 109e42c5caSLiam Girdwood 119e42c5caSLiam Girdwood /* 129e42c5caSLiam Girdwood * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 139e42c5caSLiam Girdwood */ 149e42c5caSLiam Girdwood 159e42c5caSLiam Girdwood #include <linux/module.h> 169e42c5caSLiam Girdwood #include <sound/sof.h> 179e42c5caSLiam Girdwood #include <sound/sof/xtensa.h> 189e42c5caSLiam Girdwood #include "../ops.h" 199e42c5caSLiam Girdwood #include "shim.h" 209e42c5caSLiam Girdwood 219e42c5caSLiam Girdwood /* DSP memories */ 229e42c5caSLiam Girdwood #define IRAM_OFFSET 0x0C0000 239e42c5caSLiam Girdwood #define IRAM_SIZE (80 * 1024) 249e42c5caSLiam Girdwood #define DRAM_OFFSET 0x100000 259e42c5caSLiam Girdwood #define DRAM_SIZE (160 * 1024) 269e42c5caSLiam Girdwood #define SHIM_OFFSET 0x140000 279e42c5caSLiam Girdwood #define SHIM_SIZE 0x100 289e42c5caSLiam Girdwood #define MBOX_OFFSET 0x144000 299e42c5caSLiam Girdwood #define MBOX_SIZE 0x1000 309e42c5caSLiam Girdwood #define EXCEPT_OFFSET 0x800 319e42c5caSLiam Girdwood 329e42c5caSLiam Girdwood /* DSP peripherals */ 339e42c5caSLiam Girdwood #define DMAC0_OFFSET 0x098000 349e42c5caSLiam Girdwood #define DMAC1_OFFSET 0x09c000 359e42c5caSLiam Girdwood #define DMAC2_OFFSET 0x094000 369e42c5caSLiam Girdwood #define DMAC_SIZE 0x420 379e42c5caSLiam Girdwood #define SSP0_OFFSET 0x0a0000 389e42c5caSLiam Girdwood #define SSP1_OFFSET 0x0a1000 399e42c5caSLiam Girdwood #define SSP2_OFFSET 0x0a2000 409e42c5caSLiam Girdwood #define SSP3_OFFSET 0x0a4000 419e42c5caSLiam Girdwood #define SSP4_OFFSET 0x0a5000 429e42c5caSLiam Girdwood #define SSP5_OFFSET 0x0a6000 439e42c5caSLiam Girdwood #define SSP_SIZE 0x100 449e42c5caSLiam Girdwood 459e42c5caSLiam Girdwood #define BYT_STACK_DUMP_SIZE 32 469e42c5caSLiam Girdwood 479e42c5caSLiam Girdwood #define BYT_PCI_BAR_SIZE 0x200000 489e42c5caSLiam Girdwood 499e42c5caSLiam Girdwood #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 509e42c5caSLiam Girdwood 519e42c5caSLiam Girdwood /* 529e42c5caSLiam Girdwood * Debug 539e42c5caSLiam Girdwood */ 549e42c5caSLiam Girdwood 559e42c5caSLiam Girdwood #define MBOX_DUMP_SIZE 0x30 569e42c5caSLiam Girdwood 579e42c5caSLiam Girdwood /* BARs */ 589e42c5caSLiam Girdwood #define BYT_DSP_BAR 0 599e42c5caSLiam Girdwood #define BYT_PCI_BAR 1 609e42c5caSLiam Girdwood #define BYT_IMR_BAR 2 619e42c5caSLiam Girdwood 629e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map byt_debugfs[] = { 639e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 649e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 659e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 669e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 679e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 689e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 699e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 709e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 719e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 729e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 739e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 749e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 759e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 779e42c5caSLiam Girdwood {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 789e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 799e42c5caSLiam Girdwood }; 809e42c5caSLiam Girdwood 819e42c5caSLiam Girdwood static const struct snd_sof_debugfs_map cht_debugfs[] = { 829e42c5caSLiam Girdwood {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 839e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 849e42c5caSLiam Girdwood {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 859e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 869e42c5caSLiam Girdwood {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 879e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 889e42c5caSLiam Girdwood {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 899e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 909e42c5caSLiam Girdwood {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 919e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 929e42c5caSLiam Girdwood {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 939e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 949e42c5caSLiam Girdwood {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 959e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 969e42c5caSLiam Girdwood {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 979e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 989e42c5caSLiam Girdwood {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 999e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1009e42c5caSLiam Girdwood {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 1019e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 1029e42c5caSLiam Girdwood {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 1039e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 1049e42c5caSLiam Girdwood {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 1059e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 1069e42c5caSLiam Girdwood }; 1079e42c5caSLiam Girdwood 1089e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev); 1099e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev); 1109e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev); 1119e42c5caSLiam Girdwood 1129e42c5caSLiam Girdwood /* 1139e42c5caSLiam Girdwood * IPC Firmware ready. 1149e42c5caSLiam Girdwood */ 1159e42c5caSLiam Girdwood static void byt_get_windows(struct snd_sof_dev *sdev) 1169e42c5caSLiam Girdwood { 1179e42c5caSLiam Girdwood struct sof_ipc_window_elem *elem; 1189e42c5caSLiam Girdwood u32 outbox_offset = 0; 1199e42c5caSLiam Girdwood u32 stream_offset = 0; 1209e42c5caSLiam Girdwood u32 inbox_offset = 0; 1219e42c5caSLiam Girdwood u32 outbox_size = 0; 1229e42c5caSLiam Girdwood u32 stream_size = 0; 1239e42c5caSLiam Girdwood u32 inbox_size = 0; 1249e42c5caSLiam Girdwood int i; 1259e42c5caSLiam Girdwood 1269e42c5caSLiam Girdwood if (!sdev->info_window) { 1279e42c5caSLiam Girdwood dev_err(sdev->dev, "error: have no window info\n"); 1289e42c5caSLiam Girdwood return; 1299e42c5caSLiam Girdwood } 1309e42c5caSLiam Girdwood 1319e42c5caSLiam Girdwood for (i = 0; i < sdev->info_window->num_windows; i++) { 1329e42c5caSLiam Girdwood elem = &sdev->info_window->window[i]; 1339e42c5caSLiam Girdwood 1349e42c5caSLiam Girdwood switch (elem->type) { 1359e42c5caSLiam Girdwood case SOF_IPC_REGION_UPBOX: 1369e42c5caSLiam Girdwood inbox_offset = elem->offset + MBOX_OFFSET; 1379e42c5caSLiam Girdwood inbox_size = elem->size; 1389e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1399e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1409e42c5caSLiam Girdwood inbox_offset, 1419e42c5caSLiam Girdwood elem->size, "inbox", 1429e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1439e42c5caSLiam Girdwood break; 1449e42c5caSLiam Girdwood case SOF_IPC_REGION_DOWNBOX: 1459e42c5caSLiam Girdwood outbox_offset = elem->offset + MBOX_OFFSET; 1469e42c5caSLiam Girdwood outbox_size = elem->size; 1479e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1489e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1499e42c5caSLiam Girdwood outbox_offset, 1509e42c5caSLiam Girdwood elem->size, "outbox", 1519e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1529e42c5caSLiam Girdwood break; 1539e42c5caSLiam Girdwood case SOF_IPC_REGION_TRACE: 1549e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1559e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1569e42c5caSLiam Girdwood elem->offset + 1579e42c5caSLiam Girdwood MBOX_OFFSET, 1589e42c5caSLiam Girdwood elem->size, "etrace", 1599e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1609e42c5caSLiam Girdwood break; 1619e42c5caSLiam Girdwood case SOF_IPC_REGION_DEBUG: 1629e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1639e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1649e42c5caSLiam Girdwood elem->offset + 1659e42c5caSLiam Girdwood MBOX_OFFSET, 1669e42c5caSLiam Girdwood elem->size, "debug", 1679e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1689e42c5caSLiam Girdwood break; 1699e42c5caSLiam Girdwood case SOF_IPC_REGION_STREAM: 1709e42c5caSLiam Girdwood stream_offset = elem->offset + MBOX_OFFSET; 1719e42c5caSLiam Girdwood stream_size = elem->size; 1729e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1739e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1749e42c5caSLiam Girdwood stream_offset, 1759e42c5caSLiam Girdwood elem->size, "stream", 1769e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1779e42c5caSLiam Girdwood break; 1789e42c5caSLiam Girdwood case SOF_IPC_REGION_REGS: 1799e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1809e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1819e42c5caSLiam Girdwood elem->offset + 1829e42c5caSLiam Girdwood MBOX_OFFSET, 1839e42c5caSLiam Girdwood elem->size, "regs", 1849e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1859e42c5caSLiam Girdwood break; 1869e42c5caSLiam Girdwood case SOF_IPC_REGION_EXCEPTION: 1879e42c5caSLiam Girdwood sdev->dsp_oops_offset = elem->offset + MBOX_OFFSET; 1889e42c5caSLiam Girdwood snd_sof_debugfs_io_item(sdev, 1899e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] + 1909e42c5caSLiam Girdwood elem->offset + 1919e42c5caSLiam Girdwood MBOX_OFFSET, 1929e42c5caSLiam Girdwood elem->size, "exception", 1939e42c5caSLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY); 1949e42c5caSLiam Girdwood break; 1959e42c5caSLiam Girdwood default: 1969e42c5caSLiam Girdwood dev_err(sdev->dev, "error: get illegal window info\n"); 1979e42c5caSLiam Girdwood return; 1989e42c5caSLiam Girdwood } 1999e42c5caSLiam Girdwood } 2009e42c5caSLiam Girdwood 2019e42c5caSLiam Girdwood if (outbox_size == 0 || inbox_size == 0) { 2029e42c5caSLiam Girdwood dev_err(sdev->dev, "error: get illegal mailbox window\n"); 2039e42c5caSLiam Girdwood return; 2049e42c5caSLiam Girdwood } 2059e42c5caSLiam Girdwood 2069e42c5caSLiam Girdwood snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size, 2079e42c5caSLiam Girdwood outbox_offset, outbox_size); 2089e42c5caSLiam Girdwood sdev->stream_box.offset = stream_offset; 2099e42c5caSLiam Girdwood sdev->stream_box.size = stream_size; 2109e42c5caSLiam Girdwood 2119e42c5caSLiam Girdwood dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n", 2129e42c5caSLiam Girdwood inbox_offset, inbox_size); 2139e42c5caSLiam Girdwood dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n", 2149e42c5caSLiam Girdwood outbox_offset, outbox_size); 2159e42c5caSLiam Girdwood dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n", 2169e42c5caSLiam Girdwood stream_offset, stream_size); 2179e42c5caSLiam Girdwood } 2189e42c5caSLiam Girdwood 2199e42c5caSLiam Girdwood /* check for ABI compatibility and create memory windows on first boot */ 2209e42c5caSLiam Girdwood static int byt_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) 2219e42c5caSLiam Girdwood { 2229e42c5caSLiam Girdwood struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready; 2239e42c5caSLiam Girdwood u32 offset; 2249e42c5caSLiam Girdwood int ret; 2259e42c5caSLiam Girdwood 2269e42c5caSLiam Girdwood /* mailbox must be on 4k boundary */ 2279e42c5caSLiam Girdwood offset = MBOX_OFFSET; 2289e42c5caSLiam Girdwood 2299e42c5caSLiam Girdwood dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset 0x%x\n", 2309e42c5caSLiam Girdwood msg_id, offset); 2319e42c5caSLiam Girdwood 2329e42c5caSLiam Girdwood /* no need to re-check version/ABI for subsequent boots */ 2339e42c5caSLiam Girdwood if (!sdev->first_boot) 2349e42c5caSLiam Girdwood return 0; 2359e42c5caSLiam Girdwood 2369e42c5caSLiam Girdwood /* copy data from the DSP FW ready offset */ 2379e42c5caSLiam Girdwood sof_block_read(sdev, sdev->mmio_bar, offset, fw_ready, 2389e42c5caSLiam Girdwood sizeof(*fw_ready)); 2399e42c5caSLiam Girdwood 2409e42c5caSLiam Girdwood snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset, 2419e42c5caSLiam Girdwood fw_ready->dspbox_size, 2429e42c5caSLiam Girdwood fw_ready->hostbox_offset, 2439e42c5caSLiam Girdwood fw_ready->hostbox_size); 2449e42c5caSLiam Girdwood 2459e42c5caSLiam Girdwood /* make sure ABI version is compatible */ 2469e42c5caSLiam Girdwood ret = snd_sof_ipc_valid(sdev); 2479e42c5caSLiam Girdwood if (ret < 0) 2489e42c5caSLiam Girdwood return ret; 2499e42c5caSLiam Girdwood 2509e42c5caSLiam Girdwood /* now check for extended data */ 2519e42c5caSLiam Girdwood snd_sof_fw_parse_ext_data(sdev, sdev->mmio_bar, MBOX_OFFSET + 2529e42c5caSLiam Girdwood sizeof(struct sof_ipc_fw_ready)); 2539e42c5caSLiam Girdwood 2549e42c5caSLiam Girdwood byt_get_windows(sdev); 2559e42c5caSLiam Girdwood 2569e42c5caSLiam Girdwood return 0; 2579e42c5caSLiam Girdwood } 2589e42c5caSLiam Girdwood 2599e42c5caSLiam Girdwood /* 2609e42c5caSLiam Girdwood * Debug 2619e42c5caSLiam Girdwood */ 2629e42c5caSLiam Girdwood 2639e42c5caSLiam Girdwood static void byt_get_registers(struct snd_sof_dev *sdev, 2649e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 2659e42c5caSLiam Girdwood struct sof_ipc_panic_info *panic_info, 2669e42c5caSLiam Girdwood u32 *stack, size_t stack_words) 2679e42c5caSLiam Girdwood { 26814104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 26914104eb6SKai Vehmanen 2709e42c5caSLiam Girdwood /* first read regsisters */ 27114104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 27214104eb6SKai Vehmanen 27314104eb6SKai Vehmanen /* note: variable AR register array is not read */ 2749e42c5caSLiam Girdwood 2759e42c5caSLiam Girdwood /* then get panic info */ 27614104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 27714104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 2789e42c5caSLiam Girdwood 2799e42c5caSLiam Girdwood /* then get the stack */ 28014104eb6SKai Vehmanen offset += sizeof(*panic_info); 28114104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 2829e42c5caSLiam Girdwood } 2839e42c5caSLiam Girdwood 2849e42c5caSLiam Girdwood static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 2859e42c5caSLiam Girdwood { 2869e42c5caSLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 2879e42c5caSLiam Girdwood struct sof_ipc_panic_info panic_info; 2889e42c5caSLiam Girdwood u32 stack[BYT_STACK_DUMP_SIZE]; 2899e42c5caSLiam Girdwood u32 status, panic; 2909e42c5caSLiam Girdwood 2919e42c5caSLiam Girdwood /* now try generic SOF status messages */ 2929e42c5caSLiam Girdwood status = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCD); 2939e42c5caSLiam Girdwood panic = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCX); 2949e42c5caSLiam Girdwood byt_get_registers(sdev, &xoops, &panic_info, stack, 2959e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 2969e42c5caSLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 2979e42c5caSLiam Girdwood BYT_STACK_DUMP_SIZE); 2989e42c5caSLiam Girdwood } 2999e42c5caSLiam Girdwood 3009e42c5caSLiam Girdwood /* 3019e42c5caSLiam Girdwood * IPC Doorbell IRQ handler and thread. 3029e42c5caSLiam Girdwood */ 3039e42c5caSLiam Girdwood 3049e42c5caSLiam Girdwood static irqreturn_t byt_irq_handler(int irq, void *context) 3059e42c5caSLiam Girdwood { 3069e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 3079e42c5caSLiam Girdwood u64 isr; 3089e42c5caSLiam Girdwood int ret = IRQ_NONE; 3099e42c5caSLiam Girdwood 3109e42c5caSLiam Girdwood /* Interrupt arrived, check src */ 3119e42c5caSLiam Girdwood isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX); 3129e42c5caSLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 3139e42c5caSLiam Girdwood ret = IRQ_WAKE_THREAD; 3149e42c5caSLiam Girdwood 3159e42c5caSLiam Girdwood return ret; 3169e42c5caSLiam Girdwood } 3179e42c5caSLiam Girdwood 3189e42c5caSLiam Girdwood static irqreturn_t byt_irq_thread(int irq, void *context) 3199e42c5caSLiam Girdwood { 3209e42c5caSLiam Girdwood struct snd_sof_dev *sdev = context; 3219e42c5caSLiam Girdwood u64 ipcx, ipcd; 3229e42c5caSLiam Girdwood u64 imrx; 3239e42c5caSLiam Girdwood 3249e42c5caSLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 3259e42c5caSLiam Girdwood ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 3269e42c5caSLiam Girdwood 3279e42c5caSLiam Girdwood /* reply message from DSP */ 3289e42c5caSLiam Girdwood if (ipcx & SHIM_BYT_IPCX_DONE && 3299e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 3309e42c5caSLiam Girdwood /* Mask Done interrupt before first */ 3319e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 3329e42c5caSLiam Girdwood SHIM_IMRX, 3339e42c5caSLiam Girdwood SHIM_IMRX_DONE, 3349e42c5caSLiam Girdwood SHIM_IMRX_DONE); 3351183e9a6SGuennadi Liakhovetski 3361183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 3371183e9a6SGuennadi Liakhovetski 3389e42c5caSLiam Girdwood /* 3399e42c5caSLiam Girdwood * handle immediate reply from DSP core. If the msg is 3409e42c5caSLiam Girdwood * found, set done bit in cmd_done which is called at the 3419e42c5caSLiam Girdwood * end of message processing function, else set it here 3429e42c5caSLiam Girdwood * because the done bit can't be set in cmd_done function 3439e42c5caSLiam Girdwood * which is triggered by msg 3449e42c5caSLiam Girdwood */ 3459e42c5caSLiam Girdwood byt_get_reply(sdev); 3469e42c5caSLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 3479e42c5caSLiam Girdwood 3489e42c5caSLiam Girdwood byt_dsp_done(sdev); 3491183e9a6SGuennadi Liakhovetski 3501183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 3519e42c5caSLiam Girdwood } 3529e42c5caSLiam Girdwood 3539e42c5caSLiam Girdwood /* new message from DSP */ 3549e42c5caSLiam Girdwood ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 3559e42c5caSLiam Girdwood if (ipcd & SHIM_BYT_IPCD_BUSY && 3569e42c5caSLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 3579e42c5caSLiam Girdwood /* Mask Busy interrupt before return */ 3589e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 3599e42c5caSLiam Girdwood SHIM_IMRX, 3609e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 3619e42c5caSLiam Girdwood SHIM_IMRX_BUSY); 3629e42c5caSLiam Girdwood 3639e42c5caSLiam Girdwood /* Handle messages from DSP Core */ 3649e42c5caSLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 3659e42c5caSLiam Girdwood snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 3669e42c5caSLiam Girdwood MBOX_OFFSET); 3679e42c5caSLiam Girdwood } else { 3689e42c5caSLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 3699e42c5caSLiam Girdwood } 3709e42c5caSLiam Girdwood 3719e42c5caSLiam Girdwood byt_host_done(sdev); 3729e42c5caSLiam Girdwood } 3739e42c5caSLiam Girdwood 3749e42c5caSLiam Girdwood return IRQ_HANDLED; 3759e42c5caSLiam Girdwood } 3769e42c5caSLiam Girdwood 3779e42c5caSLiam Girdwood static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 3789e42c5caSLiam Girdwood { 3799e42c5caSLiam Girdwood u64 cmd = msg->header; 3809e42c5caSLiam Girdwood 3819e42c5caSLiam Girdwood /* send the message */ 3829e42c5caSLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 3839e42c5caSLiam Girdwood msg->msg_size); 3849e42c5caSLiam Girdwood snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, 3859e42c5caSLiam Girdwood cmd | SHIM_BYT_IPCX_BUSY); 3869e42c5caSLiam Girdwood 3879e42c5caSLiam Girdwood return 0; 3889e42c5caSLiam Girdwood } 3899e42c5caSLiam Girdwood 3909e42c5caSLiam Girdwood static void byt_get_reply(struct snd_sof_dev *sdev) 3919e42c5caSLiam Girdwood { 3929e42c5caSLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 3939e42c5caSLiam Girdwood struct sof_ipc_reply reply; 3949e42c5caSLiam Girdwood int ret = 0; 3959e42c5caSLiam Girdwood 3969e42c5caSLiam Girdwood /* 3979e42c5caSLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 3989e42c5caSLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 3999e42c5caSLiam Girdwood * In this case, the driver must ignore the ipc. 4009e42c5caSLiam Girdwood */ 4019e42c5caSLiam Girdwood if (!msg) { 4029e42c5caSLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 4039e42c5caSLiam Girdwood return; 4049e42c5caSLiam Girdwood } 4059e42c5caSLiam Girdwood 4069e42c5caSLiam Girdwood /* get reply */ 4079e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 4089e42c5caSLiam Girdwood 4099e42c5caSLiam Girdwood if (reply.error < 0) { 4109e42c5caSLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 4119e42c5caSLiam Girdwood ret = reply.error; 4129e42c5caSLiam Girdwood } else { 4139e42c5caSLiam Girdwood /* reply correct size ? */ 4149e42c5caSLiam Girdwood if (reply.hdr.size != msg->reply_size) { 4159e42c5caSLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 4169e42c5caSLiam Girdwood msg->reply_size, reply.hdr.size); 4179e42c5caSLiam Girdwood ret = -EINVAL; 4189e42c5caSLiam Girdwood } 4199e42c5caSLiam Girdwood 4209e42c5caSLiam Girdwood /* read the message */ 4219e42c5caSLiam Girdwood if (msg->reply_size > 0) 4229e42c5caSLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 4239e42c5caSLiam Girdwood msg->reply_data, msg->reply_size); 4249e42c5caSLiam Girdwood } 4259e42c5caSLiam Girdwood 4269e42c5caSLiam Girdwood msg->reply_error = ret; 4279e42c5caSLiam Girdwood } 4289e42c5caSLiam Girdwood 4299e42c5caSLiam Girdwood static void byt_host_done(struct snd_sof_dev *sdev) 4309e42c5caSLiam Girdwood { 4319e42c5caSLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 4329e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 4339e42c5caSLiam Girdwood SHIM_BYT_IPCD_BUSY | 4349e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE, 4359e42c5caSLiam Girdwood SHIM_BYT_IPCD_DONE); 4369e42c5caSLiam Girdwood 4379e42c5caSLiam Girdwood /* unmask busy interrupt */ 4389e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 4399e42c5caSLiam Girdwood SHIM_IMRX_BUSY, 0); 4409e42c5caSLiam Girdwood } 4419e42c5caSLiam Girdwood 4429e42c5caSLiam Girdwood static void byt_dsp_done(struct snd_sof_dev *sdev) 4439e42c5caSLiam Girdwood { 4449e42c5caSLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 4459e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 4469e42c5caSLiam Girdwood SHIM_BYT_IPCX_DONE, 0); 4479e42c5caSLiam Girdwood 4489e42c5caSLiam Girdwood /* unmask Done interrupt */ 4499e42c5caSLiam Girdwood snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 4509e42c5caSLiam Girdwood SHIM_IMRX_DONE, 0); 4519e42c5caSLiam Girdwood } 4529e42c5caSLiam Girdwood 4539e42c5caSLiam Girdwood /* 4549e42c5caSLiam Girdwood * DSP control. 4559e42c5caSLiam Girdwood */ 4569e42c5caSLiam Girdwood 4579e42c5caSLiam Girdwood static int byt_run(struct snd_sof_dev *sdev) 4589e42c5caSLiam Girdwood { 4599e42c5caSLiam Girdwood int tries = 10; 4609e42c5caSLiam Girdwood 4619e42c5caSLiam Girdwood /* release stall and wait to unstall */ 4629e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 4639e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 0x0); 4649e42c5caSLiam Girdwood while (tries--) { 4659e42c5caSLiam Girdwood if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 4669e42c5caSLiam Girdwood SHIM_BYT_CSR_PWAITMODE)) 4679e42c5caSLiam Girdwood break; 4689e42c5caSLiam Girdwood msleep(100); 4699e42c5caSLiam Girdwood } 4709e42c5caSLiam Girdwood if (tries < 0) { 4719e42c5caSLiam Girdwood dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 4729e42c5caSLiam Girdwood byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX); 4739e42c5caSLiam Girdwood return -ENODEV; 4749e42c5caSLiam Girdwood } 4759e42c5caSLiam Girdwood 4769e42c5caSLiam Girdwood /* return init core mask */ 4779e42c5caSLiam Girdwood return 1; 4789e42c5caSLiam Girdwood } 4799e42c5caSLiam Girdwood 4809e42c5caSLiam Girdwood static int byt_reset(struct snd_sof_dev *sdev) 4819e42c5caSLiam Girdwood { 4829e42c5caSLiam Girdwood /* put DSP into reset, set reset vector and stall */ 4839e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 4849e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 4859e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL, 4869e42c5caSLiam Girdwood SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 4879e42c5caSLiam Girdwood SHIM_BYT_CSR_STALL); 4889e42c5caSLiam Girdwood 4899e42c5caSLiam Girdwood usleep_range(10, 15); 4909e42c5caSLiam Girdwood 4919e42c5caSLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 4929e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 4939e42c5caSLiam Girdwood SHIM_BYT_CSR_RST, 0); 4949e42c5caSLiam Girdwood 4959e42c5caSLiam Girdwood return 0; 4969e42c5caSLiam Girdwood } 4979e42c5caSLiam Girdwood 4989e42c5caSLiam Girdwood /* Baytrail DAIs */ 4999e42c5caSLiam Girdwood static struct snd_soc_dai_driver byt_dai[] = { 5009e42c5caSLiam Girdwood { 5019e42c5caSLiam Girdwood .name = "ssp0-port", 5029e42c5caSLiam Girdwood }, 5039e42c5caSLiam Girdwood { 5049e42c5caSLiam Girdwood .name = "ssp1-port", 5059e42c5caSLiam Girdwood }, 5069e42c5caSLiam Girdwood { 5079e42c5caSLiam Girdwood .name = "ssp2-port", 5089e42c5caSLiam Girdwood }, 5099e42c5caSLiam Girdwood { 5109e42c5caSLiam Girdwood .name = "ssp3-port", 5119e42c5caSLiam Girdwood }, 5129e42c5caSLiam Girdwood { 5139e42c5caSLiam Girdwood .name = "ssp4-port", 5149e42c5caSLiam Girdwood }, 5159e42c5caSLiam Girdwood { 5169e42c5caSLiam Girdwood .name = "ssp5-port", 5179e42c5caSLiam Girdwood }, 5189e42c5caSLiam Girdwood }; 5199e42c5caSLiam Girdwood 5209e42c5caSLiam Girdwood /* 5219e42c5caSLiam Girdwood * Probe and remove. 5229e42c5caSLiam Girdwood */ 5239e42c5caSLiam Girdwood 5249e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 5259e42c5caSLiam Girdwood 5269e42c5caSLiam Girdwood static int tangier_pci_probe(struct snd_sof_dev *sdev) 5279e42c5caSLiam Girdwood { 5289e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 5299e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 5309e42c5caSLiam Girdwood struct pci_dev *pci = to_pci_dev(sdev->dev); 5319e42c5caSLiam Girdwood u32 base, size; 5329e42c5caSLiam Girdwood int ret; 5339e42c5caSLiam Girdwood 5349e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 5359e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 5369e42c5caSLiam Girdwood if (ret < 0) { 5379e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 5389e42c5caSLiam Girdwood return ret; 5399e42c5caSLiam Girdwood } 5409e42c5caSLiam Girdwood 5419e42c5caSLiam Girdwood /* LPE base */ 5429e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 5439e42c5caSLiam Girdwood size = BYT_PCI_BAR_SIZE; 5449e42c5caSLiam Girdwood 5459e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 5469e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 5479e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 5489e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 5499e42c5caSLiam Girdwood base, size); 5509e42c5caSLiam Girdwood return -ENODEV; 5519e42c5caSLiam Girdwood } 5529e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 5539e42c5caSLiam Girdwood 5549e42c5caSLiam Girdwood /* IMR base - optional */ 5559e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 5569e42c5caSLiam Girdwood goto irq; 5579e42c5caSLiam Girdwood 5589e42c5caSLiam Girdwood base = pci_resource_start(pci, desc->resindex_imr_base); 5599e42c5caSLiam Girdwood size = pci_resource_len(pci, desc->resindex_imr_base); 5609e42c5caSLiam Girdwood 5619e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 5629e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 5639e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 5649e42c5caSLiam Girdwood goto irq; 5659e42c5caSLiam Girdwood } 5669e42c5caSLiam Girdwood 5679e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 5689e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 5699e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 5709e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 5719e42c5caSLiam Girdwood base, size); 5729e42c5caSLiam Girdwood return -ENODEV; 5739e42c5caSLiam Girdwood } 5749e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 5759e42c5caSLiam Girdwood 5769e42c5caSLiam Girdwood irq: 5779e42c5caSLiam Girdwood /* register our IRQ */ 5789e42c5caSLiam Girdwood sdev->ipc_irq = pci->irq; 5799e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 5809e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 5819e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 5829e42c5caSLiam Girdwood 0, "AudioDSP", sdev); 5839e42c5caSLiam Girdwood if (ret < 0) { 5849e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 5859e42c5caSLiam Girdwood sdev->ipc_irq); 5869e42c5caSLiam Girdwood return ret; 5879e42c5caSLiam Girdwood } 5889e42c5caSLiam Girdwood 5899e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 5909e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 5919e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 5929e42c5caSLiam Girdwood 5939e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 5949e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 5959e42c5caSLiam Girdwood 5969e42c5caSLiam Girdwood return ret; 5979e42c5caSLiam Girdwood } 5989e42c5caSLiam Girdwood 5999e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_tng_ops = { 6009e42c5caSLiam Girdwood /* device init */ 6019e42c5caSLiam Girdwood .probe = tangier_pci_probe, 6029e42c5caSLiam Girdwood 6039e42c5caSLiam Girdwood /* DSP core boot / reset */ 6049e42c5caSLiam Girdwood .run = byt_run, 6059e42c5caSLiam Girdwood .reset = byt_reset, 6069e42c5caSLiam Girdwood 6079e42c5caSLiam Girdwood /* Register IO */ 6089e42c5caSLiam Girdwood .write = sof_io_write, 6099e42c5caSLiam Girdwood .read = sof_io_read, 6109e42c5caSLiam Girdwood .write64 = sof_io_write64, 6119e42c5caSLiam Girdwood .read64 = sof_io_read64, 6129e42c5caSLiam Girdwood 6139e42c5caSLiam Girdwood /* Block IO */ 6149e42c5caSLiam Girdwood .block_read = sof_block_read, 6159e42c5caSLiam Girdwood .block_write = sof_block_write, 6169e42c5caSLiam Girdwood 6179e42c5caSLiam Girdwood /* doorbell */ 6189e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 6199e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 6209e42c5caSLiam Girdwood 6219e42c5caSLiam Girdwood /* ipc */ 6229e42c5caSLiam Girdwood .send_msg = byt_send_msg, 6239e42c5caSLiam Girdwood .fw_ready = byt_fw_ready, 6249e42c5caSLiam Girdwood 6259e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 6269e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 6279e42c5caSLiam Girdwood 6289e42c5caSLiam Girdwood /* debug */ 6299e42c5caSLiam Girdwood .debug_map = byt_debugfs, 6309e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 6319e42c5caSLiam Girdwood .dbg_dump = byt_dump, 6329e42c5caSLiam Girdwood 6339e42c5caSLiam Girdwood /* stream callbacks */ 6349e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 6359e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 6369e42c5caSLiam Girdwood 6379e42c5caSLiam Girdwood /* module loading */ 6389e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 6399e42c5caSLiam Girdwood 6409e42c5caSLiam Girdwood /*Firmware loading */ 6419e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 6429e42c5caSLiam Girdwood 6439e42c5caSLiam Girdwood /* DAI drivers */ 6449e42c5caSLiam Girdwood .drv = byt_dai, 6459e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 6469e42c5caSLiam Girdwood }; 6479e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_tng_ops); 6489e42c5caSLiam Girdwood 6499e42c5caSLiam Girdwood const struct sof_intel_dsp_desc tng_chip_info = { 6509e42c5caSLiam Girdwood .cores_num = 1, 6519e42c5caSLiam Girdwood .cores_mask = 1, 6529e42c5caSLiam Girdwood }; 6539e42c5caSLiam Girdwood EXPORT_SYMBOL(tng_chip_info); 6549e42c5caSLiam Girdwood 6559e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 6569e42c5caSLiam Girdwood 6579e42c5caSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 6589e42c5caSLiam Girdwood 6599e42c5caSLiam Girdwood static int byt_acpi_probe(struct snd_sof_dev *sdev) 6609e42c5caSLiam Girdwood { 6619e42c5caSLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 6629e42c5caSLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 6639e42c5caSLiam Girdwood struct platform_device *pdev = 6649e42c5caSLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 6659e42c5caSLiam Girdwood struct resource *mmio; 6669e42c5caSLiam Girdwood u32 base, size; 6679e42c5caSLiam Girdwood int ret; 6689e42c5caSLiam Girdwood 6699e42c5caSLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 6709e42c5caSLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 6719e42c5caSLiam Girdwood if (ret < 0) { 6729e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 6739e42c5caSLiam Girdwood return ret; 6749e42c5caSLiam Girdwood } 6759e42c5caSLiam Girdwood 6769e42c5caSLiam Girdwood /* LPE base */ 6779e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 6789e42c5caSLiam Girdwood desc->resindex_lpe_base); 6799e42c5caSLiam Girdwood if (mmio) { 6809e42c5caSLiam Girdwood base = mmio->start; 6819e42c5caSLiam Girdwood size = resource_size(mmio); 6829e42c5caSLiam Girdwood } else { 6839e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 6849e42c5caSLiam Girdwood desc->resindex_lpe_base); 6859e42c5caSLiam Girdwood return -EINVAL; 6869e42c5caSLiam Girdwood } 6879e42c5caSLiam Girdwood 6889e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 6899e42c5caSLiam Girdwood sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 6909e42c5caSLiam Girdwood if (!sdev->bar[BYT_DSP_BAR]) { 6919e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 6929e42c5caSLiam Girdwood base, size); 6939e42c5caSLiam Girdwood return -ENODEV; 6949e42c5caSLiam Girdwood } 6959e42c5caSLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 6969e42c5caSLiam Girdwood 6979e42c5caSLiam Girdwood /* TODO: add offsets */ 6989e42c5caSLiam Girdwood sdev->mmio_bar = BYT_DSP_BAR; 6999e42c5caSLiam Girdwood sdev->mailbox_bar = BYT_DSP_BAR; 7009e42c5caSLiam Girdwood 7019e42c5caSLiam Girdwood /* IMR base - optional */ 7029e42c5caSLiam Girdwood if (desc->resindex_imr_base == -1) 7039e42c5caSLiam Girdwood goto irq; 7049e42c5caSLiam Girdwood 7059e42c5caSLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 7069e42c5caSLiam Girdwood desc->resindex_imr_base); 7079e42c5caSLiam Girdwood if (mmio) { 7089e42c5caSLiam Girdwood base = mmio->start; 7099e42c5caSLiam Girdwood size = resource_size(mmio); 7109e42c5caSLiam Girdwood } else { 7119e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 7129e42c5caSLiam Girdwood desc->resindex_imr_base); 7139e42c5caSLiam Girdwood return -ENODEV; 7149e42c5caSLiam Girdwood } 7159e42c5caSLiam Girdwood 7169e42c5caSLiam Girdwood /* some BIOSes don't map IMR */ 7179e42c5caSLiam Girdwood if (base == 0x55aa55aa || base == 0x0) { 7189e42c5caSLiam Girdwood dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 7199e42c5caSLiam Girdwood goto irq; 7209e42c5caSLiam Girdwood } 7219e42c5caSLiam Girdwood 7229e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 7239e42c5caSLiam Girdwood sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 7249e42c5caSLiam Girdwood if (!sdev->bar[BYT_IMR_BAR]) { 7259e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 7269e42c5caSLiam Girdwood base, size); 7279e42c5caSLiam Girdwood return -ENODEV; 7289e42c5caSLiam Girdwood } 7299e42c5caSLiam Girdwood dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 7309e42c5caSLiam Girdwood 7319e42c5caSLiam Girdwood irq: 7329e42c5caSLiam Girdwood /* register our IRQ */ 7339e42c5caSLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 7349e42c5caSLiam Girdwood if (sdev->ipc_irq < 0) { 7359e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to get IRQ at index %d\n", 7369e42c5caSLiam Girdwood desc->irqindex_host_ipc); 7379e42c5caSLiam Girdwood return sdev->ipc_irq; 7389e42c5caSLiam Girdwood } 7399e42c5caSLiam Girdwood 7409e42c5caSLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 7419e42c5caSLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 7429e42c5caSLiam Girdwood byt_irq_handler, byt_irq_thread, 7439e42c5caSLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 7449e42c5caSLiam Girdwood if (ret < 0) { 7459e42c5caSLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 7469e42c5caSLiam Girdwood sdev->ipc_irq); 7479e42c5caSLiam Girdwood return ret; 7489e42c5caSLiam Girdwood } 7499e42c5caSLiam Girdwood 7509e42c5caSLiam Girdwood /* enable Interrupt from both sides */ 7519e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0); 7529e42c5caSLiam Girdwood snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0); 7539e42c5caSLiam Girdwood 7549e42c5caSLiam Girdwood /* set default mailbox offset for FW ready message */ 7559e42c5caSLiam Girdwood sdev->dsp_box.offset = MBOX_OFFSET; 7569e42c5caSLiam Girdwood 7579e42c5caSLiam Girdwood return ret; 7589e42c5caSLiam Girdwood } 7599e42c5caSLiam Girdwood 7609e42c5caSLiam Girdwood /* baytrail ops */ 7619e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_byt_ops = { 7629e42c5caSLiam Girdwood /* device init */ 7639e42c5caSLiam Girdwood .probe = byt_acpi_probe, 7649e42c5caSLiam Girdwood 7659e42c5caSLiam Girdwood /* DSP core boot / reset */ 7669e42c5caSLiam Girdwood .run = byt_run, 7679e42c5caSLiam Girdwood .reset = byt_reset, 7689e42c5caSLiam Girdwood 7699e42c5caSLiam Girdwood /* Register IO */ 7709e42c5caSLiam Girdwood .write = sof_io_write, 7719e42c5caSLiam Girdwood .read = sof_io_read, 7729e42c5caSLiam Girdwood .write64 = sof_io_write64, 7739e42c5caSLiam Girdwood .read64 = sof_io_read64, 7749e42c5caSLiam Girdwood 7759e42c5caSLiam Girdwood /* Block IO */ 7769e42c5caSLiam Girdwood .block_read = sof_block_read, 7779e42c5caSLiam Girdwood .block_write = sof_block_write, 7789e42c5caSLiam Girdwood 7799e42c5caSLiam Girdwood /* doorbell */ 7809e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 7819e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 7829e42c5caSLiam Girdwood 7839e42c5caSLiam Girdwood /* ipc */ 7849e42c5caSLiam Girdwood .send_msg = byt_send_msg, 7859e42c5caSLiam Girdwood .fw_ready = byt_fw_ready, 7869e42c5caSLiam Girdwood 7879e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 7889e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 7899e42c5caSLiam Girdwood 7909e42c5caSLiam Girdwood /* debug */ 7919e42c5caSLiam Girdwood .debug_map = byt_debugfs, 7929e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(byt_debugfs), 7939e42c5caSLiam Girdwood .dbg_dump = byt_dump, 7949e42c5caSLiam Girdwood 7959e42c5caSLiam Girdwood /* stream callbacks */ 7969e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 7979e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 7989e42c5caSLiam Girdwood 7999e42c5caSLiam Girdwood /* module loading */ 8009e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 8019e42c5caSLiam Girdwood 8029e42c5caSLiam Girdwood /*Firmware loading */ 8039e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 8049e42c5caSLiam Girdwood 8059e42c5caSLiam Girdwood /* DAI drivers */ 8069e42c5caSLiam Girdwood .drv = byt_dai, 8079e42c5caSLiam Girdwood .num_drv = 3, /* we have only 3 SSPs on byt*/ 8089e42c5caSLiam Girdwood }; 8099e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_byt_ops); 8109e42c5caSLiam Girdwood 8119e42c5caSLiam Girdwood const struct sof_intel_dsp_desc byt_chip_info = { 8129e42c5caSLiam Girdwood .cores_num = 1, 8139e42c5caSLiam Girdwood .cores_mask = 1, 8149e42c5caSLiam Girdwood }; 8159e42c5caSLiam Girdwood EXPORT_SYMBOL(byt_chip_info); 8169e42c5caSLiam Girdwood 8179e42c5caSLiam Girdwood /* cherrytrail and braswell ops */ 8189e42c5caSLiam Girdwood const struct snd_sof_dsp_ops sof_cht_ops = { 8199e42c5caSLiam Girdwood /* device init */ 8209e42c5caSLiam Girdwood .probe = byt_acpi_probe, 8219e42c5caSLiam Girdwood 8229e42c5caSLiam Girdwood /* DSP core boot / reset */ 8239e42c5caSLiam Girdwood .run = byt_run, 8249e42c5caSLiam Girdwood .reset = byt_reset, 8259e42c5caSLiam Girdwood 8269e42c5caSLiam Girdwood /* Register IO */ 8279e42c5caSLiam Girdwood .write = sof_io_write, 8289e42c5caSLiam Girdwood .read = sof_io_read, 8299e42c5caSLiam Girdwood .write64 = sof_io_write64, 8309e42c5caSLiam Girdwood .read64 = sof_io_read64, 8319e42c5caSLiam Girdwood 8329e42c5caSLiam Girdwood /* Block IO */ 8339e42c5caSLiam Girdwood .block_read = sof_block_read, 8349e42c5caSLiam Girdwood .block_write = sof_block_write, 8359e42c5caSLiam Girdwood 8369e42c5caSLiam Girdwood /* doorbell */ 8379e42c5caSLiam Girdwood .irq_handler = byt_irq_handler, 8389e42c5caSLiam Girdwood .irq_thread = byt_irq_thread, 8399e42c5caSLiam Girdwood 8409e42c5caSLiam Girdwood /* ipc */ 8419e42c5caSLiam Girdwood .send_msg = byt_send_msg, 8429e42c5caSLiam Girdwood .fw_ready = byt_fw_ready, 8439e42c5caSLiam Girdwood 8449e42c5caSLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 8459e42c5caSLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 8469e42c5caSLiam Girdwood 8479e42c5caSLiam Girdwood /* debug */ 8489e42c5caSLiam Girdwood .debug_map = cht_debugfs, 8499e42c5caSLiam Girdwood .debug_map_count = ARRAY_SIZE(cht_debugfs), 8509e42c5caSLiam Girdwood .dbg_dump = byt_dump, 8519e42c5caSLiam Girdwood 8529e42c5caSLiam Girdwood /* stream callbacks */ 8539e42c5caSLiam Girdwood .pcm_open = intel_pcm_open, 8549e42c5caSLiam Girdwood .pcm_close = intel_pcm_close, 8559e42c5caSLiam Girdwood 8569e42c5caSLiam Girdwood /* module loading */ 8579e42c5caSLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 8589e42c5caSLiam Girdwood 8599e42c5caSLiam Girdwood /*Firmware loading */ 8609e42c5caSLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 8619e42c5caSLiam Girdwood 8629e42c5caSLiam Girdwood /* DAI drivers */ 8639e42c5caSLiam Girdwood .drv = byt_dai, 8649e42c5caSLiam Girdwood /* all 6 SSPs may be available for cherrytrail */ 8659e42c5caSLiam Girdwood .num_drv = ARRAY_SIZE(byt_dai), 8669e42c5caSLiam Girdwood }; 8679e42c5caSLiam Girdwood EXPORT_SYMBOL(sof_cht_ops); 8689e42c5caSLiam Girdwood 8699e42c5caSLiam Girdwood const struct sof_intel_dsp_desc cht_chip_info = { 8709e42c5caSLiam Girdwood .cores_num = 1, 8719e42c5caSLiam Girdwood .cores_mask = 1, 8729e42c5caSLiam Girdwood }; 8739e42c5caSLiam Girdwood EXPORT_SYMBOL(cht_chip_info); 8749e42c5caSLiam Girdwood 8759e42c5caSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 8769e42c5caSLiam Girdwood 8779e42c5caSLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 878