1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Broadwell 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include "../ops.h" 19 #include "shim.h" 20 21 /* BARs */ 22 #define BDW_DSP_BAR 0 23 #define BDW_PCI_BAR 1 24 25 /* 26 * Debug 27 */ 28 29 /* DSP memories for BDW */ 30 #define IRAM_OFFSET 0xA0000 31 #define BDW_IRAM_SIZE (10 * 32 * 1024) 32 #define DRAM_OFFSET 0x00000 33 #define BDW_DRAM_SIZE (20 * 32 * 1024) 34 #define SHIM_OFFSET 0xFB000 35 #define SHIM_SIZE 0x100 36 #define MBOX_OFFSET 0x9E000 37 #define MBOX_SIZE 0x1000 38 #define MBOX_DUMP_SIZE 0x30 39 #define EXCEPT_OFFSET 0x800 40 41 /* DSP peripherals */ 42 #define DMAC0_OFFSET 0xFE000 43 #define DMAC1_OFFSET 0xFF000 44 #define DMAC_SIZE 0x420 45 #define SSP0_OFFSET 0xFC000 46 #define SSP1_OFFSET 0xFD000 47 #define SSP_SIZE 0x100 48 49 #define BDW_STACK_DUMP_SIZE 32 50 51 #define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF) 52 53 static const struct snd_sof_debugfs_map bdw_debugfs[] = { 54 {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 55 SOF_DEBUGFS_ACCESS_ALWAYS}, 56 {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 57 SOF_DEBUGFS_ACCESS_ALWAYS}, 58 {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 59 SOF_DEBUGFS_ACCESS_ALWAYS}, 60 {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 61 SOF_DEBUGFS_ACCESS_ALWAYS}, 62 {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE, 63 SOF_DEBUGFS_ACCESS_D0_ONLY}, 64 {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE, 65 SOF_DEBUGFS_ACCESS_D0_ONLY}, 66 {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 67 SOF_DEBUGFS_ACCESS_ALWAYS}, 68 }; 69 70 static void bdw_host_done(struct snd_sof_dev *sdev); 71 static void bdw_dsp_done(struct snd_sof_dev *sdev); 72 static void bdw_get_reply(struct snd_sof_dev *sdev); 73 74 /* 75 * DSP Control. 76 */ 77 78 static int bdw_run(struct snd_sof_dev *sdev) 79 { 80 /* set opportunistic mode on engine 0,1 for all channels */ 81 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 82 SHIM_HMDC_HDDA_E0_ALLCH | 83 SHIM_HMDC_HDDA_E1_ALLCH, 0); 84 85 /* set DSP to RUN */ 86 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 87 SHIM_CSR_STALL, 0x0); 88 89 /* return init core mask */ 90 return 1; 91 } 92 93 static int bdw_reset(struct snd_sof_dev *sdev) 94 { 95 /* put DSP into reset and stall */ 96 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 97 SHIM_CSR_RST | SHIM_CSR_STALL, 98 SHIM_CSR_RST | SHIM_CSR_STALL); 99 100 /* keep in reset for 10ms */ 101 mdelay(10); 102 103 /* take DSP out of reset and keep stalled for FW loading */ 104 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 105 SHIM_CSR_RST | SHIM_CSR_STALL, 106 SHIM_CSR_STALL); 107 108 return 0; 109 } 110 111 static int bdw_set_dsp_D0(struct snd_sof_dev *sdev) 112 { 113 int tries = 10; 114 u32 reg; 115 116 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 117 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 118 PCI_VDRTCL2_DCLCGE | 119 PCI_VDRTCL2_DTCGE, 0); 120 121 /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ 122 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 123 PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD); 124 125 /* Set D0 state */ 126 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS, 127 PCI_PMCS_PS_MASK, 0); 128 129 /* check that ADSP shim is enabled */ 130 while (tries--) { 131 reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS) 132 & PCI_PMCS_PS_MASK; 133 if (reg == 0) 134 goto finish; 135 136 msleep(20); 137 } 138 139 return -ENODEV; 140 141 finish: 142 /* 143 * select SSP1 19.2MHz base clock, SSP clock 0, 144 * turn off Low Power Clock 145 */ 146 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 147 SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 | 148 SHIM_CSR_LPCS, 0x0); 149 150 /* stall DSP core, set clk to 192/96Mhz */ 151 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 152 SHIM_CSR, SHIM_CSR_STALL | 153 SHIM_CSR_DCS_MASK, 154 SHIM_CSR_STALL | 155 SHIM_CSR_DCS(4)); 156 157 /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ 158 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL, 159 SHIM_CLKCTL_MASK | 160 SHIM_CLKCTL_DCPLCG | 161 SHIM_CLKCTL_SCOE0, 162 SHIM_CLKCTL_MASK | 163 SHIM_CLKCTL_DCPLCG | 164 SHIM_CLKCTL_SCOE0); 165 166 /* Stall and reset core, set CSR */ 167 bdw_reset(sdev); 168 169 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 170 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 171 PCI_VDRTCL2_DCLCGE | 172 PCI_VDRTCL2_DTCGE, 173 PCI_VDRTCL2_DCLCGE | 174 PCI_VDRTCL2_DTCGE); 175 176 usleep_range(50, 55); 177 178 /* switch on audio PLL */ 179 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 180 PCI_VDRTCL2_APLLSE_MASK, 0); 181 182 /* 183 * set default power gating control, enable power gating control for 184 * all blocks. that is, can't be accessed, please enable each block 185 * before accessing. 186 */ 187 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 188 0xfffffffC, 0x0); 189 190 /* disable DMA finish function for SSP0 & SSP1 */ 191 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2, 192 SHIM_CSR2_SDFD_SSP1, 193 SHIM_CSR2_SDFD_SSP1); 194 195 /* set on-demond mode on engine 0,1 for all channels */ 196 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 197 SHIM_HMDC_HDDA_E0_ALLCH | 198 SHIM_HMDC_HDDA_E1_ALLCH, 199 SHIM_HMDC_HDDA_E0_ALLCH | 200 SHIM_HMDC_HDDA_E1_ALLCH); 201 202 /* Enable Interrupt from both sides */ 203 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX, 204 (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0); 205 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD, 206 (SHIM_IMRD_DONE | SHIM_IMRD_BUSY | 207 SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0); 208 209 /* clear IPC registers */ 210 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0); 211 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0); 212 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6); 213 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a); 214 215 return 0; 216 } 217 218 static void bdw_get_registers(struct snd_sof_dev *sdev, 219 struct sof_ipc_dsp_oops_xtensa *xoops, 220 struct sof_ipc_panic_info *panic_info, 221 u32 *stack, size_t stack_words) 222 { 223 /* first read regsisters */ 224 sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops)); 225 226 /* then get panic info */ 227 sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops), 228 panic_info, sizeof(*panic_info)); 229 230 /* then get the stack */ 231 sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) + 232 sizeof(*panic_info), stack, 233 stack_words * sizeof(u32)); 234 } 235 236 static void bdw_dump(struct snd_sof_dev *sdev, u32 flags) 237 { 238 struct sof_ipc_dsp_oops_xtensa xoops; 239 struct sof_ipc_panic_info panic_info; 240 u32 stack[BDW_STACK_DUMP_SIZE]; 241 u32 status, panic; 242 243 /* now try generic SOF status messages */ 244 status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 245 panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 246 bdw_get_registers(sdev, &xoops, &panic_info, stack, 247 BDW_STACK_DUMP_SIZE); 248 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 249 BDW_STACK_DUMP_SIZE); 250 } 251 252 /* 253 * IPC Doorbell IRQ handler and thread. 254 */ 255 256 static irqreturn_t bdw_irq_handler(int irq, void *context) 257 { 258 struct snd_sof_dev *sdev = context; 259 u32 isr; 260 int ret = IRQ_NONE; 261 262 /* Interrupt arrived, check src */ 263 isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX); 264 if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 265 ret = IRQ_WAKE_THREAD; 266 267 return ret; 268 } 269 270 static irqreturn_t bdw_irq_thread(int irq, void *context) 271 { 272 struct snd_sof_dev *sdev = context; 273 u32 ipcx, ipcd, imrx; 274 275 imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX); 276 ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 277 278 /* reply message from DSP */ 279 if (ipcx & SHIM_IPCX_DONE && 280 !(imrx & SHIM_IMRX_DONE)) { 281 /* Mask Done interrupt before return */ 282 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 283 SHIM_IMRX, SHIM_IMRX_DONE, 284 SHIM_IMRX_DONE); 285 286 /* 287 * handle immediate reply from DSP core. If the msg is 288 * found, set done bit in cmd_done which is called at the 289 * end of message processing function, else set it here 290 * because the done bit can't be set in cmd_done function 291 * which is triggered by msg 292 */ 293 bdw_get_reply(sdev); 294 snd_sof_ipc_reply(sdev, ipcx); 295 296 bdw_dsp_done(sdev); 297 } 298 299 ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 300 301 /* new message from DSP */ 302 if (ipcd & SHIM_IPCD_BUSY && 303 !(imrx & SHIM_IMRX_BUSY)) { 304 /* Mask Busy interrupt before return */ 305 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 306 SHIM_IMRX, SHIM_IMRX_BUSY, 307 SHIM_IMRX_BUSY); 308 309 /* Handle messages from DSP Core */ 310 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 311 snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + 312 MBOX_OFFSET); 313 } else { 314 snd_sof_ipc_msgs_rx(sdev); 315 } 316 317 bdw_host_done(sdev); 318 } 319 320 return IRQ_HANDLED; 321 } 322 323 /* 324 * IPC Firmware ready. 325 */ 326 static void bdw_get_windows(struct snd_sof_dev *sdev) 327 { 328 struct sof_ipc_window_elem *elem; 329 u32 outbox_offset = 0; 330 u32 stream_offset = 0; 331 u32 inbox_offset = 0; 332 u32 outbox_size = 0; 333 u32 stream_size = 0; 334 u32 inbox_size = 0; 335 int i; 336 337 if (!sdev->info_window) { 338 dev_err(sdev->dev, "error: have no window info\n"); 339 return; 340 } 341 342 for (i = 0; i < sdev->info_window->num_windows; i++) { 343 elem = &sdev->info_window->window[i]; 344 345 switch (elem->type) { 346 case SOF_IPC_REGION_UPBOX: 347 inbox_offset = elem->offset + MBOX_OFFSET; 348 inbox_size = elem->size; 349 snd_sof_debugfs_io_item(sdev, 350 sdev->bar[BDW_DSP_BAR] + 351 inbox_offset, 352 elem->size, "inbox", 353 SOF_DEBUGFS_ACCESS_D0_ONLY); 354 break; 355 case SOF_IPC_REGION_DOWNBOX: 356 outbox_offset = elem->offset + MBOX_OFFSET; 357 outbox_size = elem->size; 358 snd_sof_debugfs_io_item(sdev, 359 sdev->bar[BDW_DSP_BAR] + 360 outbox_offset, 361 elem->size, "outbox", 362 SOF_DEBUGFS_ACCESS_D0_ONLY); 363 break; 364 case SOF_IPC_REGION_TRACE: 365 snd_sof_debugfs_io_item(sdev, 366 sdev->bar[BDW_DSP_BAR] + 367 elem->offset + 368 MBOX_OFFSET, 369 elem->size, "etrace", 370 SOF_DEBUGFS_ACCESS_D0_ONLY); 371 break; 372 case SOF_IPC_REGION_DEBUG: 373 snd_sof_debugfs_io_item(sdev, 374 sdev->bar[BDW_DSP_BAR] + 375 elem->offset + 376 MBOX_OFFSET, 377 elem->size, "debug", 378 SOF_DEBUGFS_ACCESS_D0_ONLY); 379 break; 380 case SOF_IPC_REGION_STREAM: 381 stream_offset = elem->offset + MBOX_OFFSET; 382 stream_size = elem->size; 383 snd_sof_debugfs_io_item(sdev, 384 sdev->bar[BDW_DSP_BAR] + 385 stream_offset, 386 elem->size, "stream", 387 SOF_DEBUGFS_ACCESS_D0_ONLY); 388 break; 389 case SOF_IPC_REGION_REGS: 390 snd_sof_debugfs_io_item(sdev, 391 sdev->bar[BDW_DSP_BAR] + 392 elem->offset + 393 MBOX_OFFSET, 394 elem->size, "regs", 395 SOF_DEBUGFS_ACCESS_D0_ONLY); 396 break; 397 case SOF_IPC_REGION_EXCEPTION: 398 sdev->dsp_oops_offset = elem->offset + MBOX_OFFSET; 399 snd_sof_debugfs_io_item(sdev, 400 sdev->bar[BDW_DSP_BAR] + 401 elem->offset + 402 MBOX_OFFSET, 403 elem->size, "exception", 404 SOF_DEBUGFS_ACCESS_D0_ONLY); 405 break; 406 default: 407 dev_err(sdev->dev, "error: get illegal window info\n"); 408 return; 409 } 410 } 411 412 if (outbox_size == 0 || inbox_size == 0) { 413 dev_err(sdev->dev, "error: get illegal mailbox window\n"); 414 return; 415 } 416 417 snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size, 418 outbox_offset, outbox_size); 419 sdev->stream_box.offset = stream_offset; 420 sdev->stream_box.size = stream_size; 421 422 dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n", 423 inbox_offset, inbox_size); 424 dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n", 425 outbox_offset, outbox_size); 426 dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n", 427 stream_offset, stream_size); 428 } 429 430 /* check for ABI compatibility and create memory windows on first boot */ 431 static int bdw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id) 432 { 433 struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready; 434 u32 offset; 435 int ret; 436 437 /* mailbox must be on 4k boundary */ 438 offset = MBOX_OFFSET; 439 440 dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset %d\n", 441 msg_id, offset); 442 443 /* no need to re-check version/ABI for subsequent boots */ 444 if (!sdev->first_boot) 445 return 0; 446 447 /* copy data from the DSP FW ready offset */ 448 sof_block_read(sdev, sdev->mmio_bar, offset, fw_ready, 449 sizeof(*fw_ready)); 450 451 snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset, 452 fw_ready->dspbox_size, 453 fw_ready->hostbox_offset, 454 fw_ready->hostbox_size); 455 456 /* make sure ABI version is compatible */ 457 ret = snd_sof_ipc_valid(sdev); 458 if (ret < 0) 459 return ret; 460 461 /* now check for extended data */ 462 snd_sof_fw_parse_ext_data(sdev, sdev->mmio_bar, MBOX_OFFSET + 463 sizeof(struct sof_ipc_fw_ready)); 464 465 bdw_get_windows(sdev); 466 467 return 0; 468 } 469 470 /* 471 * IPC Mailbox IO 472 */ 473 474 static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 475 { 476 /* send the message */ 477 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 478 msg->msg_size); 479 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY); 480 481 return 0; 482 } 483 484 static void bdw_get_reply(struct snd_sof_dev *sdev) 485 { 486 struct snd_sof_ipc_msg *msg = sdev->msg; 487 struct sof_ipc_reply reply; 488 unsigned long flags; 489 int ret = 0; 490 491 /* 492 * Sometimes, there is unexpected reply ipc arriving. The reply 493 * ipc belongs to none of the ipcs sent from driver. 494 * In this case, the driver must ignore the ipc. 495 */ 496 if (!msg) { 497 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 498 return; 499 } 500 501 /* get reply */ 502 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 503 504 spin_lock_irqsave(&sdev->ipc_lock, flags); 505 506 if (reply.error < 0) { 507 memcpy(msg->reply_data, &reply, sizeof(reply)); 508 ret = reply.error; 509 } else { 510 /* reply correct size ? */ 511 if (reply.hdr.size != msg->reply_size) { 512 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 513 msg->reply_size, reply.hdr.size); 514 ret = -EINVAL; 515 } 516 517 /* read the message */ 518 if (msg->reply_size > 0) 519 sof_mailbox_read(sdev, sdev->host_box.offset, 520 msg->reply_data, msg->reply_size); 521 } 522 523 msg->reply_error = ret; 524 525 spin_unlock_irqrestore(&sdev->ipc_lock, flags); 526 } 527 528 static void bdw_host_done(struct snd_sof_dev *sdev) 529 { 530 /* clear BUSY bit and set DONE bit - accept new messages */ 531 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD, 532 SHIM_IPCD_BUSY | SHIM_IPCD_DONE, 533 SHIM_IPCD_DONE); 534 535 /* unmask busy interrupt */ 536 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 537 SHIM_IMRX_BUSY, 0); 538 } 539 540 static void bdw_dsp_done(struct snd_sof_dev *sdev) 541 { 542 /* clear DONE bit - tell DSP we have completed */ 543 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX, 544 SHIM_IPCX_DONE, 0); 545 546 /* unmask Done interrupt */ 547 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 548 SHIM_IMRX_DONE, 0); 549 } 550 551 /* 552 * Probe and remove. 553 */ 554 static int bdw_probe(struct snd_sof_dev *sdev) 555 { 556 struct snd_sof_pdata *pdata = sdev->pdata; 557 const struct sof_dev_desc *desc = pdata->desc; 558 struct platform_device *pdev = 559 container_of(sdev->dev, struct platform_device, dev); 560 struct resource *mmio; 561 u32 base, size; 562 int ret; 563 564 /* LPE base */ 565 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 566 desc->resindex_lpe_base); 567 if (mmio) { 568 base = mmio->start; 569 size = resource_size(mmio); 570 } else { 571 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 572 desc->resindex_lpe_base); 573 return -EINVAL; 574 } 575 576 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 577 sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 578 if (!sdev->bar[BDW_DSP_BAR]) { 579 dev_err(sdev->dev, 580 "error: failed to ioremap LPE base 0x%x size 0x%x\n", 581 base, size); 582 return -ENODEV; 583 } 584 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]); 585 586 /* TODO: add offsets */ 587 sdev->mmio_bar = BDW_DSP_BAR; 588 sdev->mailbox_bar = BDW_DSP_BAR; 589 590 /* PCI base */ 591 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 592 desc->resindex_pcicfg_base); 593 if (mmio) { 594 base = mmio->start; 595 size = resource_size(mmio); 596 } else { 597 dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n", 598 desc->resindex_pcicfg_base); 599 return -ENODEV; 600 } 601 602 dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size); 603 sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size); 604 if (!sdev->bar[BDW_PCI_BAR]) { 605 dev_err(sdev->dev, 606 "error: failed to ioremap PCI base 0x%x size 0x%x\n", 607 base, size); 608 return -ENODEV; 609 } 610 dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]); 611 612 /* register our IRQ */ 613 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 614 if (sdev->ipc_irq < 0) { 615 dev_err(sdev->dev, "error: failed to get IRQ at index %d\n", 616 desc->irqindex_host_ipc); 617 return sdev->ipc_irq; 618 } 619 620 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 621 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 622 bdw_irq_handler, bdw_irq_thread, 623 IRQF_SHARED, "AudioDSP", sdev); 624 if (ret < 0) { 625 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 626 sdev->ipc_irq); 627 return ret; 628 } 629 630 /* enable the DSP SHIM */ 631 ret = bdw_set_dsp_D0(sdev); 632 if (ret < 0) { 633 dev_err(sdev->dev, "error: failed to set DSP D0\n"); 634 return ret; 635 } 636 637 /* DSP DMA can only access low 31 bits of host memory */ 638 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 639 if (ret < 0) { 640 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 641 return ret; 642 } 643 644 /* set default mailbox */ 645 snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0); 646 647 return ret; 648 } 649 650 /* Broadwell DAIs */ 651 static struct snd_soc_dai_driver bdw_dai[] = { 652 { 653 .name = "ssp0-port", 654 }, 655 { 656 .name = "ssp1-port", 657 }, 658 }; 659 660 /* broadwell ops */ 661 const struct snd_sof_dsp_ops sof_bdw_ops = { 662 /*Device init */ 663 .probe = bdw_probe, 664 665 /* DSP Core Control */ 666 .run = bdw_run, 667 .reset = bdw_reset, 668 669 /* Register IO */ 670 .write = sof_io_write, 671 .read = sof_io_read, 672 .write64 = sof_io_write64, 673 .read64 = sof_io_read64, 674 675 /* Block IO */ 676 .block_read = sof_block_read, 677 .block_write = sof_block_write, 678 679 /* ipc */ 680 .send_msg = bdw_send_msg, 681 .fw_ready = bdw_fw_ready, 682 683 .ipc_msg_data = intel_ipc_msg_data, 684 .ipc_pcm_params = intel_ipc_pcm_params, 685 686 /* debug */ 687 .debug_map = bdw_debugfs, 688 .debug_map_count = ARRAY_SIZE(bdw_debugfs), 689 .dbg_dump = bdw_dump, 690 691 /* stream callbacks */ 692 .pcm_open = intel_pcm_open, 693 .pcm_close = intel_pcm_close, 694 695 /* Module loading */ 696 .load_module = snd_sof_parse_module_memcpy, 697 698 /*Firmware loading */ 699 .load_firmware = snd_sof_load_firmware_memcpy, 700 701 /* DAI drivers */ 702 .drv = bdw_dai, 703 .num_drv = ARRAY_SIZE(bdw_dai) 704 }; 705 EXPORT_SYMBOL(sof_bdw_ops); 706 707 const struct sof_intel_dsp_desc bdw_chip_info = { 708 .cores_num = 1, 709 .cores_mask = 1, 710 }; 711 EXPORT_SYMBOL(bdw_chip_info); 712 713 MODULE_LICENSE("Dual BSD/GPL"); 714