1458bc729SLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2458bc729SLiam Girdwood // 3458bc729SLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 4458bc729SLiam Girdwood // redistributing this file, you may do so under either license. 5458bc729SLiam Girdwood // 6458bc729SLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 7458bc729SLiam Girdwood // 8458bc729SLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9458bc729SLiam Girdwood // 10458bc729SLiam Girdwood 11458bc729SLiam Girdwood /* 12458bc729SLiam Girdwood * Hardware interface for audio DSP on Broadwell 13458bc729SLiam Girdwood */ 14458bc729SLiam Girdwood 15458bc729SLiam Girdwood #include <linux/module.h> 16458bc729SLiam Girdwood #include <sound/sof.h> 17458bc729SLiam Girdwood #include <sound/sof/xtensa.h> 18458bc729SLiam Girdwood #include "../ops.h" 19458bc729SLiam Girdwood #include "shim.h" 20458bc729SLiam Girdwood 21458bc729SLiam Girdwood /* BARs */ 22458bc729SLiam Girdwood #define BDW_DSP_BAR 0 23458bc729SLiam Girdwood #define BDW_PCI_BAR 1 24458bc729SLiam Girdwood 25458bc729SLiam Girdwood /* 26458bc729SLiam Girdwood * Debug 27458bc729SLiam Girdwood */ 28458bc729SLiam Girdwood 29458bc729SLiam Girdwood /* DSP memories for BDW */ 30458bc729SLiam Girdwood #define IRAM_OFFSET 0xA0000 31458bc729SLiam Girdwood #define BDW_IRAM_SIZE (10 * 32 * 1024) 32458bc729SLiam Girdwood #define DRAM_OFFSET 0x00000 33458bc729SLiam Girdwood #define BDW_DRAM_SIZE (20 * 32 * 1024) 34458bc729SLiam Girdwood #define SHIM_OFFSET 0xFB000 35458bc729SLiam Girdwood #define SHIM_SIZE 0x100 36458bc729SLiam Girdwood #define MBOX_OFFSET 0x9E000 37458bc729SLiam Girdwood #define MBOX_SIZE 0x1000 38458bc729SLiam Girdwood #define MBOX_DUMP_SIZE 0x30 39458bc729SLiam Girdwood #define EXCEPT_OFFSET 0x800 40ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 41458bc729SLiam Girdwood 42458bc729SLiam Girdwood /* DSP peripherals */ 43458bc729SLiam Girdwood #define DMAC0_OFFSET 0xFE000 44458bc729SLiam Girdwood #define DMAC1_OFFSET 0xFF000 45458bc729SLiam Girdwood #define DMAC_SIZE 0x420 46458bc729SLiam Girdwood #define SSP0_OFFSET 0xFC000 47458bc729SLiam Girdwood #define SSP1_OFFSET 0xFD000 48458bc729SLiam Girdwood #define SSP_SIZE 0x100 49458bc729SLiam Girdwood 50458bc729SLiam Girdwood #define BDW_STACK_DUMP_SIZE 32 51458bc729SLiam Girdwood 52458bc729SLiam Girdwood #define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF) 53458bc729SLiam Girdwood 54458bc729SLiam Girdwood static const struct snd_sof_debugfs_map bdw_debugfs[] = { 55458bc729SLiam Girdwood {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 56458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 57458bc729SLiam Girdwood {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 58458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 59458bc729SLiam Girdwood {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 60458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 61458bc729SLiam Girdwood {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 62458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 63458bc729SLiam Girdwood {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE, 64458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 65458bc729SLiam Girdwood {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE, 66458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 67458bc729SLiam Girdwood {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 68458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 69458bc729SLiam Girdwood }; 70458bc729SLiam Girdwood 71458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev); 72458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev); 73458bc729SLiam Girdwood static void bdw_get_reply(struct snd_sof_dev *sdev); 74458bc729SLiam Girdwood 75458bc729SLiam Girdwood /* 76458bc729SLiam Girdwood * DSP Control. 77458bc729SLiam Girdwood */ 78458bc729SLiam Girdwood 79458bc729SLiam Girdwood static int bdw_run(struct snd_sof_dev *sdev) 80458bc729SLiam Girdwood { 81458bc729SLiam Girdwood /* set opportunistic mode on engine 0,1 for all channels */ 82458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 83458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 84458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 0); 85458bc729SLiam Girdwood 86458bc729SLiam Girdwood /* set DSP to RUN */ 87458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 88458bc729SLiam Girdwood SHIM_CSR_STALL, 0x0); 89458bc729SLiam Girdwood 90458bc729SLiam Girdwood /* return init core mask */ 91458bc729SLiam Girdwood return 1; 92458bc729SLiam Girdwood } 93458bc729SLiam Girdwood 94458bc729SLiam Girdwood static int bdw_reset(struct snd_sof_dev *sdev) 95458bc729SLiam Girdwood { 96458bc729SLiam Girdwood /* put DSP into reset and stall */ 97458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 98458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 99458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL); 100458bc729SLiam Girdwood 101458bc729SLiam Girdwood /* keep in reset for 10ms */ 102458bc729SLiam Girdwood mdelay(10); 103458bc729SLiam Girdwood 104458bc729SLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 105458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 106458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 107458bc729SLiam Girdwood SHIM_CSR_STALL); 108458bc729SLiam Girdwood 109458bc729SLiam Girdwood return 0; 110458bc729SLiam Girdwood } 111458bc729SLiam Girdwood 112458bc729SLiam Girdwood static int bdw_set_dsp_D0(struct snd_sof_dev *sdev) 113458bc729SLiam Girdwood { 114458bc729SLiam Girdwood int tries = 10; 115458bc729SLiam Girdwood u32 reg; 116458bc729SLiam Girdwood 117458bc729SLiam Girdwood /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 118458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 119458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 120458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 0); 121458bc729SLiam Girdwood 122458bc729SLiam Girdwood /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ 123458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 124458bc729SLiam Girdwood PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD); 125458bc729SLiam Girdwood 126458bc729SLiam Girdwood /* Set D0 state */ 127458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS, 128458bc729SLiam Girdwood PCI_PMCS_PS_MASK, 0); 129458bc729SLiam Girdwood 130458bc729SLiam Girdwood /* check that ADSP shim is enabled */ 131458bc729SLiam Girdwood while (tries--) { 132458bc729SLiam Girdwood reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS) 133458bc729SLiam Girdwood & PCI_PMCS_PS_MASK; 134458bc729SLiam Girdwood if (reg == 0) 135458bc729SLiam Girdwood goto finish; 136458bc729SLiam Girdwood 137458bc729SLiam Girdwood msleep(20); 138458bc729SLiam Girdwood } 139458bc729SLiam Girdwood 140458bc729SLiam Girdwood return -ENODEV; 141458bc729SLiam Girdwood 142458bc729SLiam Girdwood finish: 143458bc729SLiam Girdwood /* 144458bc729SLiam Girdwood * select SSP1 19.2MHz base clock, SSP clock 0, 145458bc729SLiam Girdwood * turn off Low Power Clock 146458bc729SLiam Girdwood */ 147458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 148458bc729SLiam Girdwood SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 | 149458bc729SLiam Girdwood SHIM_CSR_LPCS, 0x0); 150458bc729SLiam Girdwood 151458bc729SLiam Girdwood /* stall DSP core, set clk to 192/96Mhz */ 152458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 153458bc729SLiam Girdwood SHIM_CSR, SHIM_CSR_STALL | 154458bc729SLiam Girdwood SHIM_CSR_DCS_MASK, 155458bc729SLiam Girdwood SHIM_CSR_STALL | 156458bc729SLiam Girdwood SHIM_CSR_DCS(4)); 157458bc729SLiam Girdwood 158458bc729SLiam Girdwood /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ 159458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL, 160458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 161458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 162458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0, 163458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 164458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 165458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0); 166458bc729SLiam Girdwood 167458bc729SLiam Girdwood /* Stall and reset core, set CSR */ 168458bc729SLiam Girdwood bdw_reset(sdev); 169458bc729SLiam Girdwood 170458bc729SLiam Girdwood /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 171458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 172458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 173458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 174458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 175458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE); 176458bc729SLiam Girdwood 177458bc729SLiam Girdwood usleep_range(50, 55); 178458bc729SLiam Girdwood 179458bc729SLiam Girdwood /* switch on audio PLL */ 180458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 181458bc729SLiam Girdwood PCI_VDRTCL2_APLLSE_MASK, 0); 182458bc729SLiam Girdwood 183458bc729SLiam Girdwood /* 184458bc729SLiam Girdwood * set default power gating control, enable power gating control for 185458bc729SLiam Girdwood * all blocks. that is, can't be accessed, please enable each block 186458bc729SLiam Girdwood * before accessing. 187458bc729SLiam Girdwood */ 188458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 189458bc729SLiam Girdwood 0xfffffffC, 0x0); 190458bc729SLiam Girdwood 191458bc729SLiam Girdwood /* disable DMA finish function for SSP0 & SSP1 */ 192458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2, 193458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1, 194458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1); 195458bc729SLiam Girdwood 196458bc729SLiam Girdwood /* set on-demond mode on engine 0,1 for all channels */ 197458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 198458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 199458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 200458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 201458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH); 202458bc729SLiam Girdwood 203458bc729SLiam Girdwood /* Enable Interrupt from both sides */ 204458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX, 205458bc729SLiam Girdwood (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0); 206458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD, 207458bc729SLiam Girdwood (SHIM_IMRD_DONE | SHIM_IMRD_BUSY | 208458bc729SLiam Girdwood SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0); 209458bc729SLiam Girdwood 210458bc729SLiam Girdwood /* clear IPC registers */ 211458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0); 212458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0); 213458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6); 214458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a); 215458bc729SLiam Girdwood 216458bc729SLiam Girdwood return 0; 217458bc729SLiam Girdwood } 218458bc729SLiam Girdwood 219458bc729SLiam Girdwood static void bdw_get_registers(struct snd_sof_dev *sdev, 220458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 221458bc729SLiam Girdwood struct sof_ipc_panic_info *panic_info, 222458bc729SLiam Girdwood u32 *stack, size_t stack_words) 223458bc729SLiam Girdwood { 22414104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 22514104eb6SKai Vehmanen 22614104eb6SKai Vehmanen /* first read registers */ 22714104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 22814104eb6SKai Vehmanen 22914104eb6SKai Vehmanen /* note: variable AR register array is not read */ 230458bc729SLiam Girdwood 231458bc729SLiam Girdwood /* then get panic info */ 232ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 233ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 234ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 235ff2be865SLiam Girdwood return; 236ff2be865SLiam Girdwood } 23714104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 23814104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 239458bc729SLiam Girdwood 240458bc729SLiam Girdwood /* then get the stack */ 24114104eb6SKai Vehmanen offset += sizeof(*panic_info); 24214104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 243458bc729SLiam Girdwood } 244458bc729SLiam Girdwood 245458bc729SLiam Girdwood static void bdw_dump(struct snd_sof_dev *sdev, u32 flags) 246458bc729SLiam Girdwood { 247458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 248458bc729SLiam Girdwood struct sof_ipc_panic_info panic_info; 249458bc729SLiam Girdwood u32 stack[BDW_STACK_DUMP_SIZE]; 250458bc729SLiam Girdwood u32 status, panic; 251458bc729SLiam Girdwood 252458bc729SLiam Girdwood /* now try generic SOF status messages */ 253458bc729SLiam Girdwood status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 254458bc729SLiam Girdwood panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 255458bc729SLiam Girdwood bdw_get_registers(sdev, &xoops, &panic_info, stack, 256458bc729SLiam Girdwood BDW_STACK_DUMP_SIZE); 257458bc729SLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 258458bc729SLiam Girdwood BDW_STACK_DUMP_SIZE); 259458bc729SLiam Girdwood } 260458bc729SLiam Girdwood 261458bc729SLiam Girdwood /* 262458bc729SLiam Girdwood * IPC Doorbell IRQ handler and thread. 263458bc729SLiam Girdwood */ 264458bc729SLiam Girdwood 265458bc729SLiam Girdwood static irqreturn_t bdw_irq_handler(int irq, void *context) 266458bc729SLiam Girdwood { 267458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 268458bc729SLiam Girdwood u32 isr; 269458bc729SLiam Girdwood int ret = IRQ_NONE; 270458bc729SLiam Girdwood 271458bc729SLiam Girdwood /* Interrupt arrived, check src */ 272458bc729SLiam Girdwood isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX); 273458bc729SLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 274458bc729SLiam Girdwood ret = IRQ_WAKE_THREAD; 275458bc729SLiam Girdwood 276458bc729SLiam Girdwood return ret; 277458bc729SLiam Girdwood } 278458bc729SLiam Girdwood 279458bc729SLiam Girdwood static irqreturn_t bdw_irq_thread(int irq, void *context) 280458bc729SLiam Girdwood { 281458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 282458bc729SLiam Girdwood u32 ipcx, ipcd, imrx; 283458bc729SLiam Girdwood 284458bc729SLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX); 285458bc729SLiam Girdwood ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 286458bc729SLiam Girdwood 287458bc729SLiam Girdwood /* reply message from DSP */ 288458bc729SLiam Girdwood if (ipcx & SHIM_IPCX_DONE && 289458bc729SLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 290458bc729SLiam Girdwood /* Mask Done interrupt before return */ 291458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 292458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_DONE, 293458bc729SLiam Girdwood SHIM_IMRX_DONE); 294458bc729SLiam Girdwood 2951183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2961183e9a6SGuennadi Liakhovetski 297458bc729SLiam Girdwood /* 298458bc729SLiam Girdwood * handle immediate reply from DSP core. If the msg is 299458bc729SLiam Girdwood * found, set done bit in cmd_done which is called at the 300458bc729SLiam Girdwood * end of message processing function, else set it here 301458bc729SLiam Girdwood * because the done bit can't be set in cmd_done function 302458bc729SLiam Girdwood * which is triggered by msg 303458bc729SLiam Girdwood */ 304458bc729SLiam Girdwood bdw_get_reply(sdev); 305458bc729SLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 306458bc729SLiam Girdwood 307458bc729SLiam Girdwood bdw_dsp_done(sdev); 3081183e9a6SGuennadi Liakhovetski 3091183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 310458bc729SLiam Girdwood } 311458bc729SLiam Girdwood 312458bc729SLiam Girdwood ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 313458bc729SLiam Girdwood 314458bc729SLiam Girdwood /* new message from DSP */ 315458bc729SLiam Girdwood if (ipcd & SHIM_IPCD_BUSY && 316458bc729SLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 317458bc729SLiam Girdwood /* Mask Busy interrupt before return */ 318458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 319458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_BUSY, 320458bc729SLiam Girdwood SHIM_IMRX_BUSY); 321458bc729SLiam Girdwood 322458bc729SLiam Girdwood /* Handle messages from DSP Core */ 323458bc729SLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 324458bc729SLiam Girdwood snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + 325458bc729SLiam Girdwood MBOX_OFFSET); 326458bc729SLiam Girdwood } else { 327458bc729SLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 328458bc729SLiam Girdwood } 329458bc729SLiam Girdwood 330458bc729SLiam Girdwood bdw_host_done(sdev); 331458bc729SLiam Girdwood } 332458bc729SLiam Girdwood 333458bc729SLiam Girdwood return IRQ_HANDLED; 334458bc729SLiam Girdwood } 335458bc729SLiam Girdwood 336458bc729SLiam Girdwood /* 337458bc729SLiam Girdwood * IPC Mailbox IO 338458bc729SLiam Girdwood */ 339458bc729SLiam Girdwood 340458bc729SLiam Girdwood static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 341458bc729SLiam Girdwood { 342458bc729SLiam Girdwood /* send the message */ 343458bc729SLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 344458bc729SLiam Girdwood msg->msg_size); 345458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY); 346458bc729SLiam Girdwood 347458bc729SLiam Girdwood return 0; 348458bc729SLiam Girdwood } 349458bc729SLiam Girdwood 350458bc729SLiam Girdwood static void bdw_get_reply(struct snd_sof_dev *sdev) 351458bc729SLiam Girdwood { 352458bc729SLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 353458bc729SLiam Girdwood struct sof_ipc_reply reply; 354458bc729SLiam Girdwood int ret = 0; 355458bc729SLiam Girdwood 356458bc729SLiam Girdwood /* 357458bc729SLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 358458bc729SLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 359458bc729SLiam Girdwood * In this case, the driver must ignore the ipc. 360458bc729SLiam Girdwood */ 361458bc729SLiam Girdwood if (!msg) { 362458bc729SLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 363458bc729SLiam Girdwood return; 364458bc729SLiam Girdwood } 365458bc729SLiam Girdwood 366458bc729SLiam Girdwood /* get reply */ 367458bc729SLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 368458bc729SLiam Girdwood 369458bc729SLiam Girdwood if (reply.error < 0) { 370458bc729SLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 371458bc729SLiam Girdwood ret = reply.error; 372458bc729SLiam Girdwood } else { 373458bc729SLiam Girdwood /* reply correct size ? */ 374458bc729SLiam Girdwood if (reply.hdr.size != msg->reply_size) { 375458bc729SLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 376458bc729SLiam Girdwood msg->reply_size, reply.hdr.size); 377458bc729SLiam Girdwood ret = -EINVAL; 378458bc729SLiam Girdwood } 379458bc729SLiam Girdwood 380458bc729SLiam Girdwood /* read the message */ 381458bc729SLiam Girdwood if (msg->reply_size > 0) 382458bc729SLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 383458bc729SLiam Girdwood msg->reply_data, msg->reply_size); 384458bc729SLiam Girdwood } 385458bc729SLiam Girdwood 386458bc729SLiam Girdwood msg->reply_error = ret; 387458bc729SLiam Girdwood } 388458bc729SLiam Girdwood 389ddf14b64SDaniel Baluta static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev) 390ddf14b64SDaniel Baluta { 391ddf14b64SDaniel Baluta return MBOX_OFFSET; 392ddf14b64SDaniel Baluta } 393ddf14b64SDaniel Baluta 394ddf14b64SDaniel Baluta static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id) 395ddf14b64SDaniel Baluta { 396ddf14b64SDaniel Baluta return MBOX_OFFSET; 397ddf14b64SDaniel Baluta } 398ddf14b64SDaniel Baluta 399458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev) 400458bc729SLiam Girdwood { 401458bc729SLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 402458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD, 403458bc729SLiam Girdwood SHIM_IPCD_BUSY | SHIM_IPCD_DONE, 404458bc729SLiam Girdwood SHIM_IPCD_DONE); 405458bc729SLiam Girdwood 406458bc729SLiam Girdwood /* unmask busy interrupt */ 407458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 408458bc729SLiam Girdwood SHIM_IMRX_BUSY, 0); 409458bc729SLiam Girdwood } 410458bc729SLiam Girdwood 411458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev) 412458bc729SLiam Girdwood { 413458bc729SLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 414458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX, 415458bc729SLiam Girdwood SHIM_IPCX_DONE, 0); 416458bc729SLiam Girdwood 417458bc729SLiam Girdwood /* unmask Done interrupt */ 418458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 419458bc729SLiam Girdwood SHIM_IMRX_DONE, 0); 420458bc729SLiam Girdwood } 421458bc729SLiam Girdwood 422458bc729SLiam Girdwood /* 423458bc729SLiam Girdwood * Probe and remove. 424458bc729SLiam Girdwood */ 425458bc729SLiam Girdwood static int bdw_probe(struct snd_sof_dev *sdev) 426458bc729SLiam Girdwood { 427458bc729SLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 428458bc729SLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 429458bc729SLiam Girdwood struct platform_device *pdev = 430458bc729SLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 431458bc729SLiam Girdwood struct resource *mmio; 432458bc729SLiam Girdwood u32 base, size; 433458bc729SLiam Girdwood int ret; 434458bc729SLiam Girdwood 435458bc729SLiam Girdwood /* LPE base */ 436458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 437458bc729SLiam Girdwood desc->resindex_lpe_base); 438458bc729SLiam Girdwood if (mmio) { 439458bc729SLiam Girdwood base = mmio->start; 440458bc729SLiam Girdwood size = resource_size(mmio); 441458bc729SLiam Girdwood } else { 442458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 443458bc729SLiam Girdwood desc->resindex_lpe_base); 444458bc729SLiam Girdwood return -EINVAL; 445458bc729SLiam Girdwood } 446458bc729SLiam Girdwood 447458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 448458bc729SLiam Girdwood sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 449458bc729SLiam Girdwood if (!sdev->bar[BDW_DSP_BAR]) { 450458bc729SLiam Girdwood dev_err(sdev->dev, 451458bc729SLiam Girdwood "error: failed to ioremap LPE base 0x%x size 0x%x\n", 452458bc729SLiam Girdwood base, size); 453458bc729SLiam Girdwood return -ENODEV; 454458bc729SLiam Girdwood } 455458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]); 456458bc729SLiam Girdwood 457458bc729SLiam Girdwood /* TODO: add offsets */ 458458bc729SLiam Girdwood sdev->mmio_bar = BDW_DSP_BAR; 459458bc729SLiam Girdwood sdev->mailbox_bar = BDW_DSP_BAR; 460ff2be865SLiam Girdwood sdev->dsp_oops_offset = MBOX_OFFSET; 461458bc729SLiam Girdwood 462458bc729SLiam Girdwood /* PCI base */ 463458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 464458bc729SLiam Girdwood desc->resindex_pcicfg_base); 465458bc729SLiam Girdwood if (mmio) { 466458bc729SLiam Girdwood base = mmio->start; 467458bc729SLiam Girdwood size = resource_size(mmio); 468458bc729SLiam Girdwood } else { 469458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n", 470458bc729SLiam Girdwood desc->resindex_pcicfg_base); 471458bc729SLiam Girdwood return -ENODEV; 472458bc729SLiam Girdwood } 473458bc729SLiam Girdwood 474458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size); 475458bc729SLiam Girdwood sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size); 476458bc729SLiam Girdwood if (!sdev->bar[BDW_PCI_BAR]) { 477458bc729SLiam Girdwood dev_err(sdev->dev, 478458bc729SLiam Girdwood "error: failed to ioremap PCI base 0x%x size 0x%x\n", 479458bc729SLiam Girdwood base, size); 480458bc729SLiam Girdwood return -ENODEV; 481458bc729SLiam Girdwood } 482458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]); 483458bc729SLiam Girdwood 484458bc729SLiam Girdwood /* register our IRQ */ 485458bc729SLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 486cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 487458bc729SLiam Girdwood return sdev->ipc_irq; 488458bc729SLiam Girdwood 489458bc729SLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 490458bc729SLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 491458bc729SLiam Girdwood bdw_irq_handler, bdw_irq_thread, 492458bc729SLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 493458bc729SLiam Girdwood if (ret < 0) { 494458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 495458bc729SLiam Girdwood sdev->ipc_irq); 496458bc729SLiam Girdwood return ret; 497458bc729SLiam Girdwood } 498458bc729SLiam Girdwood 499458bc729SLiam Girdwood /* enable the DSP SHIM */ 500458bc729SLiam Girdwood ret = bdw_set_dsp_D0(sdev); 501458bc729SLiam Girdwood if (ret < 0) { 502458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DSP D0\n"); 503458bc729SLiam Girdwood return ret; 504458bc729SLiam Girdwood } 505458bc729SLiam Girdwood 506458bc729SLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 507458bc729SLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 508458bc729SLiam Girdwood if (ret < 0) { 509458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 510458bc729SLiam Girdwood return ret; 511458bc729SLiam Girdwood } 512458bc729SLiam Girdwood 513458bc729SLiam Girdwood /* set default mailbox */ 514458bc729SLiam Girdwood snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0); 515458bc729SLiam Girdwood 516458bc729SLiam Girdwood return ret; 517458bc729SLiam Girdwood } 518458bc729SLiam Girdwood 519458bc729SLiam Girdwood /* Broadwell DAIs */ 520458bc729SLiam Girdwood static struct snd_soc_dai_driver bdw_dai[] = { 521458bc729SLiam Girdwood { 522458bc729SLiam Girdwood .name = "ssp0-port", 523458bc729SLiam Girdwood }, 524458bc729SLiam Girdwood { 525458bc729SLiam Girdwood .name = "ssp1-port", 526458bc729SLiam Girdwood }, 527458bc729SLiam Girdwood }; 528458bc729SLiam Girdwood 529458bc729SLiam Girdwood /* broadwell ops */ 530458bc729SLiam Girdwood const struct snd_sof_dsp_ops sof_bdw_ops = { 531458bc729SLiam Girdwood /*Device init */ 532458bc729SLiam Girdwood .probe = bdw_probe, 533458bc729SLiam Girdwood 534458bc729SLiam Girdwood /* DSP Core Control */ 535458bc729SLiam Girdwood .run = bdw_run, 536458bc729SLiam Girdwood .reset = bdw_reset, 537458bc729SLiam Girdwood 538458bc729SLiam Girdwood /* Register IO */ 539458bc729SLiam Girdwood .write = sof_io_write, 540458bc729SLiam Girdwood .read = sof_io_read, 541458bc729SLiam Girdwood .write64 = sof_io_write64, 542458bc729SLiam Girdwood .read64 = sof_io_read64, 543458bc729SLiam Girdwood 544458bc729SLiam Girdwood /* Block IO */ 545458bc729SLiam Girdwood .block_read = sof_block_read, 546458bc729SLiam Girdwood .block_write = sof_block_write, 547458bc729SLiam Girdwood 548458bc729SLiam Girdwood /* ipc */ 549458bc729SLiam Girdwood .send_msg = bdw_send_msg, 550ddf14b64SDaniel Baluta .fw_ready = sof_fw_ready, 551ddf14b64SDaniel Baluta .get_mailbox_offset = bdw_get_mailbox_offset, 552ddf14b64SDaniel Baluta .get_window_offset = bdw_get_window_offset, 553458bc729SLiam Girdwood 554458bc729SLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 555458bc729SLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 556458bc729SLiam Girdwood 557458bc729SLiam Girdwood /* debug */ 558458bc729SLiam Girdwood .debug_map = bdw_debugfs, 559458bc729SLiam Girdwood .debug_map_count = ARRAY_SIZE(bdw_debugfs), 560458bc729SLiam Girdwood .dbg_dump = bdw_dump, 561458bc729SLiam Girdwood 562458bc729SLiam Girdwood /* stream callbacks */ 563458bc729SLiam Girdwood .pcm_open = intel_pcm_open, 564458bc729SLiam Girdwood .pcm_close = intel_pcm_close, 565458bc729SLiam Girdwood 566458bc729SLiam Girdwood /* Module loading */ 567458bc729SLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 568458bc729SLiam Girdwood 569458bc729SLiam Girdwood /*Firmware loading */ 570458bc729SLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 571458bc729SLiam Girdwood 572458bc729SLiam Girdwood /* DAI drivers */ 573458bc729SLiam Girdwood .drv = bdw_dai, 574458bc729SLiam Girdwood .num_drv = ARRAY_SIZE(bdw_dai) 575458bc729SLiam Girdwood }; 576458bc729SLiam Girdwood EXPORT_SYMBOL(sof_bdw_ops); 577458bc729SLiam Girdwood 578458bc729SLiam Girdwood const struct sof_intel_dsp_desc bdw_chip_info = { 579458bc729SLiam Girdwood .cores_num = 1, 580458bc729SLiam Girdwood .cores_mask = 1, 581458bc729SLiam Girdwood }; 582458bc729SLiam Girdwood EXPORT_SYMBOL(bdw_chip_info); 583458bc729SLiam Girdwood 584458bc729SLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 585