1458bc729SLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2458bc729SLiam Girdwood // 3458bc729SLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 4458bc729SLiam Girdwood // redistributing this file, you may do so under either license. 5458bc729SLiam Girdwood // 6458bc729SLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 7458bc729SLiam Girdwood // 8458bc729SLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9458bc729SLiam Girdwood // 10458bc729SLiam Girdwood 11458bc729SLiam Girdwood /* 12458bc729SLiam Girdwood * Hardware interface for audio DSP on Broadwell 13458bc729SLiam Girdwood */ 14458bc729SLiam Girdwood 15458bc729SLiam Girdwood #include <linux/module.h> 16458bc729SLiam Girdwood #include <sound/sof.h> 17458bc729SLiam Girdwood #include <sound/sof/xtensa.h> 18458bc729SLiam Girdwood #include "../ops.h" 19458bc729SLiam Girdwood #include "shim.h" 20458bc729SLiam Girdwood 21458bc729SLiam Girdwood /* BARs */ 22458bc729SLiam Girdwood #define BDW_DSP_BAR 0 23458bc729SLiam Girdwood #define BDW_PCI_BAR 1 24458bc729SLiam Girdwood 25458bc729SLiam Girdwood /* 26458bc729SLiam Girdwood * Debug 27458bc729SLiam Girdwood */ 28458bc729SLiam Girdwood 29458bc729SLiam Girdwood /* DSP memories for BDW */ 30458bc729SLiam Girdwood #define IRAM_OFFSET 0xA0000 31458bc729SLiam Girdwood #define BDW_IRAM_SIZE (10 * 32 * 1024) 32458bc729SLiam Girdwood #define DRAM_OFFSET 0x00000 33458bc729SLiam Girdwood #define BDW_DRAM_SIZE (20 * 32 * 1024) 34458bc729SLiam Girdwood #define SHIM_OFFSET 0xFB000 35458bc729SLiam Girdwood #define SHIM_SIZE 0x100 36458bc729SLiam Girdwood #define MBOX_OFFSET 0x9E000 37458bc729SLiam Girdwood #define MBOX_SIZE 0x1000 38458bc729SLiam Girdwood #define MBOX_DUMP_SIZE 0x30 39458bc729SLiam Girdwood #define EXCEPT_OFFSET 0x800 40458bc729SLiam Girdwood 41458bc729SLiam Girdwood /* DSP peripherals */ 42458bc729SLiam Girdwood #define DMAC0_OFFSET 0xFE000 43458bc729SLiam Girdwood #define DMAC1_OFFSET 0xFF000 44458bc729SLiam Girdwood #define DMAC_SIZE 0x420 45458bc729SLiam Girdwood #define SSP0_OFFSET 0xFC000 46458bc729SLiam Girdwood #define SSP1_OFFSET 0xFD000 47458bc729SLiam Girdwood #define SSP_SIZE 0x100 48458bc729SLiam Girdwood 49458bc729SLiam Girdwood #define BDW_STACK_DUMP_SIZE 32 50458bc729SLiam Girdwood 51458bc729SLiam Girdwood #define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF) 52458bc729SLiam Girdwood 53458bc729SLiam Girdwood static const struct snd_sof_debugfs_map bdw_debugfs[] = { 54458bc729SLiam Girdwood {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 55458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 56458bc729SLiam Girdwood {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 57458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 58458bc729SLiam Girdwood {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 59458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 60458bc729SLiam Girdwood {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 61458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 62458bc729SLiam Girdwood {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE, 63458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 64458bc729SLiam Girdwood {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE, 65458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 66458bc729SLiam Girdwood {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 67458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 68458bc729SLiam Girdwood }; 69458bc729SLiam Girdwood 70458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev); 71458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev); 72458bc729SLiam Girdwood static void bdw_get_reply(struct snd_sof_dev *sdev); 73458bc729SLiam Girdwood 74458bc729SLiam Girdwood /* 75458bc729SLiam Girdwood * DSP Control. 76458bc729SLiam Girdwood */ 77458bc729SLiam Girdwood 78458bc729SLiam Girdwood static int bdw_run(struct snd_sof_dev *sdev) 79458bc729SLiam Girdwood { 80458bc729SLiam Girdwood /* set opportunistic mode on engine 0,1 for all channels */ 81458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 82458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 83458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 0); 84458bc729SLiam Girdwood 85458bc729SLiam Girdwood /* set DSP to RUN */ 86458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 87458bc729SLiam Girdwood SHIM_CSR_STALL, 0x0); 88458bc729SLiam Girdwood 89458bc729SLiam Girdwood /* return init core mask */ 90458bc729SLiam Girdwood return 1; 91458bc729SLiam Girdwood } 92458bc729SLiam Girdwood 93458bc729SLiam Girdwood static int bdw_reset(struct snd_sof_dev *sdev) 94458bc729SLiam Girdwood { 95458bc729SLiam Girdwood /* put DSP into reset and stall */ 96458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 97458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 98458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL); 99458bc729SLiam Girdwood 100458bc729SLiam Girdwood /* keep in reset for 10ms */ 101458bc729SLiam Girdwood mdelay(10); 102458bc729SLiam Girdwood 103458bc729SLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 104458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 105458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 106458bc729SLiam Girdwood SHIM_CSR_STALL); 107458bc729SLiam Girdwood 108458bc729SLiam Girdwood return 0; 109458bc729SLiam Girdwood } 110458bc729SLiam Girdwood 111458bc729SLiam Girdwood static int bdw_set_dsp_D0(struct snd_sof_dev *sdev) 112458bc729SLiam Girdwood { 113458bc729SLiam Girdwood int tries = 10; 114458bc729SLiam Girdwood u32 reg; 115458bc729SLiam Girdwood 116458bc729SLiam Girdwood /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 117458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 118458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 119458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 0); 120458bc729SLiam Girdwood 121458bc729SLiam Girdwood /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ 122458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 123458bc729SLiam Girdwood PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD); 124458bc729SLiam Girdwood 125458bc729SLiam Girdwood /* Set D0 state */ 126458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS, 127458bc729SLiam Girdwood PCI_PMCS_PS_MASK, 0); 128458bc729SLiam Girdwood 129458bc729SLiam Girdwood /* check that ADSP shim is enabled */ 130458bc729SLiam Girdwood while (tries--) { 131458bc729SLiam Girdwood reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS) 132458bc729SLiam Girdwood & PCI_PMCS_PS_MASK; 133458bc729SLiam Girdwood if (reg == 0) 134458bc729SLiam Girdwood goto finish; 135458bc729SLiam Girdwood 136458bc729SLiam Girdwood msleep(20); 137458bc729SLiam Girdwood } 138458bc729SLiam Girdwood 139458bc729SLiam Girdwood return -ENODEV; 140458bc729SLiam Girdwood 141458bc729SLiam Girdwood finish: 142458bc729SLiam Girdwood /* 143458bc729SLiam Girdwood * select SSP1 19.2MHz base clock, SSP clock 0, 144458bc729SLiam Girdwood * turn off Low Power Clock 145458bc729SLiam Girdwood */ 146458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 147458bc729SLiam Girdwood SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 | 148458bc729SLiam Girdwood SHIM_CSR_LPCS, 0x0); 149458bc729SLiam Girdwood 150458bc729SLiam Girdwood /* stall DSP core, set clk to 192/96Mhz */ 151458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 152458bc729SLiam Girdwood SHIM_CSR, SHIM_CSR_STALL | 153458bc729SLiam Girdwood SHIM_CSR_DCS_MASK, 154458bc729SLiam Girdwood SHIM_CSR_STALL | 155458bc729SLiam Girdwood SHIM_CSR_DCS(4)); 156458bc729SLiam Girdwood 157458bc729SLiam Girdwood /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ 158458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL, 159458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 160458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 161458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0, 162458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 163458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 164458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0); 165458bc729SLiam Girdwood 166458bc729SLiam Girdwood /* Stall and reset core, set CSR */ 167458bc729SLiam Girdwood bdw_reset(sdev); 168458bc729SLiam Girdwood 169458bc729SLiam Girdwood /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 170458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 171458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 172458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 173458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 174458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE); 175458bc729SLiam Girdwood 176458bc729SLiam Girdwood usleep_range(50, 55); 177458bc729SLiam Girdwood 178458bc729SLiam Girdwood /* switch on audio PLL */ 179458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 180458bc729SLiam Girdwood PCI_VDRTCL2_APLLSE_MASK, 0); 181458bc729SLiam Girdwood 182458bc729SLiam Girdwood /* 183458bc729SLiam Girdwood * set default power gating control, enable power gating control for 184458bc729SLiam Girdwood * all blocks. that is, can't be accessed, please enable each block 185458bc729SLiam Girdwood * before accessing. 186458bc729SLiam Girdwood */ 187458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 188458bc729SLiam Girdwood 0xfffffffC, 0x0); 189458bc729SLiam Girdwood 190458bc729SLiam Girdwood /* disable DMA finish function for SSP0 & SSP1 */ 191458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2, 192458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1, 193458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1); 194458bc729SLiam Girdwood 195458bc729SLiam Girdwood /* set on-demond mode on engine 0,1 for all channels */ 196458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 197458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 198458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 199458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 200458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH); 201458bc729SLiam Girdwood 202458bc729SLiam Girdwood /* Enable Interrupt from both sides */ 203458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX, 204458bc729SLiam Girdwood (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0); 205458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD, 206458bc729SLiam Girdwood (SHIM_IMRD_DONE | SHIM_IMRD_BUSY | 207458bc729SLiam Girdwood SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0); 208458bc729SLiam Girdwood 209458bc729SLiam Girdwood /* clear IPC registers */ 210458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0); 211458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0); 212458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6); 213458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a); 214458bc729SLiam Girdwood 215458bc729SLiam Girdwood return 0; 216458bc729SLiam Girdwood } 217458bc729SLiam Girdwood 218458bc729SLiam Girdwood static void bdw_get_registers(struct snd_sof_dev *sdev, 219458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 220458bc729SLiam Girdwood struct sof_ipc_panic_info *panic_info, 221458bc729SLiam Girdwood u32 *stack, size_t stack_words) 222458bc729SLiam Girdwood { 22314104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 22414104eb6SKai Vehmanen 22514104eb6SKai Vehmanen /* first read registers */ 22614104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 22714104eb6SKai Vehmanen 22814104eb6SKai Vehmanen /* note: variable AR register array is not read */ 229458bc729SLiam Girdwood 230458bc729SLiam Girdwood /* then get panic info */ 23114104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 23214104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 233458bc729SLiam Girdwood 234458bc729SLiam Girdwood /* then get the stack */ 23514104eb6SKai Vehmanen offset += sizeof(*panic_info); 23614104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 237458bc729SLiam Girdwood } 238458bc729SLiam Girdwood 239458bc729SLiam Girdwood static void bdw_dump(struct snd_sof_dev *sdev, u32 flags) 240458bc729SLiam Girdwood { 241458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 242458bc729SLiam Girdwood struct sof_ipc_panic_info panic_info; 243458bc729SLiam Girdwood u32 stack[BDW_STACK_DUMP_SIZE]; 244458bc729SLiam Girdwood u32 status, panic; 245458bc729SLiam Girdwood 246458bc729SLiam Girdwood /* now try generic SOF status messages */ 247458bc729SLiam Girdwood status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 248458bc729SLiam Girdwood panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 249458bc729SLiam Girdwood bdw_get_registers(sdev, &xoops, &panic_info, stack, 250458bc729SLiam Girdwood BDW_STACK_DUMP_SIZE); 251458bc729SLiam Girdwood snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 252458bc729SLiam Girdwood BDW_STACK_DUMP_SIZE); 253458bc729SLiam Girdwood } 254458bc729SLiam Girdwood 255458bc729SLiam Girdwood /* 256458bc729SLiam Girdwood * IPC Doorbell IRQ handler and thread. 257458bc729SLiam Girdwood */ 258458bc729SLiam Girdwood 259458bc729SLiam Girdwood static irqreturn_t bdw_irq_handler(int irq, void *context) 260458bc729SLiam Girdwood { 261458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 262458bc729SLiam Girdwood u32 isr; 263458bc729SLiam Girdwood int ret = IRQ_NONE; 264458bc729SLiam Girdwood 265458bc729SLiam Girdwood /* Interrupt arrived, check src */ 266458bc729SLiam Girdwood isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX); 267458bc729SLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 268458bc729SLiam Girdwood ret = IRQ_WAKE_THREAD; 269458bc729SLiam Girdwood 270458bc729SLiam Girdwood return ret; 271458bc729SLiam Girdwood } 272458bc729SLiam Girdwood 273458bc729SLiam Girdwood static irqreturn_t bdw_irq_thread(int irq, void *context) 274458bc729SLiam Girdwood { 275458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 276458bc729SLiam Girdwood u32 ipcx, ipcd, imrx; 277458bc729SLiam Girdwood 278458bc729SLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX); 279458bc729SLiam Girdwood ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 280458bc729SLiam Girdwood 281458bc729SLiam Girdwood /* reply message from DSP */ 282458bc729SLiam Girdwood if (ipcx & SHIM_IPCX_DONE && 283458bc729SLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 284458bc729SLiam Girdwood /* Mask Done interrupt before return */ 285458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 286458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_DONE, 287458bc729SLiam Girdwood SHIM_IMRX_DONE); 288458bc729SLiam Girdwood 2891183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 2901183e9a6SGuennadi Liakhovetski 291458bc729SLiam Girdwood /* 292458bc729SLiam Girdwood * handle immediate reply from DSP core. If the msg is 293458bc729SLiam Girdwood * found, set done bit in cmd_done which is called at the 294458bc729SLiam Girdwood * end of message processing function, else set it here 295458bc729SLiam Girdwood * because the done bit can't be set in cmd_done function 296458bc729SLiam Girdwood * which is triggered by msg 297458bc729SLiam Girdwood */ 298458bc729SLiam Girdwood bdw_get_reply(sdev); 299458bc729SLiam Girdwood snd_sof_ipc_reply(sdev, ipcx); 300458bc729SLiam Girdwood 301458bc729SLiam Girdwood bdw_dsp_done(sdev); 3021183e9a6SGuennadi Liakhovetski 3031183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 304458bc729SLiam Girdwood } 305458bc729SLiam Girdwood 306458bc729SLiam Girdwood ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 307458bc729SLiam Girdwood 308458bc729SLiam Girdwood /* new message from DSP */ 309458bc729SLiam Girdwood if (ipcd & SHIM_IPCD_BUSY && 310458bc729SLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 311458bc729SLiam Girdwood /* Mask Busy interrupt before return */ 312458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 313458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_BUSY, 314458bc729SLiam Girdwood SHIM_IMRX_BUSY); 315458bc729SLiam Girdwood 316458bc729SLiam Girdwood /* Handle messages from DSP Core */ 317458bc729SLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 318458bc729SLiam Girdwood snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + 319458bc729SLiam Girdwood MBOX_OFFSET); 320458bc729SLiam Girdwood } else { 321458bc729SLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 322458bc729SLiam Girdwood } 323458bc729SLiam Girdwood 324458bc729SLiam Girdwood bdw_host_done(sdev); 325458bc729SLiam Girdwood } 326458bc729SLiam Girdwood 327458bc729SLiam Girdwood return IRQ_HANDLED; 328458bc729SLiam Girdwood } 329458bc729SLiam Girdwood 330458bc729SLiam Girdwood /* 331458bc729SLiam Girdwood * IPC Mailbox IO 332458bc729SLiam Girdwood */ 333458bc729SLiam Girdwood 334458bc729SLiam Girdwood static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 335458bc729SLiam Girdwood { 336458bc729SLiam Girdwood /* send the message */ 337458bc729SLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 338458bc729SLiam Girdwood msg->msg_size); 339458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY); 340458bc729SLiam Girdwood 341458bc729SLiam Girdwood return 0; 342458bc729SLiam Girdwood } 343458bc729SLiam Girdwood 344458bc729SLiam Girdwood static void bdw_get_reply(struct snd_sof_dev *sdev) 345458bc729SLiam Girdwood { 346458bc729SLiam Girdwood struct snd_sof_ipc_msg *msg = sdev->msg; 347458bc729SLiam Girdwood struct sof_ipc_reply reply; 348458bc729SLiam Girdwood int ret = 0; 349458bc729SLiam Girdwood 350458bc729SLiam Girdwood /* 351458bc729SLiam Girdwood * Sometimes, there is unexpected reply ipc arriving. The reply 352458bc729SLiam Girdwood * ipc belongs to none of the ipcs sent from driver. 353458bc729SLiam Girdwood * In this case, the driver must ignore the ipc. 354458bc729SLiam Girdwood */ 355458bc729SLiam Girdwood if (!msg) { 356458bc729SLiam Girdwood dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 357458bc729SLiam Girdwood return; 358458bc729SLiam Girdwood } 359458bc729SLiam Girdwood 360458bc729SLiam Girdwood /* get reply */ 361458bc729SLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 362458bc729SLiam Girdwood 363458bc729SLiam Girdwood if (reply.error < 0) { 364458bc729SLiam Girdwood memcpy(msg->reply_data, &reply, sizeof(reply)); 365458bc729SLiam Girdwood ret = reply.error; 366458bc729SLiam Girdwood } else { 367458bc729SLiam Girdwood /* reply correct size ? */ 368458bc729SLiam Girdwood if (reply.hdr.size != msg->reply_size) { 369458bc729SLiam Girdwood dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 370458bc729SLiam Girdwood msg->reply_size, reply.hdr.size); 371458bc729SLiam Girdwood ret = -EINVAL; 372458bc729SLiam Girdwood } 373458bc729SLiam Girdwood 374458bc729SLiam Girdwood /* read the message */ 375458bc729SLiam Girdwood if (msg->reply_size > 0) 376458bc729SLiam Girdwood sof_mailbox_read(sdev, sdev->host_box.offset, 377458bc729SLiam Girdwood msg->reply_data, msg->reply_size); 378458bc729SLiam Girdwood } 379458bc729SLiam Girdwood 380458bc729SLiam Girdwood msg->reply_error = ret; 381458bc729SLiam Girdwood } 382458bc729SLiam Girdwood 383ddf14b64SDaniel Baluta static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev) 384ddf14b64SDaniel Baluta { 385ddf14b64SDaniel Baluta return MBOX_OFFSET; 386ddf14b64SDaniel Baluta } 387ddf14b64SDaniel Baluta 388ddf14b64SDaniel Baluta static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id) 389ddf14b64SDaniel Baluta { 390ddf14b64SDaniel Baluta return MBOX_OFFSET; 391ddf14b64SDaniel Baluta } 392ddf14b64SDaniel Baluta 393458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev) 394458bc729SLiam Girdwood { 395458bc729SLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 396458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD, 397458bc729SLiam Girdwood SHIM_IPCD_BUSY | SHIM_IPCD_DONE, 398458bc729SLiam Girdwood SHIM_IPCD_DONE); 399458bc729SLiam Girdwood 400458bc729SLiam Girdwood /* unmask busy interrupt */ 401458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 402458bc729SLiam Girdwood SHIM_IMRX_BUSY, 0); 403458bc729SLiam Girdwood } 404458bc729SLiam Girdwood 405458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev) 406458bc729SLiam Girdwood { 407458bc729SLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 408458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX, 409458bc729SLiam Girdwood SHIM_IPCX_DONE, 0); 410458bc729SLiam Girdwood 411458bc729SLiam Girdwood /* unmask Done interrupt */ 412458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 413458bc729SLiam Girdwood SHIM_IMRX_DONE, 0); 414458bc729SLiam Girdwood } 415458bc729SLiam Girdwood 416458bc729SLiam Girdwood /* 417458bc729SLiam Girdwood * Probe and remove. 418458bc729SLiam Girdwood */ 419458bc729SLiam Girdwood static int bdw_probe(struct snd_sof_dev *sdev) 420458bc729SLiam Girdwood { 421458bc729SLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 422458bc729SLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 423458bc729SLiam Girdwood struct platform_device *pdev = 424458bc729SLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 425458bc729SLiam Girdwood struct resource *mmio; 426458bc729SLiam Girdwood u32 base, size; 427458bc729SLiam Girdwood int ret; 428458bc729SLiam Girdwood 429458bc729SLiam Girdwood /* LPE base */ 430458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 431458bc729SLiam Girdwood desc->resindex_lpe_base); 432458bc729SLiam Girdwood if (mmio) { 433458bc729SLiam Girdwood base = mmio->start; 434458bc729SLiam Girdwood size = resource_size(mmio); 435458bc729SLiam Girdwood } else { 436458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 437458bc729SLiam Girdwood desc->resindex_lpe_base); 438458bc729SLiam Girdwood return -EINVAL; 439458bc729SLiam Girdwood } 440458bc729SLiam Girdwood 441458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 442458bc729SLiam Girdwood sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 443458bc729SLiam Girdwood if (!sdev->bar[BDW_DSP_BAR]) { 444458bc729SLiam Girdwood dev_err(sdev->dev, 445458bc729SLiam Girdwood "error: failed to ioremap LPE base 0x%x size 0x%x\n", 446458bc729SLiam Girdwood base, size); 447458bc729SLiam Girdwood return -ENODEV; 448458bc729SLiam Girdwood } 449458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]); 450458bc729SLiam Girdwood 451458bc729SLiam Girdwood /* TODO: add offsets */ 452458bc729SLiam Girdwood sdev->mmio_bar = BDW_DSP_BAR; 453458bc729SLiam Girdwood sdev->mailbox_bar = BDW_DSP_BAR; 454458bc729SLiam Girdwood 455458bc729SLiam Girdwood /* PCI base */ 456458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 457458bc729SLiam Girdwood desc->resindex_pcicfg_base); 458458bc729SLiam Girdwood if (mmio) { 459458bc729SLiam Girdwood base = mmio->start; 460458bc729SLiam Girdwood size = resource_size(mmio); 461458bc729SLiam Girdwood } else { 462458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n", 463458bc729SLiam Girdwood desc->resindex_pcicfg_base); 464458bc729SLiam Girdwood return -ENODEV; 465458bc729SLiam Girdwood } 466458bc729SLiam Girdwood 467458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size); 468458bc729SLiam Girdwood sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size); 469458bc729SLiam Girdwood if (!sdev->bar[BDW_PCI_BAR]) { 470458bc729SLiam Girdwood dev_err(sdev->dev, 471458bc729SLiam Girdwood "error: failed to ioremap PCI base 0x%x size 0x%x\n", 472458bc729SLiam Girdwood base, size); 473458bc729SLiam Girdwood return -ENODEV; 474458bc729SLiam Girdwood } 475458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]); 476458bc729SLiam Girdwood 477458bc729SLiam Girdwood /* register our IRQ */ 478458bc729SLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 479cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 480458bc729SLiam Girdwood return sdev->ipc_irq; 481458bc729SLiam Girdwood 482458bc729SLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 483458bc729SLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 484458bc729SLiam Girdwood bdw_irq_handler, bdw_irq_thread, 485458bc729SLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 486458bc729SLiam Girdwood if (ret < 0) { 487458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 488458bc729SLiam Girdwood sdev->ipc_irq); 489458bc729SLiam Girdwood return ret; 490458bc729SLiam Girdwood } 491458bc729SLiam Girdwood 492458bc729SLiam Girdwood /* enable the DSP SHIM */ 493458bc729SLiam Girdwood ret = bdw_set_dsp_D0(sdev); 494458bc729SLiam Girdwood if (ret < 0) { 495458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DSP D0\n"); 496458bc729SLiam Girdwood return ret; 497458bc729SLiam Girdwood } 498458bc729SLiam Girdwood 499458bc729SLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 500458bc729SLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 501458bc729SLiam Girdwood if (ret < 0) { 502458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 503458bc729SLiam Girdwood return ret; 504458bc729SLiam Girdwood } 505458bc729SLiam Girdwood 506458bc729SLiam Girdwood /* set default mailbox */ 507458bc729SLiam Girdwood snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0); 508458bc729SLiam Girdwood 509458bc729SLiam Girdwood return ret; 510458bc729SLiam Girdwood } 511458bc729SLiam Girdwood 512458bc729SLiam Girdwood /* Broadwell DAIs */ 513458bc729SLiam Girdwood static struct snd_soc_dai_driver bdw_dai[] = { 514458bc729SLiam Girdwood { 515458bc729SLiam Girdwood .name = "ssp0-port", 516458bc729SLiam Girdwood }, 517458bc729SLiam Girdwood { 518458bc729SLiam Girdwood .name = "ssp1-port", 519458bc729SLiam Girdwood }, 520458bc729SLiam Girdwood }; 521458bc729SLiam Girdwood 522458bc729SLiam Girdwood /* broadwell ops */ 523458bc729SLiam Girdwood const struct snd_sof_dsp_ops sof_bdw_ops = { 524458bc729SLiam Girdwood /*Device init */ 525458bc729SLiam Girdwood .probe = bdw_probe, 526458bc729SLiam Girdwood 527458bc729SLiam Girdwood /* DSP Core Control */ 528458bc729SLiam Girdwood .run = bdw_run, 529458bc729SLiam Girdwood .reset = bdw_reset, 530458bc729SLiam Girdwood 531458bc729SLiam Girdwood /* Register IO */ 532458bc729SLiam Girdwood .write = sof_io_write, 533458bc729SLiam Girdwood .read = sof_io_read, 534458bc729SLiam Girdwood .write64 = sof_io_write64, 535458bc729SLiam Girdwood .read64 = sof_io_read64, 536458bc729SLiam Girdwood 537458bc729SLiam Girdwood /* Block IO */ 538458bc729SLiam Girdwood .block_read = sof_block_read, 539458bc729SLiam Girdwood .block_write = sof_block_write, 540458bc729SLiam Girdwood 541458bc729SLiam Girdwood /* ipc */ 542458bc729SLiam Girdwood .send_msg = bdw_send_msg, 543ddf14b64SDaniel Baluta .fw_ready = sof_fw_ready, 544ddf14b64SDaniel Baluta .get_mailbox_offset = bdw_get_mailbox_offset, 545ddf14b64SDaniel Baluta .get_window_offset = bdw_get_window_offset, 546458bc729SLiam Girdwood 547458bc729SLiam Girdwood .ipc_msg_data = intel_ipc_msg_data, 548458bc729SLiam Girdwood .ipc_pcm_params = intel_ipc_pcm_params, 549458bc729SLiam Girdwood 550458bc729SLiam Girdwood /* debug */ 551458bc729SLiam Girdwood .debug_map = bdw_debugfs, 552458bc729SLiam Girdwood .debug_map_count = ARRAY_SIZE(bdw_debugfs), 553458bc729SLiam Girdwood .dbg_dump = bdw_dump, 554458bc729SLiam Girdwood 555458bc729SLiam Girdwood /* stream callbacks */ 556458bc729SLiam Girdwood .pcm_open = intel_pcm_open, 557458bc729SLiam Girdwood .pcm_close = intel_pcm_close, 558458bc729SLiam Girdwood 559458bc729SLiam Girdwood /* Module loading */ 560458bc729SLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 561458bc729SLiam Girdwood 562458bc729SLiam Girdwood /*Firmware loading */ 563458bc729SLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 564458bc729SLiam Girdwood 565458bc729SLiam Girdwood /* DAI drivers */ 566458bc729SLiam Girdwood .drv = bdw_dai, 567458bc729SLiam Girdwood .num_drv = ARRAY_SIZE(bdw_dai) 568458bc729SLiam Girdwood }; 569458bc729SLiam Girdwood EXPORT_SYMBOL(sof_bdw_ops); 570458bc729SLiam Girdwood 571458bc729SLiam Girdwood const struct sof_intel_dsp_desc bdw_chip_info = { 572458bc729SLiam Girdwood .cores_num = 1, 573458bc729SLiam Girdwood .cores_mask = 1, 574458bc729SLiam Girdwood }; 575458bc729SLiam Girdwood EXPORT_SYMBOL(bdw_chip_info); 576458bc729SLiam Girdwood 577458bc729SLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 578