1e149ca29SPierre-Louis Bossart // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2458bc729SLiam Girdwood // 3458bc729SLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 4458bc729SLiam Girdwood // redistributing this file, you may do so under either license. 5458bc729SLiam Girdwood // 6458bc729SLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 7458bc729SLiam Girdwood // 8458bc729SLiam Girdwood // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9458bc729SLiam Girdwood // 10458bc729SLiam Girdwood 11458bc729SLiam Girdwood /* 12458bc729SLiam Girdwood * Hardware interface for audio DSP on Broadwell 13458bc729SLiam Girdwood */ 14458bc729SLiam Girdwood 15458bc729SLiam Girdwood #include <linux/module.h> 16458bc729SLiam Girdwood #include <sound/sof.h> 17458bc729SLiam Girdwood #include <sound/sof/xtensa.h> 188a49cd11SArnd Bergmann #include <sound/soc-acpi.h> 198a49cd11SArnd Bergmann #include <sound/soc-acpi-intel-match.h> 208a49cd11SArnd Bergmann #include <sound/intel-dsp-config.h> 21458bc729SLiam Girdwood #include "../ops.h" 22458bc729SLiam Girdwood #include "shim.h" 238a49cd11SArnd Bergmann #include "../sof-acpi-dev.h" 24285880a2SDaniel Baluta #include "../sof-audio.h" 25458bc729SLiam Girdwood 26458bc729SLiam Girdwood /* BARs */ 27458bc729SLiam Girdwood #define BDW_DSP_BAR 0 28458bc729SLiam Girdwood #define BDW_PCI_BAR 1 29458bc729SLiam Girdwood 30458bc729SLiam Girdwood /* 31458bc729SLiam Girdwood * Debug 32458bc729SLiam Girdwood */ 33458bc729SLiam Girdwood 34458bc729SLiam Girdwood /* DSP memories for BDW */ 35458bc729SLiam Girdwood #define IRAM_OFFSET 0xA0000 36458bc729SLiam Girdwood #define BDW_IRAM_SIZE (10 * 32 * 1024) 37458bc729SLiam Girdwood #define DRAM_OFFSET 0x00000 38458bc729SLiam Girdwood #define BDW_DRAM_SIZE (20 * 32 * 1024) 39458bc729SLiam Girdwood #define SHIM_OFFSET 0xFB000 40458bc729SLiam Girdwood #define SHIM_SIZE 0x100 41458bc729SLiam Girdwood #define MBOX_OFFSET 0x9E000 42458bc729SLiam Girdwood #define MBOX_SIZE 0x1000 43458bc729SLiam Girdwood #define MBOX_DUMP_SIZE 0x30 44458bc729SLiam Girdwood #define EXCEPT_OFFSET 0x800 45ff2be865SLiam Girdwood #define EXCEPT_MAX_HDR_SIZE 0x400 46458bc729SLiam Girdwood 47458bc729SLiam Girdwood /* DSP peripherals */ 48458bc729SLiam Girdwood #define DMAC0_OFFSET 0xFE000 49458bc729SLiam Girdwood #define DMAC1_OFFSET 0xFF000 50458bc729SLiam Girdwood #define DMAC_SIZE 0x420 51458bc729SLiam Girdwood #define SSP0_OFFSET 0xFC000 52458bc729SLiam Girdwood #define SSP1_OFFSET 0xFD000 53458bc729SLiam Girdwood #define SSP_SIZE 0x100 54458bc729SLiam Girdwood 55458bc729SLiam Girdwood #define BDW_STACK_DUMP_SIZE 32 56458bc729SLiam Girdwood 57458bc729SLiam Girdwood #define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF) 58458bc729SLiam Girdwood 59458bc729SLiam Girdwood static const struct snd_sof_debugfs_map bdw_debugfs[] = { 60458bc729SLiam Girdwood {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 61458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 62458bc729SLiam Girdwood {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 63458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 64458bc729SLiam Girdwood {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 65458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 66458bc729SLiam Girdwood {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 67458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 68458bc729SLiam Girdwood {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE, 69458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 70458bc729SLiam Girdwood {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE, 71458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_D0_ONLY}, 72458bc729SLiam Girdwood {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE, 73458bc729SLiam Girdwood SOF_DEBUGFS_ACCESS_ALWAYS}, 74458bc729SLiam Girdwood }; 75458bc729SLiam Girdwood 76458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev); 77458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev); 78458bc729SLiam Girdwood 79458bc729SLiam Girdwood /* 80458bc729SLiam Girdwood * DSP Control. 81458bc729SLiam Girdwood */ 82458bc729SLiam Girdwood 83458bc729SLiam Girdwood static int bdw_run(struct snd_sof_dev *sdev) 84458bc729SLiam Girdwood { 85458bc729SLiam Girdwood /* set opportunistic mode on engine 0,1 for all channels */ 86458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 87458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 88458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 0); 89458bc729SLiam Girdwood 90458bc729SLiam Girdwood /* set DSP to RUN */ 91458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 92458bc729SLiam Girdwood SHIM_CSR_STALL, 0x0); 93458bc729SLiam Girdwood 94458bc729SLiam Girdwood /* return init core mask */ 95458bc729SLiam Girdwood return 1; 96458bc729SLiam Girdwood } 97458bc729SLiam Girdwood 98458bc729SLiam Girdwood static int bdw_reset(struct snd_sof_dev *sdev) 99458bc729SLiam Girdwood { 100458bc729SLiam Girdwood /* put DSP into reset and stall */ 101458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 102458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 103458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL); 104458bc729SLiam Girdwood 105458bc729SLiam Girdwood /* keep in reset for 10ms */ 106458bc729SLiam Girdwood mdelay(10); 107458bc729SLiam Girdwood 108458bc729SLiam Girdwood /* take DSP out of reset and keep stalled for FW loading */ 109458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 110458bc729SLiam Girdwood SHIM_CSR_RST | SHIM_CSR_STALL, 111458bc729SLiam Girdwood SHIM_CSR_STALL); 112458bc729SLiam Girdwood 113458bc729SLiam Girdwood return 0; 114458bc729SLiam Girdwood } 115458bc729SLiam Girdwood 116458bc729SLiam Girdwood static int bdw_set_dsp_D0(struct snd_sof_dev *sdev) 117458bc729SLiam Girdwood { 118458bc729SLiam Girdwood int tries = 10; 119458bc729SLiam Girdwood u32 reg; 120458bc729SLiam Girdwood 121458bc729SLiam Girdwood /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ 122458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 123458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 124458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 0); 125458bc729SLiam Girdwood 126458bc729SLiam Girdwood /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ 127458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 128458bc729SLiam Girdwood PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD); 129458bc729SLiam Girdwood 130458bc729SLiam Girdwood /* Set D0 state */ 131458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS, 132458bc729SLiam Girdwood PCI_PMCS_PS_MASK, 0); 133458bc729SLiam Girdwood 134458bc729SLiam Girdwood /* check that ADSP shim is enabled */ 135458bc729SLiam Girdwood while (tries--) { 136458bc729SLiam Girdwood reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS) 137458bc729SLiam Girdwood & PCI_PMCS_PS_MASK; 138458bc729SLiam Girdwood if (reg == 0) 139458bc729SLiam Girdwood goto finish; 140458bc729SLiam Girdwood 141458bc729SLiam Girdwood msleep(20); 142458bc729SLiam Girdwood } 143458bc729SLiam Girdwood 144458bc729SLiam Girdwood return -ENODEV; 145458bc729SLiam Girdwood 146458bc729SLiam Girdwood finish: 147458bc729SLiam Girdwood /* 148458bc729SLiam Girdwood * select SSP1 19.2MHz base clock, SSP clock 0, 149458bc729SLiam Girdwood * turn off Low Power Clock 150458bc729SLiam Girdwood */ 151458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR, 152458bc729SLiam Girdwood SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 | 153458bc729SLiam Girdwood SHIM_CSR_LPCS, 0x0); 154458bc729SLiam Girdwood 155458bc729SLiam Girdwood /* stall DSP core, set clk to 192/96Mhz */ 156458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 157458bc729SLiam Girdwood SHIM_CSR, SHIM_CSR_STALL | 158458bc729SLiam Girdwood SHIM_CSR_DCS_MASK, 159458bc729SLiam Girdwood SHIM_CSR_STALL | 160458bc729SLiam Girdwood SHIM_CSR_DCS(4)); 161458bc729SLiam Girdwood 162458bc729SLiam Girdwood /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ 163458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL, 164458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 165458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 166458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0, 167458bc729SLiam Girdwood SHIM_CLKCTL_MASK | 168458bc729SLiam Girdwood SHIM_CLKCTL_DCPLCG | 169458bc729SLiam Girdwood SHIM_CLKCTL_SCOE0); 170458bc729SLiam Girdwood 171458bc729SLiam Girdwood /* Stall and reset core, set CSR */ 172458bc729SLiam Girdwood bdw_reset(sdev); 173458bc729SLiam Girdwood 174458bc729SLiam Girdwood /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ 175458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 176458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 177458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE, 178458bc729SLiam Girdwood PCI_VDRTCL2_DCLCGE | 179458bc729SLiam Girdwood PCI_VDRTCL2_DTCGE); 180458bc729SLiam Girdwood 181458bc729SLiam Girdwood usleep_range(50, 55); 182458bc729SLiam Girdwood 183458bc729SLiam Girdwood /* switch on audio PLL */ 184458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2, 185458bc729SLiam Girdwood PCI_VDRTCL2_APLLSE_MASK, 0); 186458bc729SLiam Girdwood 187458bc729SLiam Girdwood /* 188458bc729SLiam Girdwood * set default power gating control, enable power gating control for 189458bc729SLiam Girdwood * all blocks. that is, can't be accessed, please enable each block 190458bc729SLiam Girdwood * before accessing. 191458bc729SLiam Girdwood */ 192458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0, 193458bc729SLiam Girdwood 0xfffffffC, 0x0); 194458bc729SLiam Girdwood 195458bc729SLiam Girdwood /* disable DMA finish function for SSP0 & SSP1 */ 196458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2, 197458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1, 198458bc729SLiam Girdwood SHIM_CSR2_SDFD_SSP1); 199458bc729SLiam Girdwood 200458bc729SLiam Girdwood /* set on-demond mode on engine 0,1 for all channels */ 201458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC, 202458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 203458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH, 204458bc729SLiam Girdwood SHIM_HMDC_HDDA_E0_ALLCH | 205458bc729SLiam Girdwood SHIM_HMDC_HDDA_E1_ALLCH); 206458bc729SLiam Girdwood 207458bc729SLiam Girdwood /* Enable Interrupt from both sides */ 208458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX, 209458bc729SLiam Girdwood (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0); 210458bc729SLiam Girdwood snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD, 211458bc729SLiam Girdwood (SHIM_IMRD_DONE | SHIM_IMRD_BUSY | 212458bc729SLiam Girdwood SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0); 213458bc729SLiam Girdwood 214458bc729SLiam Girdwood /* clear IPC registers */ 215458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0); 216458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0); 217458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6); 218458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a); 219458bc729SLiam Girdwood 220458bc729SLiam Girdwood return 0; 221458bc729SLiam Girdwood } 222458bc729SLiam Girdwood 223458bc729SLiam Girdwood static void bdw_get_registers(struct snd_sof_dev *sdev, 224458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa *xoops, 225458bc729SLiam Girdwood struct sof_ipc_panic_info *panic_info, 226458bc729SLiam Girdwood u32 *stack, size_t stack_words) 227458bc729SLiam Girdwood { 22814104eb6SKai Vehmanen u32 offset = sdev->dsp_oops_offset; 22914104eb6SKai Vehmanen 23014104eb6SKai Vehmanen /* first read registers */ 23114104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 23214104eb6SKai Vehmanen 23314104eb6SKai Vehmanen /* note: variable AR register array is not read */ 234458bc729SLiam Girdwood 235458bc729SLiam Girdwood /* then get panic info */ 236ff2be865SLiam Girdwood if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 237ff2be865SLiam Girdwood dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 238ff2be865SLiam Girdwood xoops->arch_hdr.totalsize); 239ff2be865SLiam Girdwood return; 240ff2be865SLiam Girdwood } 24114104eb6SKai Vehmanen offset += xoops->arch_hdr.totalsize; 24214104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 243458bc729SLiam Girdwood 244458bc729SLiam Girdwood /* then get the stack */ 24514104eb6SKai Vehmanen offset += sizeof(*panic_info); 24614104eb6SKai Vehmanen sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 247458bc729SLiam Girdwood } 248458bc729SLiam Girdwood 249458bc729SLiam Girdwood static void bdw_dump(struct snd_sof_dev *sdev, u32 flags) 250458bc729SLiam Girdwood { 251458bc729SLiam Girdwood struct sof_ipc_dsp_oops_xtensa xoops; 252458bc729SLiam Girdwood struct sof_ipc_panic_info panic_info; 253458bc729SLiam Girdwood u32 stack[BDW_STACK_DUMP_SIZE]; 2543a9e204dSLiam Girdwood u32 status, panic, imrx, imrd; 255458bc729SLiam Girdwood 256458bc729SLiam Girdwood /* now try generic SOF status messages */ 257458bc729SLiam Girdwood status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 258458bc729SLiam Girdwood panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 259458bc729SLiam Girdwood bdw_get_registers(sdev, &xoops, &panic_info, stack, 260458bc729SLiam Girdwood BDW_STACK_DUMP_SIZE); 2614995ffceSPeter Ujfalusi sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops, 2624995ffceSPeter Ujfalusi &panic_info, stack, BDW_STACK_DUMP_SIZE); 2633a9e204dSLiam Girdwood 2643a9e204dSLiam Girdwood /* provide some context for firmware debug */ 2653a9e204dSLiam Girdwood imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX); 2663a9e204dSLiam Girdwood imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD); 2673a9e204dSLiam Girdwood dev_err(sdev->dev, 2683a9e204dSLiam Girdwood "error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n", 2697ad03a2cSPierre-Louis Bossart (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 2707ad03a2cSPierre-Louis Bossart (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 2713a9e204dSLiam Girdwood dev_err(sdev->dev, 2723a9e204dSLiam Girdwood "error: mask host: pending %s complete %s raw 0x%8.8x\n", 2737ad03a2cSPierre-Louis Bossart (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 2747ad03a2cSPierre-Louis Bossart (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 2753a9e204dSLiam Girdwood dev_err(sdev->dev, 2763a9e204dSLiam Girdwood "error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n", 2777ad03a2cSPierre-Louis Bossart (status & SHIM_IPCD_BUSY) ? "yes" : "no", 2787ad03a2cSPierre-Louis Bossart (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 2793a9e204dSLiam Girdwood dev_err(sdev->dev, 2803a9e204dSLiam Girdwood "error: mask DSP: pending %s complete %s raw 0x%8.8x\n", 2817ad03a2cSPierre-Louis Bossart (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 2827ad03a2cSPierre-Louis Bossart (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 283458bc729SLiam Girdwood } 284458bc729SLiam Girdwood 285458bc729SLiam Girdwood /* 286458bc729SLiam Girdwood * IPC Doorbell IRQ handler and thread. 287458bc729SLiam Girdwood */ 288458bc729SLiam Girdwood 289458bc729SLiam Girdwood static irqreturn_t bdw_irq_handler(int irq, void *context) 290458bc729SLiam Girdwood { 291458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 292458bc729SLiam Girdwood u32 isr; 293458bc729SLiam Girdwood int ret = IRQ_NONE; 294458bc729SLiam Girdwood 295458bc729SLiam Girdwood /* Interrupt arrived, check src */ 296458bc729SLiam Girdwood isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX); 297458bc729SLiam Girdwood if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) 298458bc729SLiam Girdwood ret = IRQ_WAKE_THREAD; 299458bc729SLiam Girdwood 300458bc729SLiam Girdwood return ret; 301458bc729SLiam Girdwood } 302458bc729SLiam Girdwood 303458bc729SLiam Girdwood static irqreturn_t bdw_irq_thread(int irq, void *context) 304458bc729SLiam Girdwood { 305458bc729SLiam Girdwood struct snd_sof_dev *sdev = context; 306458bc729SLiam Girdwood u32 ipcx, ipcd, imrx; 307458bc729SLiam Girdwood 308458bc729SLiam Girdwood imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX); 309458bc729SLiam Girdwood ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX); 310458bc729SLiam Girdwood 311458bc729SLiam Girdwood /* reply message from DSP */ 312458bc729SLiam Girdwood if (ipcx & SHIM_IPCX_DONE && 313458bc729SLiam Girdwood !(imrx & SHIM_IMRX_DONE)) { 314458bc729SLiam Girdwood /* Mask Done interrupt before return */ 315458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 316458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_DONE, 317458bc729SLiam Girdwood SHIM_IMRX_DONE); 318458bc729SLiam Girdwood 3191183e9a6SGuennadi Liakhovetski spin_lock_irq(&sdev->ipc_lock); 3201183e9a6SGuennadi Liakhovetski 321458bc729SLiam Girdwood /* 322458bc729SLiam Girdwood * handle immediate reply from DSP core. If the msg is 323458bc729SLiam Girdwood * found, set done bit in cmd_done which is called at the 324458bc729SLiam Girdwood * end of message processing function, else set it here 325458bc729SLiam Girdwood * because the done bit can't be set in cmd_done function 326458bc729SLiam Girdwood * which is triggered by msg 327458bc729SLiam Girdwood */ 3280bd2891bSPeter Ujfalusi snd_sof_ipc_process_reply(sdev, ipcx); 329458bc729SLiam Girdwood 330458bc729SLiam Girdwood bdw_dsp_done(sdev); 3311183e9a6SGuennadi Liakhovetski 3321183e9a6SGuennadi Liakhovetski spin_unlock_irq(&sdev->ipc_lock); 333458bc729SLiam Girdwood } 334458bc729SLiam Girdwood 335458bc729SLiam Girdwood ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD); 336458bc729SLiam Girdwood 337458bc729SLiam Girdwood /* new message from DSP */ 338458bc729SLiam Girdwood if (ipcd & SHIM_IPCD_BUSY && 339458bc729SLiam Girdwood !(imrx & SHIM_IMRX_BUSY)) { 340458bc729SLiam Girdwood /* Mask Busy interrupt before return */ 341458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, 342458bc729SLiam Girdwood SHIM_IMRX, SHIM_IMRX_BUSY, 343458bc729SLiam Girdwood SHIM_IMRX_BUSY); 344458bc729SLiam Girdwood 345458bc729SLiam Girdwood /* Handle messages from DSP Core */ 346458bc729SLiam Girdwood if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 347b2b10aa7SPeter Ujfalusi snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + MBOX_OFFSET, 348b2b10aa7SPeter Ujfalusi true); 349458bc729SLiam Girdwood } else { 350458bc729SLiam Girdwood snd_sof_ipc_msgs_rx(sdev); 351458bc729SLiam Girdwood } 352458bc729SLiam Girdwood 353458bc729SLiam Girdwood bdw_host_done(sdev); 354458bc729SLiam Girdwood } 355458bc729SLiam Girdwood 356458bc729SLiam Girdwood return IRQ_HANDLED; 357458bc729SLiam Girdwood } 358458bc729SLiam Girdwood 359458bc729SLiam Girdwood /* 360458bc729SLiam Girdwood * IPC Mailbox IO 361458bc729SLiam Girdwood */ 362458bc729SLiam Girdwood 363458bc729SLiam Girdwood static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 364458bc729SLiam Girdwood { 365458bc729SLiam Girdwood /* send the message */ 366458bc729SLiam Girdwood sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 367458bc729SLiam Girdwood msg->msg_size); 368458bc729SLiam Girdwood snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY); 369458bc729SLiam Girdwood 370458bc729SLiam Girdwood return 0; 371458bc729SLiam Girdwood } 372458bc729SLiam Girdwood 373ddf14b64SDaniel Baluta static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev) 374ddf14b64SDaniel Baluta { 375ddf14b64SDaniel Baluta return MBOX_OFFSET; 376ddf14b64SDaniel Baluta } 377ddf14b64SDaniel Baluta 378ddf14b64SDaniel Baluta static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id) 379ddf14b64SDaniel Baluta { 380ddf14b64SDaniel Baluta return MBOX_OFFSET; 381ddf14b64SDaniel Baluta } 382ddf14b64SDaniel Baluta 383458bc729SLiam Girdwood static void bdw_host_done(struct snd_sof_dev *sdev) 384458bc729SLiam Girdwood { 385458bc729SLiam Girdwood /* clear BUSY bit and set DONE bit - accept new messages */ 386458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD, 387458bc729SLiam Girdwood SHIM_IPCD_BUSY | SHIM_IPCD_DONE, 388458bc729SLiam Girdwood SHIM_IPCD_DONE); 389458bc729SLiam Girdwood 390458bc729SLiam Girdwood /* unmask busy interrupt */ 391458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 392458bc729SLiam Girdwood SHIM_IMRX_BUSY, 0); 393458bc729SLiam Girdwood } 394458bc729SLiam Girdwood 395458bc729SLiam Girdwood static void bdw_dsp_done(struct snd_sof_dev *sdev) 396458bc729SLiam Girdwood { 397458bc729SLiam Girdwood /* clear DONE bit - tell DSP we have completed */ 398458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX, 399458bc729SLiam Girdwood SHIM_IPCX_DONE, 0); 400458bc729SLiam Girdwood 401458bc729SLiam Girdwood /* unmask Done interrupt */ 402458bc729SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX, 403458bc729SLiam Girdwood SHIM_IMRX_DONE, 0); 404458bc729SLiam Girdwood } 405458bc729SLiam Girdwood 406458bc729SLiam Girdwood /* 407458bc729SLiam Girdwood * Probe and remove. 408458bc729SLiam Girdwood */ 409458bc729SLiam Girdwood static int bdw_probe(struct snd_sof_dev *sdev) 410458bc729SLiam Girdwood { 411458bc729SLiam Girdwood struct snd_sof_pdata *pdata = sdev->pdata; 412458bc729SLiam Girdwood const struct sof_dev_desc *desc = pdata->desc; 413458bc729SLiam Girdwood struct platform_device *pdev = 414458bc729SLiam Girdwood container_of(sdev->dev, struct platform_device, dev); 4155974f684SRanjani Sridharan const struct sof_intel_dsp_desc *chip; 416458bc729SLiam Girdwood struct resource *mmio; 417458bc729SLiam Girdwood u32 base, size; 418458bc729SLiam Girdwood int ret; 419458bc729SLiam Girdwood 4205974f684SRanjani Sridharan chip = get_chip_info(sdev->pdata); 4215974f684SRanjani Sridharan if (!chip) { 4225974f684SRanjani Sridharan dev_err(sdev->dev, "error: no such device supported\n"); 4235974f684SRanjani Sridharan return -EIO; 4245974f684SRanjani Sridharan } 4255974f684SRanjani Sridharan 4265974f684SRanjani Sridharan sdev->num_cores = chip->cores_num; 4275974f684SRanjani Sridharan 428458bc729SLiam Girdwood /* LPE base */ 429458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 430458bc729SLiam Girdwood desc->resindex_lpe_base); 431458bc729SLiam Girdwood if (mmio) { 432458bc729SLiam Girdwood base = mmio->start; 433458bc729SLiam Girdwood size = resource_size(mmio); 434458bc729SLiam Girdwood } else { 435458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 436458bc729SLiam Girdwood desc->resindex_lpe_base); 437458bc729SLiam Girdwood return -EINVAL; 438458bc729SLiam Girdwood } 439458bc729SLiam Girdwood 440458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 441458bc729SLiam Girdwood sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 442458bc729SLiam Girdwood if (!sdev->bar[BDW_DSP_BAR]) { 443458bc729SLiam Girdwood dev_err(sdev->dev, 444458bc729SLiam Girdwood "error: failed to ioremap LPE base 0x%x size 0x%x\n", 445458bc729SLiam Girdwood base, size); 446458bc729SLiam Girdwood return -ENODEV; 447458bc729SLiam Girdwood } 448458bc729SLiam Girdwood dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]); 449458bc729SLiam Girdwood 450458bc729SLiam Girdwood /* TODO: add offsets */ 451458bc729SLiam Girdwood sdev->mmio_bar = BDW_DSP_BAR; 452458bc729SLiam Girdwood sdev->mailbox_bar = BDW_DSP_BAR; 453ff2be865SLiam Girdwood sdev->dsp_oops_offset = MBOX_OFFSET; 454458bc729SLiam Girdwood 455458bc729SLiam Girdwood /* PCI base */ 456458bc729SLiam Girdwood mmio = platform_get_resource(pdev, IORESOURCE_MEM, 457458bc729SLiam Girdwood desc->resindex_pcicfg_base); 458458bc729SLiam Girdwood if (mmio) { 459458bc729SLiam Girdwood base = mmio->start; 460458bc729SLiam Girdwood size = resource_size(mmio); 461458bc729SLiam Girdwood } else { 462458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n", 463458bc729SLiam Girdwood desc->resindex_pcicfg_base); 464458bc729SLiam Girdwood return -ENODEV; 465458bc729SLiam Girdwood } 466458bc729SLiam Girdwood 467458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size); 468458bc729SLiam Girdwood sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size); 469458bc729SLiam Girdwood if (!sdev->bar[BDW_PCI_BAR]) { 470458bc729SLiam Girdwood dev_err(sdev->dev, 471458bc729SLiam Girdwood "error: failed to ioremap PCI base 0x%x size 0x%x\n", 472458bc729SLiam Girdwood base, size); 473458bc729SLiam Girdwood return -ENODEV; 474458bc729SLiam Girdwood } 475458bc729SLiam Girdwood dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]); 476458bc729SLiam Girdwood 477458bc729SLiam Girdwood /* register our IRQ */ 478458bc729SLiam Girdwood sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 479cf9441adSStephen Boyd if (sdev->ipc_irq < 0) 480458bc729SLiam Girdwood return sdev->ipc_irq; 481458bc729SLiam Girdwood 482458bc729SLiam Girdwood dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 483458bc729SLiam Girdwood ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 484458bc729SLiam Girdwood bdw_irq_handler, bdw_irq_thread, 485458bc729SLiam Girdwood IRQF_SHARED, "AudioDSP", sdev); 486458bc729SLiam Girdwood if (ret < 0) { 487458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to register IRQ %d\n", 488458bc729SLiam Girdwood sdev->ipc_irq); 489458bc729SLiam Girdwood return ret; 490458bc729SLiam Girdwood } 491458bc729SLiam Girdwood 492458bc729SLiam Girdwood /* enable the DSP SHIM */ 493458bc729SLiam Girdwood ret = bdw_set_dsp_D0(sdev); 494458bc729SLiam Girdwood if (ret < 0) { 495458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DSP D0\n"); 496458bc729SLiam Girdwood return ret; 497458bc729SLiam Girdwood } 498458bc729SLiam Girdwood 499458bc729SLiam Girdwood /* DSP DMA can only access low 31 bits of host memory */ 500458bc729SLiam Girdwood ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 501458bc729SLiam Girdwood if (ret < 0) { 502458bc729SLiam Girdwood dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 503458bc729SLiam Girdwood return ret; 504458bc729SLiam Girdwood } 505458bc729SLiam Girdwood 5066375dbdbSPeter Ujfalusi /* set default mailbox offset for FW ready message */ 5076375dbdbSPeter Ujfalusi sdev->dsp_box.offset = MBOX_OFFSET; 508458bc729SLiam Girdwood 509458bc729SLiam Girdwood return ret; 510458bc729SLiam Girdwood } 511458bc729SLiam Girdwood 512cb515f10SGuennadi Liakhovetski static struct snd_soc_acpi_mach *bdw_machine_select(struct snd_sof_dev *sdev) 513285880a2SDaniel Baluta { 514285880a2SDaniel Baluta struct snd_sof_pdata *sof_pdata = sdev->pdata; 515285880a2SDaniel Baluta const struct sof_dev_desc *desc = sof_pdata->desc; 516285880a2SDaniel Baluta struct snd_soc_acpi_mach *mach; 517285880a2SDaniel Baluta 518285880a2SDaniel Baluta mach = snd_soc_acpi_find_machine(desc->machines); 519285880a2SDaniel Baluta if (!mach) { 520285880a2SDaniel Baluta dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 521cb515f10SGuennadi Liakhovetski return NULL; 522285880a2SDaniel Baluta } 523285880a2SDaniel Baluta 524285880a2SDaniel Baluta sof_pdata->tplg_filename = mach->sof_tplg_filename; 525285880a2SDaniel Baluta mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 526cb515f10SGuennadi Liakhovetski 527cb515f10SGuennadi Liakhovetski return mach; 528285880a2SDaniel Baluta } 529285880a2SDaniel Baluta 530cb515f10SGuennadi Liakhovetski static void bdw_set_mach_params(struct snd_soc_acpi_mach *mach, 53117e9d6b0SPierre-Louis Bossart struct snd_sof_dev *sdev) 532285880a2SDaniel Baluta { 533974cccf4SPierre-Louis Bossart struct snd_sof_pdata *pdata = sdev->pdata; 534974cccf4SPierre-Louis Bossart const struct sof_dev_desc *desc = pdata->desc; 535285880a2SDaniel Baluta struct snd_soc_acpi_mach_params *mach_params; 536285880a2SDaniel Baluta 537cb515f10SGuennadi Liakhovetski mach_params = &mach->mach_params; 53817e9d6b0SPierre-Louis Bossart mach_params->platform = dev_name(sdev->dev); 539974cccf4SPierre-Louis Bossart mach_params->num_dai_drivers = desc->ops->num_drv; 540974cccf4SPierre-Louis Bossart mach_params->dai_drivers = desc->ops->drv; 541285880a2SDaniel Baluta } 542285880a2SDaniel Baluta 543458bc729SLiam Girdwood /* Broadwell DAIs */ 544458bc729SLiam Girdwood static struct snd_soc_dai_driver bdw_dai[] = { 545458bc729SLiam Girdwood { 546458bc729SLiam Girdwood .name = "ssp0-port", 5478c05246cSPierre-Louis Bossart .playback = { 5488c05246cSPierre-Louis Bossart .channels_min = 1, 5498c05246cSPierre-Louis Bossart .channels_max = 8, 5508c05246cSPierre-Louis Bossart }, 5518c05246cSPierre-Louis Bossart .capture = { 5528c05246cSPierre-Louis Bossart .channels_min = 1, 5538c05246cSPierre-Louis Bossart .channels_max = 8, 5548c05246cSPierre-Louis Bossart }, 555458bc729SLiam Girdwood }, 556458bc729SLiam Girdwood { 557458bc729SLiam Girdwood .name = "ssp1-port", 5588c05246cSPierre-Louis Bossart .playback = { 5598c05246cSPierre-Louis Bossart .channels_min = 1, 5608c05246cSPierre-Louis Bossart .channels_max = 8, 5618c05246cSPierre-Louis Bossart }, 5628c05246cSPierre-Louis Bossart .capture = { 5638c05246cSPierre-Louis Bossart .channels_min = 1, 5648c05246cSPierre-Louis Bossart .channels_max = 8, 5658c05246cSPierre-Louis Bossart }, 566458bc729SLiam Girdwood }, 567458bc729SLiam Girdwood }; 568458bc729SLiam Girdwood 569458bc729SLiam Girdwood /* broadwell ops */ 5708a49cd11SArnd Bergmann static const struct snd_sof_dsp_ops sof_bdw_ops = { 571458bc729SLiam Girdwood /*Device init */ 572458bc729SLiam Girdwood .probe = bdw_probe, 573458bc729SLiam Girdwood 574458bc729SLiam Girdwood /* DSP Core Control */ 575458bc729SLiam Girdwood .run = bdw_run, 576458bc729SLiam Girdwood .reset = bdw_reset, 577458bc729SLiam Girdwood 578458bc729SLiam Girdwood /* Register IO */ 579458bc729SLiam Girdwood .write = sof_io_write, 580458bc729SLiam Girdwood .read = sof_io_read, 581458bc729SLiam Girdwood .write64 = sof_io_write64, 582458bc729SLiam Girdwood .read64 = sof_io_read64, 583458bc729SLiam Girdwood 584458bc729SLiam Girdwood /* Block IO */ 585458bc729SLiam Girdwood .block_read = sof_block_read, 586458bc729SLiam Girdwood .block_write = sof_block_write, 587458bc729SLiam Girdwood 588f71f59ddSDaniel Baluta /* Mailbox IO */ 589f71f59ddSDaniel Baluta .mailbox_read = sof_mailbox_read, 590f71f59ddSDaniel Baluta .mailbox_write = sof_mailbox_write, 591f71f59ddSDaniel Baluta 592458bc729SLiam Girdwood /* ipc */ 593458bc729SLiam Girdwood .send_msg = bdw_send_msg, 594ddf14b64SDaniel Baluta .fw_ready = sof_fw_ready, 595ddf14b64SDaniel Baluta .get_mailbox_offset = bdw_get_mailbox_offset, 596ddf14b64SDaniel Baluta .get_window_offset = bdw_get_window_offset, 597458bc729SLiam Girdwood 59897e22cbdSBud Liviu-Alexandru .ipc_msg_data = sof_ipc_msg_data, 599cf73363eSPeter Ujfalusi .set_stream_data_offset = sof_set_stream_data_offset, 600458bc729SLiam Girdwood 601285880a2SDaniel Baluta /* machine driver */ 602285880a2SDaniel Baluta .machine_select = bdw_machine_select, 603285880a2SDaniel Baluta .machine_register = sof_machine_register, 604285880a2SDaniel Baluta .machine_unregister = sof_machine_unregister, 605285880a2SDaniel Baluta .set_mach_params = bdw_set_mach_params, 606285880a2SDaniel Baluta 607458bc729SLiam Girdwood /* debug */ 608458bc729SLiam Girdwood .debug_map = bdw_debugfs, 609458bc729SLiam Girdwood .debug_map_count = ARRAY_SIZE(bdw_debugfs), 610458bc729SLiam Girdwood .dbg_dump = bdw_dump, 611fe509b34SPeter Ujfalusi .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 612458bc729SLiam Girdwood 613458bc729SLiam Girdwood /* stream callbacks */ 61497e22cbdSBud Liviu-Alexandru .pcm_open = sof_stream_pcm_open, 61597e22cbdSBud Liviu-Alexandru .pcm_close = sof_stream_pcm_close, 616458bc729SLiam Girdwood 617458bc729SLiam Girdwood /* Module loading */ 618458bc729SLiam Girdwood .load_module = snd_sof_parse_module_memcpy, 619458bc729SLiam Girdwood 620458bc729SLiam Girdwood /*Firmware loading */ 621458bc729SLiam Girdwood .load_firmware = snd_sof_load_firmware_memcpy, 622458bc729SLiam Girdwood 623458bc729SLiam Girdwood /* DAI drivers */ 624458bc729SLiam Girdwood .drv = bdw_dai, 62527e322faSPierre-Louis Bossart .num_drv = ARRAY_SIZE(bdw_dai), 62627e322faSPierre-Louis Bossart 62727e322faSPierre-Louis Bossart /* ALSA HW info flags */ 62827e322faSPierre-Louis Bossart .hw_info = SNDRV_PCM_INFO_MMAP | 62927e322faSPierre-Louis Bossart SNDRV_PCM_INFO_MMAP_VALID | 63027e322faSPierre-Louis Bossart SNDRV_PCM_INFO_INTERLEAVED | 63127e322faSPierre-Louis Bossart SNDRV_PCM_INFO_PAUSE | 6324c02a7bdSPierre-Louis Bossart SNDRV_PCM_INFO_BATCH, 6330f501c7cSPierre-Louis Bossart 6340ed66cb7SPeter Ujfalusi .dsp_arch_ops = &sof_xtensa_arch_ops, 635458bc729SLiam Girdwood }; 636458bc729SLiam Girdwood 6378a49cd11SArnd Bergmann static const struct sof_intel_dsp_desc bdw_chip_info = { 638458bc729SLiam Girdwood .cores_num = 1, 63964b96917SRanjani Sridharan .host_managed_cores_mask = 1, 640458bc729SLiam Girdwood }; 6418a49cd11SArnd Bergmann 6428a49cd11SArnd Bergmann static const struct sof_dev_desc sof_acpi_broadwell_desc = { 6438a49cd11SArnd Bergmann .machines = snd_soc_acpi_intel_broadwell_machines, 6448a49cd11SArnd Bergmann .resindex_lpe_base = 0, 6458a49cd11SArnd Bergmann .resindex_pcicfg_base = 1, 6468a49cd11SArnd Bergmann .resindex_imr_base = -1, 6478a49cd11SArnd Bergmann .irqindex_host_ipc = 0, 6488a49cd11SArnd Bergmann .chip_info = &bdw_chip_info, 649*a3757915SPierre-Louis Bossart .default_fw_path = { 650*a3757915SPierre-Louis Bossart [SOF_IPC] = "intel/sof", 651*a3757915SPierre-Louis Bossart }, 652*a3757915SPierre-Louis Bossart .default_tplg_path = { 653*a3757915SPierre-Louis Bossart [SOF_IPC] = "intel/sof-tplg", 654*a3757915SPierre-Louis Bossart }, 6558a49cd11SArnd Bergmann .default_fw_filename = "sof-bdw.ri", 6568a49cd11SArnd Bergmann .nocodec_tplg_filename = "sof-bdw-nocodec.tplg", 6578a49cd11SArnd Bergmann .ops = &sof_bdw_ops, 6588a49cd11SArnd Bergmann }; 6598a49cd11SArnd Bergmann 6608a49cd11SArnd Bergmann static const struct acpi_device_id sof_broadwell_match[] = { 6618a49cd11SArnd Bergmann { "INT3438", (unsigned long)&sof_acpi_broadwell_desc }, 6628a49cd11SArnd Bergmann { } 6638a49cd11SArnd Bergmann }; 6648a49cd11SArnd Bergmann MODULE_DEVICE_TABLE(acpi, sof_broadwell_match); 6658a49cd11SArnd Bergmann 6668a49cd11SArnd Bergmann static int sof_broadwell_probe(struct platform_device *pdev) 6678a49cd11SArnd Bergmann { 6688a49cd11SArnd Bergmann struct device *dev = &pdev->dev; 6698a49cd11SArnd Bergmann const struct acpi_device_id *id; 6708a49cd11SArnd Bergmann const struct sof_dev_desc *desc; 6718a49cd11SArnd Bergmann int ret; 6728a49cd11SArnd Bergmann 6738a49cd11SArnd Bergmann id = acpi_match_device(dev->driver->acpi_match_table, dev); 6748a49cd11SArnd Bergmann if (!id) 6758a49cd11SArnd Bergmann return -ENODEV; 6768a49cd11SArnd Bergmann 6778a49cd11SArnd Bergmann ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 6788a49cd11SArnd Bergmann if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 6798a49cd11SArnd Bergmann dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 6808a49cd11SArnd Bergmann return -ENODEV; 6818a49cd11SArnd Bergmann } 6828a49cd11SArnd Bergmann 6838a49cd11SArnd Bergmann desc = device_get_match_data(dev); 6848a49cd11SArnd Bergmann if (!desc) 6858a49cd11SArnd Bergmann return -ENODEV; 6868a49cd11SArnd Bergmann 6878a49cd11SArnd Bergmann return sof_acpi_probe(pdev, device_get_match_data(dev)); 6888a49cd11SArnd Bergmann } 6898a49cd11SArnd Bergmann 6908a49cd11SArnd Bergmann /* acpi_driver definition */ 6918a49cd11SArnd Bergmann static struct platform_driver snd_sof_acpi_intel_bdw_driver = { 6928a49cd11SArnd Bergmann .probe = sof_broadwell_probe, 6938a49cd11SArnd Bergmann .remove = sof_acpi_remove, 6948a49cd11SArnd Bergmann .driver = { 6958a49cd11SArnd Bergmann .name = "sof-audio-acpi-intel-bdw", 6968a49cd11SArnd Bergmann .pm = &sof_acpi_pm, 6978a49cd11SArnd Bergmann .acpi_match_table = sof_broadwell_match, 6988a49cd11SArnd Bergmann }, 6998a49cd11SArnd Bergmann }; 7008a49cd11SArnd Bergmann module_platform_driver(snd_sof_acpi_intel_bdw_driver); 701458bc729SLiam Girdwood 702458bc729SLiam Girdwood MODULE_LICENSE("Dual BSD/GPL"); 703f4483a0fSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 704068ac0dbSPierre-Louis Bossart MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 7058a49cd11SArnd Bergmann MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 706