1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for audio DSP on Apollolake and GeminiLake 16 */ 17 18 #include "../sof-priv.h" 19 #include "hda.h" 20 #include "../sof-audio.h" 21 22 static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = { 23 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26 }; 27 28 /* apollolake ops */ 29 struct snd_sof_dsp_ops sof_apl_ops; 30 EXPORT_SYMBOL_NS(sof_apl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 31 32 int sof_apl_ops_init(struct snd_sof_dev *sdev) 33 { 34 /* common defaults */ 35 memcpy(&sof_apl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 36 37 /* probe/remove/shutdown */ 38 sof_apl_ops.shutdown = hda_dsp_shutdown; 39 40 /* doorbell */ 41 sof_apl_ops.irq_thread = hda_dsp_ipc_irq_thread; 42 43 /* ipc */ 44 sof_apl_ops.send_msg = hda_dsp_ipc_send_msg; 45 46 /* debug */ 47 sof_apl_ops.debug_map = apl_dsp_debugfs; 48 sof_apl_ops.debug_map_count = ARRAY_SIZE(apl_dsp_debugfs); 49 sof_apl_ops.ipc_dump = hda_ipc_dump; 50 51 /* firmware run */ 52 sof_apl_ops.run = hda_dsp_cl_boot_firmware; 53 54 /* pre/post fw run */ 55 sof_apl_ops.post_fw_run = hda_dsp_post_fw_run; 56 57 /* dsp core get/put */ 58 sof_apl_ops.core_get = hda_dsp_core_get; 59 60 return 0; 61 }; 62 EXPORT_SYMBOL_NS(sof_apl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 63 64 const struct sof_intel_dsp_desc apl_chip_info = { 65 /* Apollolake */ 66 .cores_num = 2, 67 .init_core_mask = 1, 68 .host_managed_cores_mask = GENMASK(1, 0), 69 .ipc_req = HDA_DSP_REG_HIPCI, 70 .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, 71 .ipc_ack = HDA_DSP_REG_HIPCIE, 72 .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE, 73 .ipc_ctl = HDA_DSP_REG_HIPCCTL, 74 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 75 .rom_init_timeout = 150, 76 .ssp_count = APL_SSP_COUNT, 77 .ssp_base_offset = APL_SSP_BASE_OFFSET, 78 .quirks = SOF_INTEL_PROCEN_FMT_QUIRK, 79 .check_ipc_irq = hda_dsp_check_ipc_irq, 80 .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS, 81 }; 82 EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 83