1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright 2020 NXP 4 // 5 // Author: Daniel Baluta <daniel.baluta@nxp.com> 6 // 7 // Hardware interface for audio DSP on i.MX8M 8 9 #include <linux/bits.h> 10 #include <linux/firmware.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 17 #include <linux/module.h> 18 #include <sound/sof.h> 19 #include <sound/sof/xtensa.h> 20 #include <linux/firmware/imx/dsp.h> 21 22 #include "../ops.h" 23 #include "../sof-of-dev.h" 24 #include "imx-common.h" 25 26 #define MBOX_OFFSET 0x800000 27 #define MBOX_SIZE 0x1000 28 29 static struct clk_bulk_data imx8m_dsp_clks[] = { 30 { .id = "ipg" }, 31 { .id = "ocram" }, 32 { .id = "core" }, 33 }; 34 35 /* DAP registers */ 36 #define IMX8M_DAP_DEBUG 0x28800000 37 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 38 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 39 #define IMX8M_PWRCTL_CORERESET BIT(16) 40 41 /* DSP audio mix registers */ 42 #define AudioDSP_REG0 0x100 43 #define AudioDSP_REG1 0x104 44 #define AudioDSP_REG2 0x108 45 #define AudioDSP_REG3 0x10c 46 47 #define AudioDSP_REG2_RUNSTALL BIT(5) 48 49 struct imx8m_priv { 50 struct device *dev; 51 struct snd_sof_dev *sdev; 52 53 /* DSP IPC handler */ 54 struct imx_dsp_ipc *dsp_ipc; 55 struct platform_device *ipc_dev; 56 57 struct imx_clocks *clks; 58 59 void __iomem *dap; 60 struct regmap *regmap; 61 }; 62 63 static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev) 64 { 65 return MBOX_OFFSET; 66 } 67 68 static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id) 69 { 70 return MBOX_OFFSET; 71 } 72 73 static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc) 74 { 75 struct imx8m_priv *priv = imx_dsp_get_data(ipc); 76 unsigned long flags; 77 78 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 79 snd_sof_ipc_process_reply(priv->sdev, 0); 80 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 81 } 82 83 static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc) 84 { 85 struct imx8m_priv *priv = imx_dsp_get_data(ipc); 86 u32 p; /* Panic code */ 87 88 /* Read the message from the debug box. */ 89 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p)); 90 91 /* Check to see if the message is a panic code (0x0dead***) */ 92 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) 93 snd_sof_dsp_panic(priv->sdev, p, true); 94 else 95 snd_sof_ipc_msgs_rx(priv->sdev); 96 } 97 98 static struct imx_dsp_ops imx8m_dsp_ops = { 99 .handle_reply = imx8m_dsp_handle_reply, 100 .handle_request = imx8m_dsp_handle_request, 101 }; 102 103 static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 104 { 105 struct imx8m_priv *priv = sdev->pdata->hw_pdata; 106 107 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 108 msg->msg_size); 109 imx_dsp_ring_doorbell(priv->dsp_ipc, 0); 110 111 return 0; 112 } 113 114 /* 115 * DSP control. 116 */ 117 static int imx8m_run(struct snd_sof_dev *sdev) 118 { 119 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 120 121 regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0); 122 123 return 0; 124 } 125 126 static int imx8m_reset(struct snd_sof_dev *sdev) 127 { 128 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 129 u32 pwrctl; 130 131 /* put DSP into reset and stall */ 132 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); 133 pwrctl |= IMX8M_PWRCTL_CORERESET; 134 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); 135 136 /* keep reset asserted for 10 cycles */ 137 usleep_range(1, 2); 138 139 regmap_update_bits(priv->regmap, AudioDSP_REG2, 140 AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL); 141 142 /* take the DSP out of reset and keep stalled for FW loading */ 143 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); 144 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 145 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); 146 147 return 0; 148 } 149 150 static int imx8m_probe(struct snd_sof_dev *sdev) 151 { 152 struct platform_device *pdev = 153 container_of(sdev->dev, struct platform_device, dev); 154 struct device_node *np = pdev->dev.of_node; 155 struct device_node *res_node; 156 struct resource *mmio; 157 struct imx8m_priv *priv; 158 struct resource res; 159 u32 base, size; 160 int ret = 0; 161 162 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 163 if (!priv) 164 return -ENOMEM; 165 166 priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL); 167 if (!priv->clks) 168 return -ENOMEM; 169 170 sdev->num_cores = 1; 171 sdev->pdata->hw_pdata = priv; 172 priv->dev = sdev->dev; 173 priv->sdev = sdev; 174 175 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", 176 PLATFORM_DEVID_NONE, 177 pdev, sizeof(*pdev)); 178 if (IS_ERR(priv->ipc_dev)) 179 return PTR_ERR(priv->ipc_dev); 180 181 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 182 if (!priv->dsp_ipc) { 183 /* DSP IPC driver not probed yet, try later */ 184 ret = -EPROBE_DEFER; 185 dev_err(sdev->dev, "Failed to get drvdata\n"); 186 goto exit_pdev_unregister; 187 } 188 189 imx_dsp_set_data(priv->dsp_ipc, priv); 190 priv->dsp_ipc->ops = &imx8m_dsp_ops; 191 192 /* DSP base */ 193 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 194 if (mmio) { 195 base = mmio->start; 196 size = resource_size(mmio); 197 } else { 198 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n"); 199 ret = -EINVAL; 200 goto exit_pdev_unregister; 201 } 202 203 priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 204 if (!priv->dap) { 205 dev_err(sdev->dev, "error: failed to map DAP debug memory area"); 206 ret = -ENODEV; 207 goto exit_pdev_unregister; 208 } 209 210 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); 211 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 212 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n", 213 base, size); 214 ret = -ENODEV; 215 goto exit_pdev_unregister; 216 } 217 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM; 218 219 res_node = of_parse_phandle(np, "memory-region", 0); 220 if (!res_node) { 221 dev_err(&pdev->dev, "failed to get memory region node\n"); 222 ret = -ENODEV; 223 goto exit_pdev_unregister; 224 } 225 226 ret = of_address_to_resource(res_node, 0, &res); 227 of_node_put(res_node); 228 if (ret) { 229 dev_err(&pdev->dev, "failed to get reserved region address\n"); 230 goto exit_pdev_unregister; 231 } 232 233 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start, 234 resource_size(&res)); 235 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 236 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n", 237 base, size); 238 ret = -ENOMEM; 239 goto exit_pdev_unregister; 240 } 241 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 242 243 /* set default mailbox offset for FW ready message */ 244 sdev->dsp_box.offset = MBOX_OFFSET; 245 246 priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl"); 247 if (IS_ERR(priv->regmap)) { 248 dev_err(sdev->dev, "cannot find dsp-ctrl registers"); 249 ret = PTR_ERR(priv->regmap); 250 goto exit_pdev_unregister; 251 } 252 253 /* init clocks info */ 254 priv->clks->dsp_clks = imx8m_dsp_clks; 255 priv->clks->num_dsp_clks = ARRAY_SIZE(imx8m_dsp_clks); 256 257 ret = imx8_parse_clocks(sdev, priv->clks); 258 if (ret < 0) 259 goto exit_pdev_unregister; 260 261 ret = imx8_enable_clocks(sdev, priv->clks); 262 if (ret < 0) 263 goto exit_pdev_unregister; 264 265 return 0; 266 267 exit_pdev_unregister: 268 platform_device_unregister(priv->ipc_dev); 269 return ret; 270 } 271 272 static int imx8m_remove(struct snd_sof_dev *sdev) 273 { 274 struct imx8m_priv *priv = sdev->pdata->hw_pdata; 275 276 imx8_disable_clocks(sdev, priv->clks); 277 platform_device_unregister(priv->ipc_dev); 278 279 return 0; 280 } 281 282 /* on i.MX8 there is 1 to 1 match between type and BAR idx */ 283 static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type) 284 { 285 /* Only IRAM and SRAM bars are valid */ 286 switch (type) { 287 case SOF_FW_BLK_TYPE_IRAM: 288 case SOF_FW_BLK_TYPE_SRAM: 289 return type; 290 default: 291 return -EINVAL; 292 } 293 } 294 295 static struct snd_soc_dai_driver imx8m_dai[] = { 296 { 297 .name = "sai1", 298 .playback = { 299 .channels_min = 1, 300 .channels_max = 32, 301 }, 302 .capture = { 303 .channels_min = 1, 304 .channels_max = 32, 305 }, 306 }, 307 { 308 .name = "sai3", 309 .playback = { 310 .channels_min = 1, 311 .channels_max = 32, 312 }, 313 .capture = { 314 .channels_min = 1, 315 .channels_max = 32, 316 }, 317 }, 318 }; 319 320 static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev, 321 const struct sof_dsp_power_state *target_state) 322 { 323 sdev->dsp_power_state = *target_state; 324 325 return 0; 326 } 327 328 static int imx8m_resume(struct snd_sof_dev *sdev) 329 { 330 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 331 int ret; 332 int i; 333 334 ret = imx8_enable_clocks(sdev, priv->clks); 335 if (ret < 0) 336 return ret; 337 338 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 339 imx_dsp_request_channel(priv->dsp_ipc, i); 340 341 return 0; 342 } 343 344 static void imx8m_suspend(struct snd_sof_dev *sdev) 345 { 346 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 347 int i; 348 349 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 350 imx_dsp_free_channel(priv->dsp_ipc, i); 351 352 imx8_disable_clocks(sdev, priv->clks); 353 } 354 355 static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev) 356 { 357 int ret; 358 const struct sof_dsp_power_state target_dsp_state = { 359 .state = SOF_DSP_PM_D0, 360 }; 361 362 ret = imx8m_resume(sdev); 363 if (ret < 0) 364 return ret; 365 366 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 367 } 368 369 static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev) 370 { 371 const struct sof_dsp_power_state target_dsp_state = { 372 .state = SOF_DSP_PM_D3, 373 }; 374 375 imx8m_suspend(sdev); 376 377 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 378 } 379 380 static int imx8m_dsp_resume(struct snd_sof_dev *sdev) 381 { 382 int ret; 383 const struct sof_dsp_power_state target_dsp_state = { 384 .state = SOF_DSP_PM_D0, 385 }; 386 387 ret = imx8m_resume(sdev); 388 if (ret < 0) 389 return ret; 390 391 if (pm_runtime_suspended(sdev->dev)) { 392 pm_runtime_disable(sdev->dev); 393 pm_runtime_set_active(sdev->dev); 394 pm_runtime_mark_last_busy(sdev->dev); 395 pm_runtime_enable(sdev->dev); 396 pm_runtime_idle(sdev->dev); 397 } 398 399 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 400 } 401 402 static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state) 403 { 404 const struct sof_dsp_power_state target_dsp_state = { 405 .state = target_state, 406 }; 407 408 if (!pm_runtime_suspended(sdev->dev)) 409 imx8m_suspend(sdev); 410 411 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 412 } 413 414 /* i.MX8 ops */ 415 static struct snd_sof_dsp_ops sof_imx8m_ops = { 416 /* probe and remove */ 417 .probe = imx8m_probe, 418 .remove = imx8m_remove, 419 /* DSP core boot */ 420 .run = imx8m_run, 421 .reset = imx8m_reset, 422 423 /* Block IO */ 424 .block_read = sof_block_read, 425 .block_write = sof_block_write, 426 427 /* Mailbox IO */ 428 .mailbox_read = sof_mailbox_read, 429 .mailbox_write = sof_mailbox_write, 430 431 /* ipc */ 432 .send_msg = imx8m_send_msg, 433 .get_mailbox_offset = imx8m_get_mailbox_offset, 434 .get_window_offset = imx8m_get_window_offset, 435 436 .ipc_msg_data = sof_ipc_msg_data, 437 .set_stream_data_offset = sof_set_stream_data_offset, 438 439 .get_bar_index = imx8m_get_bar_index, 440 441 /* firmware loading */ 442 .load_firmware = snd_sof_load_firmware_memcpy, 443 444 /* Debug information */ 445 .dbg_dump = imx8_dump, 446 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 447 448 /* stream callbacks */ 449 .pcm_open = sof_stream_pcm_open, 450 .pcm_close = sof_stream_pcm_close, 451 /* Firmware ops */ 452 .dsp_arch_ops = &sof_xtensa_arch_ops, 453 454 /* DAI drivers */ 455 .drv = imx8m_dai, 456 .num_drv = ARRAY_SIZE(imx8m_dai), 457 458 .suspend = imx8m_dsp_suspend, 459 .resume = imx8m_dsp_resume, 460 461 .runtime_suspend = imx8m_dsp_runtime_suspend, 462 .runtime_resume = imx8m_dsp_runtime_resume, 463 464 .set_power_state = imx8m_dsp_set_power_state, 465 466 .hw_info = SNDRV_PCM_INFO_MMAP | 467 SNDRV_PCM_INFO_MMAP_VALID | 468 SNDRV_PCM_INFO_INTERLEAVED | 469 SNDRV_PCM_INFO_PAUSE | 470 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 471 }; 472 473 static struct sof_dev_desc sof_of_imx8mp_desc = { 474 .ipc_supported_mask = BIT(SOF_IPC), 475 .ipc_default = SOF_IPC, 476 .default_fw_path = { 477 [SOF_IPC] = "imx/sof", 478 }, 479 .default_tplg_path = { 480 [SOF_IPC] = "imx/sof-tplg", 481 }, 482 .default_fw_filename = { 483 [SOF_IPC] = "sof-imx8m.ri", 484 }, 485 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg", 486 .ops = &sof_imx8m_ops, 487 }; 488 489 static const struct of_device_id sof_of_imx8m_ids[] = { 490 { .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc}, 491 { } 492 }; 493 MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids); 494 495 /* DT driver definition */ 496 static struct platform_driver snd_sof_of_imx8m_driver = { 497 .probe = sof_of_probe, 498 .remove = sof_of_remove, 499 .driver = { 500 .name = "sof-audio-of-imx8m", 501 .pm = &sof_of_pm, 502 .of_match_table = sof_of_imx8m_ids, 503 }, 504 }; 505 module_platform_driver(snd_sof_of_imx8m_driver); 506 507 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 508 MODULE_LICENSE("Dual BSD/GPL"); 509