1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright 2020 NXP 4 // 5 // Author: Daniel Baluta <daniel.baluta@nxp.com> 6 // 7 // Hardware interface for audio DSP on i.MX8M 8 9 #include <linux/bits.h> 10 #include <linux/firmware.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 17 #include <linux/module.h> 18 #include <sound/sof.h> 19 #include <sound/sof/xtensa.h> 20 #include <linux/firmware/imx/dsp.h> 21 22 #include "../ops.h" 23 #include "../sof-of-dev.h" 24 #include "imx-common.h" 25 26 #define MBOX_OFFSET 0x800000 27 #define MBOX_SIZE 0x1000 28 29 static struct clk_bulk_data imx8m_dsp_clks[] = { 30 { .id = "ipg" }, 31 { .id = "ocram" }, 32 { .id = "core" }, 33 }; 34 35 /* DAP registers */ 36 #define IMX8M_DAP_DEBUG 0x28800000 37 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 38 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 39 #define IMX8M_PWRCTL_CORERESET BIT(16) 40 41 /* DSP audio mix registers */ 42 #define AudioDSP_REG0 0x100 43 #define AudioDSP_REG1 0x104 44 #define AudioDSP_REG2 0x108 45 #define AudioDSP_REG3 0x10c 46 47 #define AudioDSP_REG2_RUNSTALL BIT(5) 48 49 struct imx8m_priv { 50 struct device *dev; 51 struct snd_sof_dev *sdev; 52 53 /* DSP IPC handler */ 54 struct imx_dsp_ipc *dsp_ipc; 55 struct platform_device *ipc_dev; 56 57 struct imx_clocks *clks; 58 59 void __iomem *dap; 60 struct regmap *regmap; 61 }; 62 63 static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev) 64 { 65 return MBOX_OFFSET; 66 } 67 68 static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id) 69 { 70 return MBOX_OFFSET; 71 } 72 73 static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc) 74 { 75 struct imx8m_priv *priv = imx_dsp_get_data(ipc); 76 unsigned long flags; 77 78 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 79 snd_sof_ipc_process_reply(priv->sdev, 0); 80 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 81 } 82 83 static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc) 84 { 85 struct imx8m_priv *priv = imx_dsp_get_data(ipc); 86 u32 p; /* Panic code */ 87 88 /* Read the message from the debug box. */ 89 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p)); 90 91 /* Check to see if the message is a panic code (0x0dead***) */ 92 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) 93 snd_sof_dsp_panic(priv->sdev, p, true); 94 else 95 snd_sof_ipc_msgs_rx(priv->sdev); 96 } 97 98 static struct imx_dsp_ops imx8m_dsp_ops = { 99 .handle_reply = imx8m_dsp_handle_reply, 100 .handle_request = imx8m_dsp_handle_request, 101 }; 102 103 static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 104 { 105 struct imx8m_priv *priv = sdev->pdata->hw_pdata; 106 107 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 108 msg->msg_size); 109 imx_dsp_ring_doorbell(priv->dsp_ipc, 0); 110 111 return 0; 112 } 113 114 /* 115 * DSP control. 116 */ 117 static int imx8m_run(struct snd_sof_dev *sdev) 118 { 119 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 120 121 regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0); 122 123 return 0; 124 } 125 126 static int imx8m_reset(struct snd_sof_dev *sdev) 127 { 128 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 129 u32 pwrctl; 130 131 /* put DSP into reset and stall */ 132 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); 133 pwrctl |= IMX8M_PWRCTL_CORERESET; 134 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); 135 136 /* keep reset asserted for 10 cycles */ 137 usleep_range(1, 2); 138 139 regmap_update_bits(priv->regmap, AudioDSP_REG2, 140 AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL); 141 142 /* take the DSP out of reset and keep stalled for FW loading */ 143 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); 144 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 145 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); 146 147 return 0; 148 } 149 150 static int imx8m_probe(struct snd_sof_dev *sdev) 151 { 152 struct platform_device *pdev = 153 container_of(sdev->dev, struct platform_device, dev); 154 struct device_node *np = pdev->dev.of_node; 155 struct device_node *res_node; 156 struct resource *mmio; 157 struct imx8m_priv *priv; 158 struct resource res; 159 u32 base, size; 160 int ret = 0; 161 162 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 163 if (!priv) 164 return -ENOMEM; 165 166 priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL); 167 if (!priv->clks) 168 return -ENOMEM; 169 170 sdev->num_cores = 1; 171 sdev->pdata->hw_pdata = priv; 172 priv->dev = sdev->dev; 173 priv->sdev = sdev; 174 175 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", 176 PLATFORM_DEVID_NONE, 177 pdev, sizeof(*pdev)); 178 if (IS_ERR(priv->ipc_dev)) 179 return PTR_ERR(priv->ipc_dev); 180 181 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 182 if (!priv->dsp_ipc) { 183 /* DSP IPC driver not probed yet, try later */ 184 ret = -EPROBE_DEFER; 185 dev_err(sdev->dev, "Failed to get drvdata\n"); 186 goto exit_pdev_unregister; 187 } 188 189 imx_dsp_set_data(priv->dsp_ipc, priv); 190 priv->dsp_ipc->ops = &imx8m_dsp_ops; 191 192 /* DSP base */ 193 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 194 if (mmio) { 195 base = mmio->start; 196 size = resource_size(mmio); 197 } else { 198 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n"); 199 ret = -EINVAL; 200 goto exit_pdev_unregister; 201 } 202 203 priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 204 if (!priv->dap) { 205 dev_err(sdev->dev, "error: failed to map DAP debug memory area"); 206 ret = -ENODEV; 207 goto exit_pdev_unregister; 208 } 209 210 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); 211 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 212 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n", 213 base, size); 214 ret = -ENODEV; 215 goto exit_pdev_unregister; 216 } 217 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM; 218 219 res_node = of_parse_phandle(np, "memory-region", 0); 220 if (!res_node) { 221 dev_err(&pdev->dev, "failed to get memory region node\n"); 222 ret = -ENODEV; 223 goto exit_pdev_unregister; 224 } 225 226 ret = of_address_to_resource(res_node, 0, &res); 227 if (ret) { 228 dev_err(&pdev->dev, "failed to get reserved region address\n"); 229 goto exit_pdev_unregister; 230 } 231 232 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start, 233 resource_size(&res)); 234 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 235 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n", 236 base, size); 237 ret = -ENOMEM; 238 goto exit_pdev_unregister; 239 } 240 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 241 242 /* set default mailbox offset for FW ready message */ 243 sdev->dsp_box.offset = MBOX_OFFSET; 244 245 priv->regmap = syscon_regmap_lookup_by_compatible("fsl,dsp-ctrl"); 246 if (IS_ERR(priv->regmap)) { 247 dev_err(sdev->dev, "cannot find dsp-ctrl registers"); 248 ret = PTR_ERR(priv->regmap); 249 goto exit_pdev_unregister; 250 } 251 252 /* init clocks info */ 253 priv->clks->dsp_clks = imx8m_dsp_clks; 254 priv->clks->num_dsp_clks = ARRAY_SIZE(imx8m_dsp_clks); 255 256 ret = imx8_parse_clocks(sdev, priv->clks); 257 if (ret < 0) 258 goto exit_pdev_unregister; 259 260 ret = imx8_enable_clocks(sdev, priv->clks); 261 if (ret < 0) 262 goto exit_pdev_unregister; 263 264 return 0; 265 266 exit_pdev_unregister: 267 platform_device_unregister(priv->ipc_dev); 268 return ret; 269 } 270 271 static int imx8m_remove(struct snd_sof_dev *sdev) 272 { 273 struct imx8m_priv *priv = sdev->pdata->hw_pdata; 274 275 imx8_disable_clocks(sdev, priv->clks); 276 platform_device_unregister(priv->ipc_dev); 277 278 return 0; 279 } 280 281 /* on i.MX8 there is 1 to 1 match between type and BAR idx */ 282 static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type) 283 { 284 /* Only IRAM and SRAM bars are valid */ 285 switch (type) { 286 case SOF_FW_BLK_TYPE_IRAM: 287 case SOF_FW_BLK_TYPE_SRAM: 288 return type; 289 default: 290 return -EINVAL; 291 } 292 } 293 294 static struct snd_soc_dai_driver imx8m_dai[] = { 295 { 296 .name = "sai1", 297 .playback = { 298 .channels_min = 1, 299 .channels_max = 32, 300 }, 301 .capture = { 302 .channels_min = 1, 303 .channels_max = 32, 304 }, 305 }, 306 { 307 .name = "sai3", 308 .playback = { 309 .channels_min = 1, 310 .channels_max = 32, 311 }, 312 .capture = { 313 .channels_min = 1, 314 .channels_max = 32, 315 }, 316 }, 317 }; 318 319 static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev, 320 const struct sof_dsp_power_state *target_state) 321 { 322 sdev->dsp_power_state = *target_state; 323 324 return 0; 325 } 326 327 static int imx8m_resume(struct snd_sof_dev *sdev) 328 { 329 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 330 int ret; 331 int i; 332 333 ret = imx8_enable_clocks(sdev, priv->clks); 334 if (ret < 0) 335 return ret; 336 337 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 338 imx_dsp_request_channel(priv->dsp_ipc, i); 339 340 return 0; 341 } 342 343 static void imx8m_suspend(struct snd_sof_dev *sdev) 344 { 345 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; 346 int i; 347 348 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 349 imx_dsp_free_channel(priv->dsp_ipc, i); 350 351 imx8_disable_clocks(sdev, priv->clks); 352 } 353 354 static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev) 355 { 356 int ret; 357 const struct sof_dsp_power_state target_dsp_state = { 358 .state = SOF_DSP_PM_D0, 359 }; 360 361 ret = imx8m_resume(sdev); 362 if (ret < 0) 363 return ret; 364 365 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 366 } 367 368 static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev) 369 { 370 const struct sof_dsp_power_state target_dsp_state = { 371 .state = SOF_DSP_PM_D3, 372 }; 373 374 imx8m_suspend(sdev); 375 376 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 377 } 378 379 static int imx8m_dsp_resume(struct snd_sof_dev *sdev) 380 { 381 int ret; 382 const struct sof_dsp_power_state target_dsp_state = { 383 .state = SOF_DSP_PM_D0, 384 }; 385 386 ret = imx8m_resume(sdev); 387 if (ret < 0) 388 return ret; 389 390 if (pm_runtime_suspended(sdev->dev)) { 391 pm_runtime_disable(sdev->dev); 392 pm_runtime_set_active(sdev->dev); 393 pm_runtime_mark_last_busy(sdev->dev); 394 pm_runtime_enable(sdev->dev); 395 pm_runtime_idle(sdev->dev); 396 } 397 398 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 399 } 400 401 static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state) 402 { 403 const struct sof_dsp_power_state target_dsp_state = { 404 .state = target_state, 405 }; 406 407 if (!pm_runtime_suspended(sdev->dev)) 408 imx8m_suspend(sdev); 409 410 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 411 } 412 413 /* i.MX8 ops */ 414 static const struct snd_sof_dsp_ops sof_imx8m_ops = { 415 /* probe and remove */ 416 .probe = imx8m_probe, 417 .remove = imx8m_remove, 418 /* DSP core boot */ 419 .run = imx8m_run, 420 .reset = imx8m_reset, 421 422 /* Block IO */ 423 .block_read = sof_block_read, 424 .block_write = sof_block_write, 425 426 /* Mailbox IO */ 427 .mailbox_read = sof_mailbox_read, 428 .mailbox_write = sof_mailbox_write, 429 430 /* ipc */ 431 .send_msg = imx8m_send_msg, 432 .fw_ready = sof_fw_ready, 433 .get_mailbox_offset = imx8m_get_mailbox_offset, 434 .get_window_offset = imx8m_get_window_offset, 435 436 .ipc_msg_data = sof_ipc_msg_data, 437 .ipc_pcm_params = sof_ipc_pcm_params, 438 439 /* module loading */ 440 .load_module = snd_sof_parse_module_memcpy, 441 .get_bar_index = imx8m_get_bar_index, 442 /* firmware loading */ 443 .load_firmware = snd_sof_load_firmware_memcpy, 444 445 /* Debug information */ 446 .dbg_dump = imx8_dump, 447 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 448 449 /* stream callbacks */ 450 .pcm_open = sof_stream_pcm_open, 451 .pcm_close = sof_stream_pcm_close, 452 /* Firmware ops */ 453 .dsp_arch_ops = &sof_xtensa_arch_ops, 454 455 /* DAI drivers */ 456 .drv = imx8m_dai, 457 .num_drv = ARRAY_SIZE(imx8m_dai), 458 459 .suspend = imx8m_dsp_suspend, 460 .resume = imx8m_dsp_resume, 461 462 .runtime_suspend = imx8m_dsp_runtime_suspend, 463 .runtime_resume = imx8m_dsp_runtime_resume, 464 465 .set_power_state = imx8m_dsp_set_power_state, 466 467 .hw_info = SNDRV_PCM_INFO_MMAP | 468 SNDRV_PCM_INFO_MMAP_VALID | 469 SNDRV_PCM_INFO_INTERLEAVED | 470 SNDRV_PCM_INFO_PAUSE | 471 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 472 }; 473 474 static struct sof_dev_desc sof_of_imx8mp_desc = { 475 .default_fw_path = "imx/sof", 476 .default_tplg_path = "imx/sof-tplg", 477 .default_fw_filename = "sof-imx8m.ri", 478 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg", 479 .ops = &sof_imx8m_ops, 480 }; 481 482 static const struct of_device_id sof_of_imx8m_ids[] = { 483 { .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc}, 484 { } 485 }; 486 MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids); 487 488 /* DT driver definition */ 489 static struct platform_driver snd_sof_of_imx8m_driver = { 490 .probe = sof_of_probe, 491 .remove = sof_of_remove, 492 .driver = { 493 .name = "sof-audio-of-imx8m", 494 .pm = &sof_of_pm, 495 .of_match_table = sof_of_imx8m_ids, 496 }, 497 }; 498 module_platform_driver(snd_sof_of_imx8m_driver); 499 500 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 501 MODULE_LICENSE("Dual BSD/GPL"); 502