1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright 2019 NXP 4 // 5 // Author: Daniel Baluta <daniel.baluta@nxp.com> 6 // 7 // Hardware interface for audio DSP on i.MX8 8 9 #include <linux/firmware.h> 10 #include <linux/of_platform.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_domain.h> 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include <linux/firmware/imx/ipc.h> 19 #include <linux/firmware/imx/dsp.h> 20 21 #include <linux/firmware/imx/svc/misc.h> 22 #include <dt-bindings/firmware/imx/rsrc.h> 23 #include "../ops.h" 24 25 /* DSP memories */ 26 #define IRAM_OFFSET 0x10000 27 #define IRAM_SIZE (2 * 1024) 28 #define DRAM0_OFFSET 0x0 29 #define DRAM0_SIZE (32 * 1024) 30 #define DRAM1_OFFSET 0x8000 31 #define DRAM1_SIZE (32 * 1024) 32 #define SYSRAM_OFFSET 0x18000 33 #define SYSRAM_SIZE (256 * 1024) 34 #define SYSROM_OFFSET 0x58000 35 #define SYSROM_SIZE (192 * 1024) 36 37 #define RESET_VECTOR_VADDR 0x596f8000 38 39 #define MBOX_OFFSET 0x800000 40 #define MBOX_SIZE 0x1000 41 42 struct imx8_priv { 43 struct device *dev; 44 struct snd_sof_dev *sdev; 45 46 /* DSP IPC handler */ 47 struct imx_dsp_ipc *dsp_ipc; 48 struct platform_device *ipc_dev; 49 50 /* System Controller IPC handler */ 51 struct imx_sc_ipc *sc_ipc; 52 53 /* Power domain handling */ 54 int num_domains; 55 struct device **pd_dev; 56 struct device_link **link; 57 58 }; 59 60 static void imx8_get_reply(struct snd_sof_dev *sdev) 61 { 62 struct snd_sof_ipc_msg *msg = sdev->msg; 63 struct sof_ipc_reply reply; 64 int ret = 0; 65 66 if (!msg) { 67 dev_warn(sdev->dev, "unexpected ipc interrupt\n"); 68 return; 69 } 70 71 /* get reply */ 72 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 73 74 if (reply.error < 0) { 75 memcpy(msg->reply_data, &reply, sizeof(reply)); 76 ret = reply.error; 77 } else { 78 /* reply has correct size? */ 79 if (reply.hdr.size != msg->reply_size) { 80 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 81 msg->reply_size, reply.hdr.size); 82 ret = -EINVAL; 83 } 84 85 /* read the message */ 86 if (msg->reply_size > 0) 87 sof_mailbox_read(sdev, sdev->host_box.offset, 88 msg->reply_data, msg->reply_size); 89 } 90 91 msg->reply_error = ret; 92 } 93 94 static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev) 95 { 96 return MBOX_OFFSET; 97 } 98 99 static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id) 100 { 101 return MBOX_OFFSET; 102 } 103 104 static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc) 105 { 106 struct imx8_priv *priv = imx_dsp_get_data(ipc); 107 unsigned long flags; 108 109 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 110 imx8_get_reply(priv->sdev); 111 snd_sof_ipc_reply(priv->sdev, 0); 112 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 113 } 114 115 static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc) 116 { 117 struct imx8_priv *priv = imx_dsp_get_data(ipc); 118 119 snd_sof_ipc_msgs_rx(priv->sdev); 120 } 121 122 static struct imx_dsp_ops dsp_ops = { 123 .handle_reply = imx8_dsp_handle_reply, 124 .handle_request = imx8_dsp_handle_request, 125 }; 126 127 static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 128 { 129 struct imx8_priv *priv = (struct imx8_priv *)sdev->private; 130 131 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 132 msg->msg_size); 133 imx_dsp_ring_doorbell(priv->dsp_ipc, 0); 134 135 return 0; 136 } 137 138 /* 139 * DSP control. 140 */ 141 static int imx8x_run(struct snd_sof_dev *sdev) 142 { 143 struct imx8_priv *dsp_priv = (struct imx8_priv *)sdev->private; 144 int ret; 145 146 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 147 IMX_SC_C_OFS_SEL, 1); 148 if (ret < 0) { 149 dev_err(sdev->dev, "Error system address offset source select\n"); 150 return ret; 151 } 152 153 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 154 IMX_SC_C_OFS_AUDIO, 0x80); 155 if (ret < 0) { 156 dev_err(sdev->dev, "Error system address offset of AUDIO\n"); 157 return ret; 158 } 159 160 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 161 IMX_SC_C_OFS_PERIPH, 0x5A); 162 if (ret < 0) { 163 dev_err(sdev->dev, "Error system address offset of PERIPH %d\n", 164 ret); 165 return ret; 166 } 167 168 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 169 IMX_SC_C_OFS_IRQ, 0x51); 170 if (ret < 0) { 171 dev_err(sdev->dev, "Error system address offset of IRQ\n"); 172 return ret; 173 } 174 175 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true, 176 RESET_VECTOR_VADDR); 177 178 return 0; 179 } 180 181 static int imx8_run(struct snd_sof_dev *sdev) 182 { 183 struct imx8_priv *dsp_priv = (struct imx8_priv *)sdev->private; 184 int ret; 185 186 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 187 IMX_SC_C_OFS_SEL, 0); 188 if (ret < 0) { 189 dev_err(sdev->dev, "Error system address offset source select\n"); 190 return ret; 191 } 192 193 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true, 194 RESET_VECTOR_VADDR); 195 196 return 0; 197 } 198 199 static int imx8_probe(struct snd_sof_dev *sdev) 200 { 201 struct platform_device *pdev = 202 container_of(sdev->dev, struct platform_device, dev); 203 struct device_node *np = pdev->dev.of_node; 204 struct device_node *res_node; 205 struct resource *mmio; 206 struct imx8_priv *priv; 207 struct resource res; 208 u32 base, size; 209 int ret = 0; 210 int i; 211 212 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 213 if (!priv) 214 return -ENOMEM; 215 216 sdev->private = priv; 217 priv->dev = sdev->dev; 218 priv->sdev = sdev; 219 220 /* power up device associated power domains */ 221 priv->num_domains = of_count_phandle_with_args(np, "power-domains", 222 "#power-domain-cells"); 223 if (priv->num_domains < 0) { 224 dev_err(sdev->dev, "no power-domains property in %pOF\n", np); 225 return priv->num_domains; 226 } 227 228 priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains, 229 sizeof(*priv->pd_dev), GFP_KERNEL); 230 if (!priv->pd_dev) 231 return -ENOMEM; 232 233 priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains, 234 sizeof(*priv->link), GFP_KERNEL); 235 if (!priv->link) 236 return -ENOMEM; 237 238 for (i = 0; i < priv->num_domains; i++) { 239 priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i); 240 if (IS_ERR(priv->pd_dev[i])) { 241 ret = PTR_ERR(priv->pd_dev[i]); 242 goto exit_unroll_pm; 243 } 244 priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i], 245 DL_FLAG_STATELESS | 246 DL_FLAG_PM_RUNTIME | 247 DL_FLAG_RPM_ACTIVE); 248 if (!priv->link[i]) { 249 ret = -ENOMEM; 250 dev_pm_domain_detach(priv->pd_dev[i], false); 251 goto exit_unroll_pm; 252 } 253 } 254 255 ret = imx_scu_get_handle(&priv->sc_ipc); 256 if (ret) { 257 dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n", 258 ret); 259 goto exit_unroll_pm; 260 } 261 262 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", 263 PLATFORM_DEVID_NONE, 264 pdev, sizeof(*pdev)); 265 if (IS_ERR(priv->ipc_dev)) { 266 ret = PTR_ERR(priv->ipc_dev); 267 goto exit_unroll_pm; 268 } 269 270 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 271 if (!priv->dsp_ipc) { 272 /* DSP IPC driver not probed yet, try later */ 273 ret = -EPROBE_DEFER; 274 dev_err(sdev->dev, "Failed to get drvdata\n"); 275 goto exit_pdev_unregister; 276 } 277 278 imx_dsp_set_data(priv->dsp_ipc, priv); 279 priv->dsp_ipc->ops = &dsp_ops; 280 281 /* DSP base */ 282 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 283 if (mmio) { 284 base = mmio->start; 285 size = resource_size(mmio); 286 } else { 287 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n"); 288 ret = -EINVAL; 289 goto exit_pdev_unregister; 290 } 291 292 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); 293 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 294 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n", 295 base, size); 296 ret = -ENODEV; 297 goto exit_pdev_unregister; 298 } 299 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM; 300 301 res_node = of_parse_phandle(np, "memory-region", 0); 302 if (!res_node) { 303 dev_err(&pdev->dev, "failed to get memory region node\n"); 304 ret = -ENODEV; 305 goto exit_pdev_unregister; 306 } 307 308 ret = of_address_to_resource(res_node, 0, &res); 309 if (ret) { 310 dev_err(&pdev->dev, "failed to get reserved region address\n"); 311 goto exit_pdev_unregister; 312 } 313 314 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start, 315 resource_size(&res)); 316 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 317 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n", 318 base, size); 319 ret = -ENOMEM; 320 goto exit_pdev_unregister; 321 } 322 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 323 324 /* set default mailbox offset for FW ready message */ 325 sdev->dsp_box.offset = MBOX_OFFSET; 326 327 return 0; 328 329 exit_pdev_unregister: 330 platform_device_unregister(priv->ipc_dev); 331 exit_unroll_pm: 332 while (--i >= 0) { 333 device_link_del(priv->link[i]); 334 dev_pm_domain_detach(priv->pd_dev[i], false); 335 } 336 337 return ret; 338 } 339 340 static int imx8_remove(struct snd_sof_dev *sdev) 341 { 342 struct imx8_priv *priv = (struct imx8_priv *)sdev->private; 343 int i; 344 345 platform_device_unregister(priv->ipc_dev); 346 347 for (i = 0; i < priv->num_domains; i++) { 348 device_link_del(priv->link[i]); 349 dev_pm_domain_detach(priv->pd_dev[i], false); 350 } 351 352 return 0; 353 } 354 355 /* on i.MX8 there is 1 to 1 match between type and BAR idx */ 356 static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type) 357 { 358 return type; 359 } 360 361 static void imx8_ipc_msg_data(struct snd_sof_dev *sdev, 362 struct snd_pcm_substream *substream, 363 void *p, size_t sz) 364 { 365 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz); 366 } 367 368 static int imx8_ipc_pcm_params(struct snd_sof_dev *sdev, 369 struct snd_pcm_substream *substream, 370 const struct sof_ipc_pcm_params_reply *reply) 371 { 372 return 0; 373 } 374 375 static struct snd_soc_dai_driver imx8_dai[] = { 376 { 377 .name = "esai0", 378 .playback = { 379 .channels_min = 1, 380 .channels_max = 8, 381 }, 382 .capture = { 383 .channels_min = 1, 384 .channels_max = 8, 385 }, 386 }, 387 { 388 .name = "sai1", 389 .playback = { 390 .channels_min = 1, 391 .channels_max = 32, 392 }, 393 .capture = { 394 .channels_min = 1, 395 .channels_max = 32, 396 }, 397 }, 398 }; 399 400 /* i.MX8 ops */ 401 struct snd_sof_dsp_ops sof_imx8_ops = { 402 /* probe and remove */ 403 .probe = imx8_probe, 404 .remove = imx8_remove, 405 /* DSP core boot */ 406 .run = imx8_run, 407 408 /* Block IO */ 409 .block_read = sof_block_read, 410 .block_write = sof_block_write, 411 412 /* ipc */ 413 .send_msg = imx8_send_msg, 414 .fw_ready = sof_fw_ready, 415 .get_mailbox_offset = imx8_get_mailbox_offset, 416 .get_window_offset = imx8_get_window_offset, 417 418 .ipc_msg_data = imx8_ipc_msg_data, 419 .ipc_pcm_params = imx8_ipc_pcm_params, 420 421 /* module loading */ 422 .load_module = snd_sof_parse_module_memcpy, 423 .get_bar_index = imx8_get_bar_index, 424 /* firmware loading */ 425 .load_firmware = snd_sof_load_firmware_memcpy, 426 427 /* DAI drivers */ 428 .drv = imx8_dai, 429 .num_drv = ARRAY_SIZE(imx8_dai), 430 431 /* ALSA HW info flags */ 432 .hw_info = SNDRV_PCM_INFO_MMAP | 433 SNDRV_PCM_INFO_MMAP_VALID | 434 SNDRV_PCM_INFO_INTERLEAVED | 435 SNDRV_PCM_INFO_PAUSE | 436 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 437 }; 438 EXPORT_SYMBOL(sof_imx8_ops); 439 440 /* i.MX8X ops */ 441 struct snd_sof_dsp_ops sof_imx8x_ops = { 442 /* probe and remove */ 443 .probe = imx8_probe, 444 .remove = imx8_remove, 445 /* DSP core boot */ 446 .run = imx8x_run, 447 448 /* Block IO */ 449 .block_read = sof_block_read, 450 .block_write = sof_block_write, 451 452 /* ipc */ 453 .send_msg = imx8_send_msg, 454 .fw_ready = sof_fw_ready, 455 .get_mailbox_offset = imx8_get_mailbox_offset, 456 .get_window_offset = imx8_get_window_offset, 457 458 .ipc_msg_data = imx8_ipc_msg_data, 459 .ipc_pcm_params = imx8_ipc_pcm_params, 460 461 /* module loading */ 462 .load_module = snd_sof_parse_module_memcpy, 463 .get_bar_index = imx8_get_bar_index, 464 /* firmware loading */ 465 .load_firmware = snd_sof_load_firmware_memcpy, 466 467 /* DAI drivers */ 468 .drv = imx8_dai, 469 .num_drv = ARRAY_SIZE(imx8_dai), 470 471 /* ALSA HW info flags */ 472 .hw_info = SNDRV_PCM_INFO_MMAP | 473 SNDRV_PCM_INFO_MMAP_VALID | 474 SNDRV_PCM_INFO_INTERLEAVED | 475 SNDRV_PCM_INFO_PAUSE | 476 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 477 }; 478 EXPORT_SYMBOL(sof_imx8x_ops); 479 480 MODULE_LICENSE("Dual BSD/GPL"); 481