1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright 2019 NXP 4 // 5 // Author: Daniel Baluta <daniel.baluta@nxp.com> 6 // 7 // Hardware interface for audio DSP on i.MX8 8 9 #include <linux/firmware.h> 10 #include <linux/of_platform.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_domain.h> 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include <linux/firmware/imx/ipc.h> 19 #include <linux/firmware/imx/dsp.h> 20 21 #include <linux/firmware/imx/svc/misc.h> 22 #include <dt-bindings/firmware/imx/rsrc.h> 23 #include "../ops.h" 24 #include "imx-common.h" 25 #include "imx-ops.h" 26 27 /* DSP memories */ 28 #define IRAM_OFFSET 0x10000 29 #define IRAM_SIZE (2 * 1024) 30 #define DRAM0_OFFSET 0x0 31 #define DRAM0_SIZE (32 * 1024) 32 #define DRAM1_OFFSET 0x8000 33 #define DRAM1_SIZE (32 * 1024) 34 #define SYSRAM_OFFSET 0x18000 35 #define SYSRAM_SIZE (256 * 1024) 36 #define SYSROM_OFFSET 0x58000 37 #define SYSROM_SIZE (192 * 1024) 38 39 #define RESET_VECTOR_VADDR 0x596f8000 40 41 #define MBOX_OFFSET 0x800000 42 #define MBOX_SIZE 0x1000 43 44 struct imx8_priv { 45 struct device *dev; 46 struct snd_sof_dev *sdev; 47 48 /* DSP IPC handler */ 49 struct imx_dsp_ipc *dsp_ipc; 50 struct platform_device *ipc_dev; 51 52 /* System Controller IPC handler */ 53 struct imx_sc_ipc *sc_ipc; 54 55 /* Power domain handling */ 56 int num_domains; 57 struct device **pd_dev; 58 struct device_link **link; 59 60 }; 61 62 static void imx8_get_reply(struct snd_sof_dev *sdev) 63 { 64 struct snd_sof_ipc_msg *msg = sdev->msg; 65 struct sof_ipc_reply reply; 66 int ret = 0; 67 68 if (!msg) { 69 dev_warn(sdev->dev, "unexpected ipc interrupt\n"); 70 return; 71 } 72 73 /* get reply */ 74 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 75 76 if (reply.error < 0) { 77 memcpy(msg->reply_data, &reply, sizeof(reply)); 78 ret = reply.error; 79 } else { 80 /* reply has correct size? */ 81 if (reply.hdr.size != msg->reply_size) { 82 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 83 msg->reply_size, reply.hdr.size); 84 ret = -EINVAL; 85 } 86 87 /* read the message */ 88 if (msg->reply_size > 0) 89 sof_mailbox_read(sdev, sdev->host_box.offset, 90 msg->reply_data, msg->reply_size); 91 } 92 93 msg->reply_error = ret; 94 } 95 96 static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev) 97 { 98 return MBOX_OFFSET; 99 } 100 101 static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id) 102 { 103 return MBOX_OFFSET; 104 } 105 106 static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc) 107 { 108 struct imx8_priv *priv = imx_dsp_get_data(ipc); 109 unsigned long flags; 110 111 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 112 imx8_get_reply(priv->sdev); 113 snd_sof_ipc_reply(priv->sdev, 0); 114 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 115 } 116 117 static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc) 118 { 119 struct imx8_priv *priv = imx_dsp_get_data(ipc); 120 u32 p; /* panic code */ 121 122 /* Read the message from the debug box. */ 123 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p)); 124 125 /* Check to see if the message is a panic code (0x0dead***) */ 126 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) 127 snd_sof_dsp_panic(priv->sdev, p); 128 else 129 snd_sof_ipc_msgs_rx(priv->sdev); 130 } 131 132 static struct imx_dsp_ops dsp_ops = { 133 .handle_reply = imx8_dsp_handle_reply, 134 .handle_request = imx8_dsp_handle_request, 135 }; 136 137 static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 138 { 139 struct imx8_priv *priv = sdev->pdata->hw_pdata; 140 141 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 142 msg->msg_size); 143 imx_dsp_ring_doorbell(priv->dsp_ipc, 0); 144 145 return 0; 146 } 147 148 /* 149 * DSP control. 150 */ 151 static int imx8x_run(struct snd_sof_dev *sdev) 152 { 153 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata; 154 int ret; 155 156 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 157 IMX_SC_C_OFS_SEL, 1); 158 if (ret < 0) { 159 dev_err(sdev->dev, "Error system address offset source select\n"); 160 return ret; 161 } 162 163 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 164 IMX_SC_C_OFS_AUDIO, 0x80); 165 if (ret < 0) { 166 dev_err(sdev->dev, "Error system address offset of AUDIO\n"); 167 return ret; 168 } 169 170 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 171 IMX_SC_C_OFS_PERIPH, 0x5A); 172 if (ret < 0) { 173 dev_err(sdev->dev, "Error system address offset of PERIPH %d\n", 174 ret); 175 return ret; 176 } 177 178 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 179 IMX_SC_C_OFS_IRQ, 0x51); 180 if (ret < 0) { 181 dev_err(sdev->dev, "Error system address offset of IRQ\n"); 182 return ret; 183 } 184 185 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true, 186 RESET_VECTOR_VADDR); 187 188 return 0; 189 } 190 191 static int imx8_run(struct snd_sof_dev *sdev) 192 { 193 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata; 194 int ret; 195 196 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP, 197 IMX_SC_C_OFS_SEL, 0); 198 if (ret < 0) { 199 dev_err(sdev->dev, "Error system address offset source select\n"); 200 return ret; 201 } 202 203 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true, 204 RESET_VECTOR_VADDR); 205 206 return 0; 207 } 208 209 static int imx8_probe(struct snd_sof_dev *sdev) 210 { 211 struct platform_device *pdev = 212 container_of(sdev->dev, struct platform_device, dev); 213 struct device_node *np = pdev->dev.of_node; 214 struct device_node *res_node; 215 struct resource *mmio; 216 struct imx8_priv *priv; 217 struct resource res; 218 u32 base, size; 219 int ret = 0; 220 int i; 221 222 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 223 if (!priv) 224 return -ENOMEM; 225 226 sdev->pdata->hw_pdata = priv; 227 priv->dev = sdev->dev; 228 priv->sdev = sdev; 229 230 /* power up device associated power domains */ 231 priv->num_domains = of_count_phandle_with_args(np, "power-domains", 232 "#power-domain-cells"); 233 if (priv->num_domains < 0) { 234 dev_err(sdev->dev, "no power-domains property in %pOF\n", np); 235 return priv->num_domains; 236 } 237 238 priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains, 239 sizeof(*priv->pd_dev), GFP_KERNEL); 240 if (!priv->pd_dev) 241 return -ENOMEM; 242 243 priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains, 244 sizeof(*priv->link), GFP_KERNEL); 245 if (!priv->link) 246 return -ENOMEM; 247 248 for (i = 0; i < priv->num_domains; i++) { 249 priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i); 250 if (IS_ERR(priv->pd_dev[i])) { 251 ret = PTR_ERR(priv->pd_dev[i]); 252 goto exit_unroll_pm; 253 } 254 priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i], 255 DL_FLAG_STATELESS | 256 DL_FLAG_PM_RUNTIME | 257 DL_FLAG_RPM_ACTIVE); 258 if (!priv->link[i]) { 259 ret = -ENOMEM; 260 dev_pm_domain_detach(priv->pd_dev[i], false); 261 goto exit_unroll_pm; 262 } 263 } 264 265 ret = imx_scu_get_handle(&priv->sc_ipc); 266 if (ret) { 267 dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n", 268 ret); 269 goto exit_unroll_pm; 270 } 271 272 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", 273 PLATFORM_DEVID_NONE, 274 pdev, sizeof(*pdev)); 275 if (IS_ERR(priv->ipc_dev)) { 276 ret = PTR_ERR(priv->ipc_dev); 277 goto exit_unroll_pm; 278 } 279 280 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 281 if (!priv->dsp_ipc) { 282 /* DSP IPC driver not probed yet, try later */ 283 ret = -EPROBE_DEFER; 284 dev_err(sdev->dev, "Failed to get drvdata\n"); 285 goto exit_pdev_unregister; 286 } 287 288 imx_dsp_set_data(priv->dsp_ipc, priv); 289 priv->dsp_ipc->ops = &dsp_ops; 290 291 /* DSP base */ 292 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 293 if (mmio) { 294 base = mmio->start; 295 size = resource_size(mmio); 296 } else { 297 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n"); 298 ret = -EINVAL; 299 goto exit_pdev_unregister; 300 } 301 302 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); 303 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 304 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n", 305 base, size); 306 ret = -ENODEV; 307 goto exit_pdev_unregister; 308 } 309 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM; 310 311 res_node = of_parse_phandle(np, "memory-region", 0); 312 if (!res_node) { 313 dev_err(&pdev->dev, "failed to get memory region node\n"); 314 ret = -ENODEV; 315 goto exit_pdev_unregister; 316 } 317 318 ret = of_address_to_resource(res_node, 0, &res); 319 of_node_put(res_node); 320 if (ret) { 321 dev_err(&pdev->dev, "failed to get reserved region address\n"); 322 goto exit_pdev_unregister; 323 } 324 325 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start, 326 resource_size(&res)); 327 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 328 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n", 329 base, size); 330 ret = -ENOMEM; 331 goto exit_pdev_unregister; 332 } 333 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 334 335 /* set default mailbox offset for FW ready message */ 336 sdev->dsp_box.offset = MBOX_OFFSET; 337 338 return 0; 339 340 exit_pdev_unregister: 341 platform_device_unregister(priv->ipc_dev); 342 exit_unroll_pm: 343 while (--i >= 0) { 344 device_link_del(priv->link[i]); 345 dev_pm_domain_detach(priv->pd_dev[i], false); 346 } 347 348 return ret; 349 } 350 351 static int imx8_remove(struct snd_sof_dev *sdev) 352 { 353 struct imx8_priv *priv = sdev->pdata->hw_pdata; 354 int i; 355 356 platform_device_unregister(priv->ipc_dev); 357 358 for (i = 0; i < priv->num_domains; i++) { 359 device_link_del(priv->link[i]); 360 dev_pm_domain_detach(priv->pd_dev[i], false); 361 } 362 363 return 0; 364 } 365 366 /* on i.MX8 there is 1 to 1 match between type and BAR idx */ 367 static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type) 368 { 369 /* Only IRAM and SRAM bars are valid */ 370 switch (type) { 371 case SOF_FW_BLK_TYPE_IRAM: 372 case SOF_FW_BLK_TYPE_SRAM: 373 return type; 374 default: 375 return -EINVAL; 376 } 377 } 378 379 static struct snd_soc_dai_driver imx8_dai[] = { 380 { 381 .name = "esai0", 382 .playback = { 383 .channels_min = 1, 384 .channels_max = 8, 385 }, 386 .capture = { 387 .channels_min = 1, 388 .channels_max = 8, 389 }, 390 }, 391 { 392 .name = "sai1", 393 .playback = { 394 .channels_min = 1, 395 .channels_max = 32, 396 }, 397 .capture = { 398 .channels_min = 1, 399 .channels_max = 32, 400 }, 401 }, 402 }; 403 404 /* i.MX8 ops */ 405 struct snd_sof_dsp_ops sof_imx8_ops = { 406 /* probe and remove */ 407 .probe = imx8_probe, 408 .remove = imx8_remove, 409 /* DSP core boot */ 410 .run = imx8_run, 411 412 /* Block IO */ 413 .block_read = sof_block_read, 414 .block_write = sof_block_write, 415 416 /* Mailbox IO */ 417 .mailbox_read = sof_mailbox_read, 418 .mailbox_write = sof_mailbox_write, 419 420 /* ipc */ 421 .send_msg = imx8_send_msg, 422 .fw_ready = sof_fw_ready, 423 .get_mailbox_offset = imx8_get_mailbox_offset, 424 .get_window_offset = imx8_get_window_offset, 425 426 .ipc_msg_data = sof_ipc_msg_data, 427 .ipc_pcm_params = sof_ipc_pcm_params, 428 429 /* module loading */ 430 .load_module = snd_sof_parse_module_memcpy, 431 .get_bar_index = imx8_get_bar_index, 432 /* firmware loading */ 433 .load_firmware = snd_sof_load_firmware_memcpy, 434 435 /* Debug information */ 436 .dbg_dump = imx8_dump, 437 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 438 439 /* stream callbacks */ 440 .pcm_open = sof_stream_pcm_open, 441 .pcm_close = sof_stream_pcm_close, 442 443 /* Firmware ops */ 444 .dsp_arch_ops = &sof_xtensa_arch_ops, 445 446 /* DAI drivers */ 447 .drv = imx8_dai, 448 .num_drv = ARRAY_SIZE(imx8_dai), 449 450 /* ALSA HW info flags */ 451 .hw_info = SNDRV_PCM_INFO_MMAP | 452 SNDRV_PCM_INFO_MMAP_VALID | 453 SNDRV_PCM_INFO_INTERLEAVED | 454 SNDRV_PCM_INFO_PAUSE | 455 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 456 }; 457 EXPORT_SYMBOL(sof_imx8_ops); 458 459 /* i.MX8X ops */ 460 struct snd_sof_dsp_ops sof_imx8x_ops = { 461 /* probe and remove */ 462 .probe = imx8_probe, 463 .remove = imx8_remove, 464 /* DSP core boot */ 465 .run = imx8x_run, 466 467 /* Block IO */ 468 .block_read = sof_block_read, 469 .block_write = sof_block_write, 470 471 /* Mailbox IO */ 472 .mailbox_read = sof_mailbox_read, 473 .mailbox_write = sof_mailbox_write, 474 475 /* ipc */ 476 .send_msg = imx8_send_msg, 477 .fw_ready = sof_fw_ready, 478 .get_mailbox_offset = imx8_get_mailbox_offset, 479 .get_window_offset = imx8_get_window_offset, 480 481 .ipc_msg_data = sof_ipc_msg_data, 482 .ipc_pcm_params = sof_ipc_pcm_params, 483 484 /* module loading */ 485 .load_module = snd_sof_parse_module_memcpy, 486 .get_bar_index = imx8_get_bar_index, 487 /* firmware loading */ 488 .load_firmware = snd_sof_load_firmware_memcpy, 489 490 /* Debug information */ 491 .dbg_dump = imx8_dump, 492 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 493 494 /* stream callbacks */ 495 .pcm_open = sof_stream_pcm_open, 496 .pcm_close = sof_stream_pcm_close, 497 498 /* Firmware ops */ 499 .dsp_arch_ops = &sof_xtensa_arch_ops, 500 501 /* DAI drivers */ 502 .drv = imx8_dai, 503 .num_drv = ARRAY_SIZE(imx8_dai), 504 505 /* ALSA HW info flags */ 506 .hw_info = SNDRV_PCM_INFO_MMAP | 507 SNDRV_PCM_INFO_MMAP_VALID | 508 SNDRV_PCM_INFO_INTERLEAVED | 509 SNDRV_PCM_INFO_PAUSE | 510 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 511 }; 512 EXPORT_SYMBOL(sof_imx8x_ops); 513 514 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 515 MODULE_LICENSE("Dual BSD/GPL"); 516