1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include "../sof-priv.h" 15 #include "../sof-audio.h" 16 17 #define ACP_MAX_STREAM 8 18 19 #define ACP_DSP_BAR 0 20 21 #define ACP_HW_SEM_RETRY_COUNT 10000 22 #define ACP_REG_POLL_INTERVAL 500 23 #define ACP_REG_POLL_TIMEOUT_US 2000 24 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 25 26 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 27 #define ACP_PGFSM_STATUS_MASK 0x03 28 #define ACP_POWERED_ON 0x00 29 #define ACP_ASSERT_RESET 0x01 30 #define ACP_RELEASE_RESET 0x00 31 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 32 33 #define ACP_DSP_INTR_EN_MASK 0x00000001 34 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 35 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 36 #define PAGE_SIZE_4K_ENABLE 0x2 37 #define ACP_PAGE_SIZE 0x1000 38 #define ACP_DMA_CH_RUN 0x02 39 #define ACP_MAX_DESC_CNT 0x02 40 #define DSP_FW_RUN_ENABLE 0x01 41 #define ACP_SHA_RUN 0x01 42 #define ACP_SHA_RESET 0x02 43 #define ACP_DMA_CH_RST 0x01 44 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 45 #define ACP_ATU_CACHE_INVALID 0x01 46 #define ACP_MAX_DESC 128 47 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 48 49 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 50 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 51 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 52 #define ACP_IRAM_BASE_ADDRESS 0x000000 53 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 54 #define ACP_DRAM_PAGE_COUNT 128 55 56 #define ACP_DSP_TO_HOST_IRQ 0x04 57 58 #define HOST_BRIDGE_CZN 0x1630 59 #define HOST_BRIDGE_RMB 0x14B5 60 #define ACP_SHA_STAT 0x8000 61 #define ACP_PSP_TIMEOUT_COUNTER 5 62 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 63 #define MP0_C2PMSG_114_REG 0x3810AC8 64 #define MP0_C2PMSG_73_REG 0x3810A24 65 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 66 #define MBOX_DELAY 1000 67 #define MBOX_READY_MASK 0x80000000 68 #define MBOX_STATUS_MASK 0xFFFF 69 70 #define BOX_SIZE_512 0x200 71 #define BOX_SIZE_1024 0x400 72 73 #define EXCEPT_MAX_HDR_SIZE 0x400 74 #define AMD_STACK_DUMP_SIZE 32 75 76 #define SRAM1_SIZE 0x13A000 77 78 enum clock_source { 79 ACP_CLOCK_96M = 0, 80 ACP_CLOCK_48M, 81 ACP_CLOCK_24M, 82 ACP_CLOCK_ACLK, 83 ACP_CLOCK_MCLK, 84 }; 85 86 struct acp_atu_grp_pte { 87 u32 low; 88 u32 high; 89 }; 90 91 union dma_tx_cnt { 92 struct { 93 unsigned int count : 19; 94 unsigned int reserved : 12; 95 unsigned ioc : 1; 96 } bitfields, bits; 97 unsigned int u32_all; 98 signed int i32_all; 99 }; 100 101 struct dma_descriptor { 102 unsigned int src_addr; 103 unsigned int dest_addr; 104 union dma_tx_cnt tx_cnt; 105 unsigned int reserved; 106 }; 107 108 /* Scratch memory structure for communication b/w host and dsp */ 109 struct scratch_ipc_conf { 110 /* Debug memory */ 111 u8 sof_debug_box[1024]; 112 /* Exception memory*/ 113 u8 sof_except_box[1024]; 114 /* Stream buffer */ 115 u8 sof_stream_box[1024]; 116 /* Trace buffer */ 117 u8 sof_trace_box[1024]; 118 /* Host msg flag */ 119 u32 sof_host_msg_write; 120 /* Host ack flag*/ 121 u32 sof_host_ack_write; 122 /* DSP msg flag */ 123 u32 sof_dsp_msg_write; 124 /* Dsp ack flag */ 125 u32 sof_dsp_ack_write; 126 }; 127 128 struct scratch_reg_conf { 129 struct scratch_ipc_conf info; 130 struct acp_atu_grp_pte grp1_pte[16]; 131 struct acp_atu_grp_pte grp2_pte[16]; 132 struct acp_atu_grp_pte grp3_pte[16]; 133 struct acp_atu_grp_pte grp4_pte[16]; 134 struct acp_atu_grp_pte grp5_pte[16]; 135 struct acp_atu_grp_pte grp6_pte[16]; 136 struct acp_atu_grp_pte grp7_pte[16]; 137 struct acp_atu_grp_pte grp8_pte[16]; 138 struct dma_descriptor dma_desc[64]; 139 unsigned int reg_offset[8]; 140 unsigned int buf_size[8]; 141 u8 acp_tx_fifo_buf[256]; 142 u8 acp_rx_fifo_buf[256]; 143 unsigned int reserve[]; 144 }; 145 146 struct acp_dsp_stream { 147 struct list_head list; 148 struct snd_sof_dev *sdev; 149 struct snd_pcm_substream *substream; 150 struct snd_dma_buffer *dmab; 151 int num_pages; 152 int stream_tag; 153 int active; 154 unsigned int reg_offset; 155 size_t posn_offset; 156 }; 157 158 struct sof_amd_acp_desc { 159 unsigned int rev; 160 unsigned int host_bridge_id; 161 unsigned int i2s_mode; 162 u32 pgfsm_base; 163 u32 ext_intr_stat; 164 u32 dsp_intr_base; 165 u32 sram_pte_offset; 166 u32 i2s_pin_config_offset; 167 u32 hw_semaphore_offset; 168 u32 acp_clkmux_sel; 169 u32 fusion_dsp_offset; 170 }; 171 172 /* Common device data struct for ACP devices */ 173 struct acp_dev_data { 174 struct snd_sof_dev *dev; 175 unsigned int fw_bin_size; 176 unsigned int fw_data_bin_size; 177 u32 fw_bin_page_count; 178 dma_addr_t sha_dma_addr; 179 u8 *bin_buf; 180 dma_addr_t dma_addr; 181 u8 *data_buf; 182 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 183 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 184 struct acp_dsp_stream *dtrace_stream; 185 struct pci_dev *smn_dev; 186 }; 187 188 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 189 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 190 191 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 192 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 193 unsigned int dest_addr, int dsp_data_size); 194 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 195 unsigned int start_addr, unsigned int dest_addr, 196 unsigned int image_length); 197 198 /* ACP device probe/remove */ 199 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 200 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 201 202 /* DSP Loader callbacks */ 203 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 204 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 205 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 206 207 /* Block IO callbacks */ 208 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 209 u32 offset, void *src, size_t size); 210 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 211 u32 offset, void *dest, size_t size); 212 213 /* IPC callbacks */ 214 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 215 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 216 void *p, size_t sz); 217 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 218 struct snd_sof_pcm_stream *sps, 219 size_t posn_offset); 220 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 221 struct snd_sof_ipc_msg *msg); 222 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 223 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 224 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 225 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 226 227 /* ACP - DSP stream callbacks */ 228 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 229 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 230 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 231 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 232 233 /* 234 * DSP PCM Operations. 235 */ 236 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 237 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 238 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 239 struct snd_pcm_hw_params *params, 240 struct snd_sof_platform_stream_params *platform_params); 241 242 extern struct snd_sof_dsp_ops sof_acp_common_ops; 243 244 extern struct snd_sof_dsp_ops sof_renoir_ops; 245 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 246 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 247 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 248 249 int acp_dai_probe(struct snd_soc_dai *dai); 250 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 251 /* Machine configuration */ 252 int snd_amd_acp_find_config(struct pci_dev *pci); 253 254 /* Trace */ 255 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 256 struct sof_ipc_dma_trace_params_ext *dtrace_params); 257 int acp_sof_trace_release(struct snd_sof_dev *sdev); 258 259 /* PM Callbacks */ 260 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 261 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 262 263 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 264 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 265 266 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 267 { 268 const struct sof_dev_desc *desc = pdata->desc; 269 270 return desc->chip_info; 271 } 272 #endif 273