1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP3X_PGFSM_STATUS_MASK 0x03 30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31 #define ACP6X_PGFSM_STATUS_MASK 0x0F 32 33 #define ACP_POWERED_ON 0x00 34 #define ACP_ASSERT_RESET 0x01 35 #define ACP_RELEASE_RESET 0x00 36 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 37 38 #define ACP_DSP_INTR_EN_MASK 0x00000001 39 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 40 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 41 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 42 #define PAGE_SIZE_4K_ENABLE 0x2 43 #define ACP_PAGE_SIZE 0x1000 44 #define ACP_DMA_CH_RUN 0x02 45 #define ACP_MAX_DESC_CNT 0x02 46 #define DSP_FW_RUN_ENABLE 0x01 47 #define ACP_SHA_RUN 0x01 48 #define ACP_SHA_RESET 0x02 49 #define ACP_SHA_HEADER 0x01 50 #define ACP_DMA_CH_RST 0x01 51 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 52 #define ACP_ATU_CACHE_INVALID 0x01 53 #define ACP_MAX_DESC 128 54 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 55 56 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 57 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 58 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 59 #define ACP_IRAM_BASE_ADDRESS 0x000000 60 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 61 #define ACP_DRAM_PAGE_COUNT 128 62 63 #define ACP_DSP_TO_HOST_IRQ 0x04 64 65 #define ACP_RN_PCI_ID 0x01 66 #define ACP_VANGOGH_PCI_ID 0x50 67 #define ACP_RMB_PCI_ID 0x6F 68 69 #define HOST_BRIDGE_CZN 0x1630 70 #define HOST_BRIDGE_VGH 0x1645 71 #define HOST_BRIDGE_RMB 0x14B5 72 #define ACP_SHA_STAT 0x8000 73 #define ACP_PSP_TIMEOUT_US 1000000 74 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 75 #define MP0_C2PMSG_114_REG 0x3810AC8 76 #define MP0_C2PMSG_73_REG 0x3810A24 77 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 78 #define MBOX_DELAY_US 1000 79 #define MBOX_READY_MASK 0x80000000 80 #define MBOX_STATUS_MASK 0xFFFF 81 82 #define BOX_SIZE_512 0x200 83 #define BOX_SIZE_1024 0x400 84 85 #define EXCEPT_MAX_HDR_SIZE 0x400 86 #define AMD_STACK_DUMP_SIZE 32 87 88 #define SRAM1_SIZE 0x13A000 89 #define PROBE_STATUS_BIT BIT(31) 90 91 #define ACP_FIRMWARE_SIGNATURE 0x100 92 93 enum clock_source { 94 ACP_CLOCK_96M = 0, 95 ACP_CLOCK_48M, 96 ACP_CLOCK_24M, 97 ACP_CLOCK_ACLK, 98 ACP_CLOCK_MCLK, 99 }; 100 101 struct acp_atu_grp_pte { 102 u32 low; 103 u32 high; 104 }; 105 106 union dma_tx_cnt { 107 struct { 108 unsigned int count : 19; 109 unsigned int reserved : 12; 110 unsigned ioc : 1; 111 } bitfields, bits; 112 unsigned int u32_all; 113 signed int i32_all; 114 }; 115 116 struct dma_descriptor { 117 unsigned int src_addr; 118 unsigned int dest_addr; 119 union dma_tx_cnt tx_cnt; 120 unsigned int reserved; 121 }; 122 123 /* Scratch memory structure for communication b/w host and dsp */ 124 struct scratch_ipc_conf { 125 /* Debug memory */ 126 u8 sof_debug_box[1024]; 127 /* Exception memory*/ 128 u8 sof_except_box[1024]; 129 /* Stream buffer */ 130 u8 sof_stream_box[1024]; 131 /* Trace buffer */ 132 u8 sof_trace_box[1024]; 133 /* Host msg flag */ 134 u32 sof_host_msg_write; 135 /* Host ack flag*/ 136 u32 sof_host_ack_write; 137 /* DSP msg flag */ 138 u32 sof_dsp_msg_write; 139 /* Dsp ack flag */ 140 u32 sof_dsp_ack_write; 141 }; 142 143 struct scratch_reg_conf { 144 struct scratch_ipc_conf info; 145 struct acp_atu_grp_pte grp1_pte[16]; 146 struct acp_atu_grp_pte grp2_pte[16]; 147 struct acp_atu_grp_pte grp3_pte[16]; 148 struct acp_atu_grp_pte grp4_pte[16]; 149 struct acp_atu_grp_pte grp5_pte[16]; 150 struct acp_atu_grp_pte grp6_pte[16]; 151 struct acp_atu_grp_pte grp7_pte[16]; 152 struct acp_atu_grp_pte grp8_pte[16]; 153 struct dma_descriptor dma_desc[64]; 154 unsigned int reg_offset[8]; 155 unsigned int buf_size[8]; 156 u8 acp_tx_fifo_buf[256]; 157 u8 acp_rx_fifo_buf[256]; 158 unsigned int reserve[]; 159 }; 160 161 struct acp_dsp_stream { 162 struct list_head list; 163 struct snd_sof_dev *sdev; 164 struct snd_pcm_substream *substream; 165 struct snd_dma_buffer *dmab; 166 int num_pages; 167 int stream_tag; 168 int active; 169 unsigned int reg_offset; 170 size_t posn_offset; 171 struct snd_compr_stream *cstream; 172 u64 cstream_posn; 173 }; 174 175 struct sof_amd_acp_desc { 176 unsigned int rev; 177 const char *name; 178 unsigned int host_bridge_id; 179 u32 pgfsm_base; 180 u32 ext_intr_enb; 181 u32 ext_intr_stat; 182 u32 dsp_intr_base; 183 u32 sram_pte_offset; 184 u32 hw_semaphore_offset; 185 u32 acp_clkmux_sel; 186 u32 fusion_dsp_offset; 187 u32 probe_reg_offset; 188 }; 189 190 /* Common device data struct for ACP devices */ 191 struct acp_dev_data { 192 struct snd_sof_dev *dev; 193 const struct firmware *fw_dbin; 194 /* DMIC device */ 195 struct platform_device *dmic_dev; 196 unsigned int fw_bin_size; 197 unsigned int fw_data_bin_size; 198 const char *fw_code_bin; 199 const char *fw_data_bin; 200 u32 fw_bin_page_count; 201 dma_addr_t sha_dma_addr; 202 u8 *bin_buf; 203 dma_addr_t dma_addr; 204 u8 *data_buf; 205 bool signed_fw_image; 206 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 207 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 208 struct acp_dsp_stream *dtrace_stream; 209 struct pci_dev *smn_dev; 210 struct acp_dsp_stream *probe_stream; 211 bool enable_fw_debug; 212 }; 213 214 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 215 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 216 217 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 218 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 219 unsigned int dest_addr, int dsp_data_size); 220 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 221 unsigned int start_addr, unsigned int dest_addr, 222 unsigned int image_length); 223 224 /* ACP device probe/remove */ 225 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 226 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 227 228 /* DSP Loader callbacks */ 229 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 230 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 231 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 232 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 233 234 /* Block IO callbacks */ 235 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 236 u32 offset, void *src, size_t size); 237 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 238 u32 offset, void *dest, size_t size); 239 240 /* IPC callbacks */ 241 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 242 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 243 void *p, size_t sz); 244 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 245 struct snd_sof_pcm_stream *sps, 246 size_t posn_offset); 247 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 248 struct snd_sof_ipc_msg *msg); 249 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 250 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 251 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 252 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 253 254 /* ACP - DSP stream callbacks */ 255 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 256 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 257 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 258 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 259 260 /* 261 * DSP PCM Operations. 262 */ 263 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 264 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 265 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 266 struct snd_pcm_hw_params *params, 267 struct snd_sof_platform_stream_params *platform_params); 268 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 269 struct snd_pcm_substream *substream); 270 271 extern struct snd_sof_dsp_ops sof_acp_common_ops; 272 273 extern struct snd_sof_dsp_ops sof_renoir_ops; 274 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 275 extern struct snd_sof_dsp_ops sof_vangogh_ops; 276 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 277 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 278 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 279 280 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 281 /* Machine configuration */ 282 int snd_amd_acp_find_config(struct pci_dev *pci); 283 284 /* Trace */ 285 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 286 struct sof_ipc_dma_trace_params_ext *dtrace_params); 287 int acp_sof_trace_release(struct snd_sof_dev *sdev); 288 289 /* PM Callbacks */ 290 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 291 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 292 293 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 294 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 295 296 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 297 { 298 const struct sof_dev_desc *desc = pdata->desc; 299 300 return desc->chip_info; 301 } 302 303 int acp_probes_register(struct snd_sof_dev *sdev); 304 void acp_probes_unregister(struct snd_sof_dev *sdev); 305 306 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 307 extern const struct dmi_system_id acp_sof_quirk_table[]; 308 #endif 309