xref: /openbmc/linux/sound/soc/sof/amd/acp.h (revision c4c3c32d)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license. When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7  *
8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9  */
10 
11 #ifndef __SOF_AMD_ACP_H
12 #define __SOF_AMD_ACP_H
13 
14 #include "../sof-priv.h"
15 #include "../sof-audio.h"
16 
17 #define ACP_MAX_STREAM	8
18 
19 #define ACP_DSP_BAR	0
20 
21 #define ACP_HW_SEM_RETRY_COUNT			10000
22 #define ACP_REG_POLL_INTERVAL                   500
23 #define ACP_REG_POLL_TIMEOUT_US                 2000
24 #define ACP_DMA_COMPLETE_TIMEOUT_US		5000
25 
26 #define ACP_PGFSM_CNTL_POWER_ON_MASK		0x01
27 #define ACP_PGFSM_STATUS_MASK			0x03
28 #define ACP_POWERED_ON				0x00
29 #define ACP_ASSERT_RESET			0x01
30 #define ACP_RELEASE_RESET			0x00
31 #define ACP_SOFT_RESET_DONE_MASK		0x00010001
32 
33 #define ACP_DSP_INTR_EN_MASK			0x00000001
34 #define ACP3X_SRAM_PTE_OFFSET			0x02050000
35 #define ACP6X_SRAM_PTE_OFFSET			0x03800000
36 #define PAGE_SIZE_4K_ENABLE			0x2
37 #define ACP_PAGE_SIZE				0x1000
38 #define ACP_DMA_CH_RUN				0x02
39 #define ACP_MAX_DESC_CNT			0x02
40 #define DSP_FW_RUN_ENABLE			0x01
41 #define ACP_SHA_RUN				0x01
42 #define ACP_SHA_RESET				0x02
43 #define ACP_DMA_CH_RST				0x01
44 #define ACP_DMA_CH_GRACEFUL_RST_EN		0x10
45 #define ACP_ATU_CACHE_INVALID			0x01
46 #define ACP_MAX_DESC				128
47 #define ACPBUS_REG_BASE_OFFSET			ACP_DMA_CNTL_0
48 
49 #define ACP_DEFAULT_DRAM_LENGTH			0x00080000
50 #define ACP3X_SCRATCH_MEMORY_ADDRESS		0x02050000
51 #define ACP_SYSTEM_MEMORY_WINDOW		0x4000000
52 #define ACP_IRAM_BASE_ADDRESS			0x000000
53 #define ACP_DATA_RAM_BASE_ADDRESS		0x01000000
54 #define ACP_DRAM_PAGE_COUNT			128
55 
56 #define ACP_DSP_TO_HOST_IRQ			0x04
57 
58 #define ACP_RN_PCI_ID				0x01
59 #define ACP_RMB_PCI_ID				0x6F
60 
61 #define HOST_BRIDGE_CZN				0x1630
62 #define HOST_BRIDGE_RMB				0x14B5
63 #define ACP_SHA_STAT				0x8000
64 #define ACP_PSP_TIMEOUT_US			1000000
65 #define ACP_EXT_INTR_ERROR_STAT			0x20000000
66 #define MP0_C2PMSG_114_REG			0x3810AC8
67 #define MP0_C2PMSG_73_REG			0x3810A24
68 #define MBOX_ACP_SHA_DMA_COMMAND		0x70000
69 #define MBOX_DELAY_US				1000
70 #define MBOX_READY_MASK				0x80000000
71 #define MBOX_STATUS_MASK			0xFFFF
72 
73 #define BOX_SIZE_512				0x200
74 #define BOX_SIZE_1024				0x400
75 
76 #define EXCEPT_MAX_HDR_SIZE			0x400
77 #define AMD_STACK_DUMP_SIZE			32
78 
79 #define SRAM1_SIZE				0x13A000
80 #define PROBE_STATUS_BIT			BIT(31)
81 
82 enum clock_source {
83 	ACP_CLOCK_96M = 0,
84 	ACP_CLOCK_48M,
85 	ACP_CLOCK_24M,
86 	ACP_CLOCK_ACLK,
87 	ACP_CLOCK_MCLK,
88 };
89 
90 struct  acp_atu_grp_pte {
91 	u32 low;
92 	u32 high;
93 };
94 
95 union dma_tx_cnt {
96 	struct {
97 		unsigned int count : 19;
98 		unsigned int reserved : 12;
99 		unsigned ioc : 1;
100 	} bitfields, bits;
101 	unsigned int u32_all;
102 	signed int i32_all;
103 };
104 
105 struct dma_descriptor {
106 	unsigned int src_addr;
107 	unsigned int dest_addr;
108 	union dma_tx_cnt tx_cnt;
109 	unsigned int reserved;
110 };
111 
112 /* Scratch memory structure for communication b/w host and dsp */
113 struct  scratch_ipc_conf {
114 	/* Debug memory */
115 	u8 sof_debug_box[1024];
116 	/* Exception memory*/
117 	u8 sof_except_box[1024];
118 	/* Stream buffer */
119 	u8 sof_stream_box[1024];
120 	/* Trace buffer */
121 	u8 sof_trace_box[1024];
122 	/* Host msg flag */
123 	u32 sof_host_msg_write;
124 	/* Host ack flag*/
125 	u32 sof_host_ack_write;
126 	/* DSP msg flag */
127 	u32 sof_dsp_msg_write;
128 	/* Dsp ack flag */
129 	u32 sof_dsp_ack_write;
130 };
131 
132 struct  scratch_reg_conf {
133 	struct scratch_ipc_conf info;
134 	struct acp_atu_grp_pte grp1_pte[16];
135 	struct acp_atu_grp_pte grp2_pte[16];
136 	struct acp_atu_grp_pte grp3_pte[16];
137 	struct acp_atu_grp_pte grp4_pte[16];
138 	struct acp_atu_grp_pte grp5_pte[16];
139 	struct acp_atu_grp_pte grp6_pte[16];
140 	struct acp_atu_grp_pte grp7_pte[16];
141 	struct acp_atu_grp_pte grp8_pte[16];
142 	struct dma_descriptor dma_desc[64];
143 	unsigned int reg_offset[8];
144 	unsigned int buf_size[8];
145 	u8 acp_tx_fifo_buf[256];
146 	u8 acp_rx_fifo_buf[256];
147 	unsigned int    reserve[];
148 };
149 
150 struct acp_dsp_stream {
151 	struct list_head list;
152 	struct snd_sof_dev *sdev;
153 	struct snd_pcm_substream *substream;
154 	struct snd_dma_buffer *dmab;
155 	int num_pages;
156 	int stream_tag;
157 	int active;
158 	unsigned int reg_offset;
159 	size_t posn_offset;
160 	struct snd_compr_stream *cstream;
161 	u64 cstream_posn;
162 };
163 
164 struct sof_amd_acp_desc {
165 	unsigned int rev;
166 	unsigned int host_bridge_id;
167 	u32 pgfsm_base;
168 	u32 ext_intr_stat;
169 	u32 dsp_intr_base;
170 	u32 sram_pte_offset;
171 	u32 hw_semaphore_offset;
172 	u32 acp_clkmux_sel;
173 	u32 fusion_dsp_offset;
174 	u32 probe_reg_offset;
175 };
176 
177 /* Common device data struct for ACP devices */
178 struct acp_dev_data {
179 	struct snd_sof_dev  *dev;
180 	/* DMIC device */
181 	struct platform_device *dmic_dev;
182 	unsigned int fw_bin_size;
183 	unsigned int fw_data_bin_size;
184 	u32 fw_bin_page_count;
185 	dma_addr_t sha_dma_addr;
186 	u8 *bin_buf;
187 	dma_addr_t dma_addr;
188 	u8 *data_buf;
189 	struct dma_descriptor dscr_info[ACP_MAX_DESC];
190 	struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
191 	struct acp_dsp_stream *dtrace_stream;
192 	struct pci_dev *smn_dev;
193 	struct acp_dsp_stream *probe_stream;
194 };
195 
196 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
197 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
198 
199 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
200 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
201 			  unsigned int dest_addr, int dsp_data_size);
202 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
203 			      unsigned int start_addr, unsigned int dest_addr,
204 			      unsigned int image_length);
205 
206 /* ACP device probe/remove */
207 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
208 int amd_sof_acp_remove(struct snd_sof_dev *sdev);
209 
210 /* DSP Loader callbacks */
211 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
212 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
213 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
214 
215 /* Block IO callbacks */
216 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
217 			u32 offset, void *src, size_t size);
218 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
219 		       u32 offset, void *dest, size_t size);
220 
221 /* IPC callbacks */
222 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
223 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
224 			 void *p, size_t sz);
225 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
226 			       struct snd_sof_pcm_stream *sps,
227 			       size_t posn_offset);
228 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
229 			 struct snd_sof_ipc_msg *msg);
230 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
231 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
232 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
233 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
234 
235 /* ACP - DSP  stream callbacks */
236 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
237 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
238 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
239 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
240 
241 /*
242  * DSP PCM Operations.
243  */
244 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
245 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
246 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
247 		      struct snd_pcm_hw_params *params,
248 		      struct snd_sof_platform_stream_params *platform_params);
249 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev,
250 				  struct snd_pcm_substream *substream);
251 
252 extern struct snd_sof_dsp_ops sof_acp_common_ops;
253 
254 extern struct snd_sof_dsp_ops sof_renoir_ops;
255 int sof_renoir_ops_init(struct snd_sof_dev *sdev);
256 extern struct snd_sof_dsp_ops sof_rembrandt_ops;
257 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
258 
259 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
260 /* Machine configuration */
261 int snd_amd_acp_find_config(struct pci_dev *pci);
262 
263 /* Trace */
264 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
265 		       struct sof_ipc_dma_trace_params_ext *dtrace_params);
266 int acp_sof_trace_release(struct snd_sof_dev *sdev);
267 
268 /* PM Callbacks */
269 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
270 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
271 
272 void amd_sof_ipc_dump(struct snd_sof_dev *sdev);
273 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
274 
275 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
276 {
277 	const struct sof_dev_desc *desc = pdata->desc;
278 
279 	return desc->chip_info;
280 }
281 
282 int acp_probes_register(struct snd_sof_dev *sdev);
283 void acp_probes_unregister(struct snd_sof_dev *sdev);
284 
285 #endif
286