1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include "../sof-priv.h" 15 16 #define ACP_MAX_STREAM 8 17 18 #define ACP_DSP_BAR 0 19 20 #define ACP_REG_POLL_INTERVAL 500 21 #define ACP_REG_POLL_TIMEOUT_US 2000 22 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 23 24 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 25 #define ACP_PGFSM_STATUS_MASK 0x03 26 #define ACP_POWERED_ON 0x00 27 #define ACP_ASSERT_RESET 0x01 28 #define ACP_RELEASE_RESET 0x00 29 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 30 31 #define ACP_DSP_INTR_EN_MASK 0x00000001 32 #define ACP_SRAM_PTE_OFFSET 0x02050000 33 #define PAGE_SIZE_4K_ENABLE 0x2 34 #define ACP_PAGE_SIZE 0x1000 35 #define ACP_DMA_CH_RUN 0x02 36 #define ACP_MAX_DESC_CNT 0x02 37 #define DSP_FW_RUN_ENABLE 0x01 38 #define ACP_SHA_RUN 0x01 39 #define ACP_SHA_RESET 0x02 40 #define ACP_DMA_CH_RST 0x01 41 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 42 #define ACP_ATU_CACHE_INVALID 0x01 43 #define ACP_MAX_DESC 128 44 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 45 46 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 47 #define ACP_SCRATCH_MEMORY_ADDRESS 0x02050000 48 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 49 #define ACP_IRAM_BASE_ADDRESS 0x000000 50 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 51 #define ACP_DRAM_PAGE_COUNT 128 52 53 #define ACP_DSP_TO_HOST_IRQ 0x04 54 55 #define HOST_BRIDGE_CZN 0x1630 56 #define ACP_SHA_STAT 0x8000 57 #define ACP_PSP_TIMEOUT_COUNTER 5 58 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 59 #define MP0_C2PMSG_26_REG 0x03810570 60 #define MBOX_ACP_SHA_DMA_COMMAND 0x330000 61 #define MBOX_READY_MASK 0x80000000 62 #define MBOX_STATUS_MASK 0xFFFF 63 64 struct acp_atu_grp_pte { 65 u32 low; 66 u32 high; 67 }; 68 69 union dma_tx_cnt { 70 struct { 71 unsigned int count : 19; 72 unsigned int reserved : 12; 73 unsigned ioc : 1; 74 } bitfields, bits; 75 unsigned int u32_all; 76 signed int i32_all; 77 }; 78 79 struct dma_descriptor { 80 unsigned int src_addr; 81 unsigned int dest_addr; 82 union dma_tx_cnt tx_cnt; 83 unsigned int reserved; 84 }; 85 86 /* Scratch memory structure for communication b/w host and dsp */ 87 struct scratch_ipc_conf { 88 /* DSP mailbox */ 89 u8 sof_out_box[512]; 90 /* Host mailbox */ 91 u8 sof_in_box[512]; 92 /* Debug memory */ 93 u8 sof_debug_box[1024]; 94 /* Exception memory*/ 95 u8 sof_except_box[1024]; 96 /* Stream buffer */ 97 u8 sof_stream_box[1024]; 98 /* Trace buffer */ 99 u8 sof_trace_box[1024]; 100 /* Host msg flag */ 101 u32 sof_host_msg_write; 102 /* Host ack flag*/ 103 u32 sof_host_ack_write; 104 /* DSP msg flag */ 105 u32 sof_dsp_msg_write; 106 /* Dsp ack flag */ 107 u32 sof_dsp_ack_write; 108 }; 109 110 struct scratch_reg_conf { 111 struct scratch_ipc_conf info; 112 struct acp_atu_grp_pte grp1_pte[16]; 113 struct acp_atu_grp_pte grp2_pte[16]; 114 struct acp_atu_grp_pte grp3_pte[16]; 115 struct acp_atu_grp_pte grp4_pte[16]; 116 struct acp_atu_grp_pte grp5_pte[16]; 117 struct acp_atu_grp_pte grp6_pte[16]; 118 struct acp_atu_grp_pte grp7_pte[16]; 119 struct acp_atu_grp_pte grp8_pte[16]; 120 struct dma_descriptor dma_desc[64]; 121 unsigned int reg_offset[8]; 122 unsigned int buf_size[8]; 123 u8 acp_tx_fifo_buf[256]; 124 u8 acp_rx_fifo_buf[256]; 125 unsigned int reserve[]; 126 }; 127 128 struct acp_dsp_stream { 129 struct list_head list; 130 struct snd_sof_dev *sdev; 131 struct snd_pcm_substream *substream; 132 struct snd_dma_buffer *dmab; 133 int num_pages; 134 int stream_tag; 135 int active; 136 unsigned int reg_offset; 137 }; 138 139 /* Common device data struct for ACP devices */ 140 struct acp_dev_data { 141 struct snd_sof_dev *dev; 142 unsigned int fw_bin_size; 143 unsigned int fw_data_bin_size; 144 u32 fw_bin_page_count; 145 dma_addr_t sha_dma_addr; 146 u8 *bin_buf; 147 dma_addr_t dma_addr; 148 u8 *data_buf; 149 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 150 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 151 struct acp_dsp_stream *dtrace_stream; 152 struct pci_dev *smn_dev; 153 }; 154 155 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 156 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 157 158 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 159 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 160 unsigned int dest_addr, int dsp_data_size); 161 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 162 unsigned int start_addr, unsigned int dest_addr, 163 unsigned int image_length); 164 165 /* ACP device probe/remove */ 166 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 167 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 168 169 /* DSP Loader callbacks */ 170 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 171 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 172 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 173 174 /* Block IO callbacks */ 175 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 176 u32 offset, void *src, size_t size); 177 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 178 u32 offset, void *dest, size_t size); 179 180 /* IPC callbacks */ 181 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 182 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 183 void *p, size_t sz); 184 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 185 struct snd_sof_ipc_msg *msg); 186 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 187 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 188 int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 189 const struct sof_ipc_pcm_params_reply *reply); 190 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 191 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 192 193 /* ACP - DSP stream callbacks */ 194 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 195 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 196 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 197 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 198 199 /* 200 * DSP PCM Operations. 201 */ 202 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 203 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 204 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 205 struct snd_pcm_hw_params *params, struct sof_ipc_stream_params *ipc_params); 206 207 extern const struct snd_sof_dsp_ops sof_renoir_ops; 208 209 /* Machine configuration */ 210 int snd_amd_acp_find_config(struct pci_dev *pci); 211 212 /* Trace */ 213 int acp_sof_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 214 int acp_sof_trace_release(struct snd_sof_dev *sdev); 215 216 struct sof_amd_acp_desc { 217 unsigned int host_bridge_id; 218 }; 219 220 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 221 { 222 const struct sof_dev_desc *desc = pdata->desc; 223 224 return desc->chip_info; 225 } 226 #endif 227