1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include "../sof-priv.h" 15 16 #define ACP_MAX_STREAM 8 17 18 #define ACP_DSP_BAR 0 19 20 #define ACP_HW_SEM_RETRY_COUNT 10000 21 #define ACP_REG_POLL_INTERVAL 500 22 #define ACP_REG_POLL_TIMEOUT_US 2000 23 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 24 25 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 26 #define ACP_PGFSM_STATUS_MASK 0x03 27 #define ACP_POWERED_ON 0x00 28 #define ACP_ASSERT_RESET 0x01 29 #define ACP_RELEASE_RESET 0x00 30 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 31 32 #define ACP_DSP_INTR_EN_MASK 0x00000001 33 #define ACP_SRAM_PTE_OFFSET 0x02050000 34 #define PAGE_SIZE_4K_ENABLE 0x2 35 #define ACP_PAGE_SIZE 0x1000 36 #define ACP_DMA_CH_RUN 0x02 37 #define ACP_MAX_DESC_CNT 0x02 38 #define DSP_FW_RUN_ENABLE 0x01 39 #define ACP_SHA_RUN 0x01 40 #define ACP_SHA_RESET 0x02 41 #define ACP_DMA_CH_RST 0x01 42 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 43 #define ACP_ATU_CACHE_INVALID 0x01 44 #define ACP_MAX_DESC 128 45 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 46 47 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 48 #define ACP_SCRATCH_MEMORY_ADDRESS 0x02050000 49 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 50 #define ACP_IRAM_BASE_ADDRESS 0x000000 51 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 52 #define ACP_DRAM_PAGE_COUNT 128 53 54 #define ACP_DSP_TO_HOST_IRQ 0x04 55 56 #define HOST_BRIDGE_CZN 0x1630 57 #define ACP_SHA_STAT 0x8000 58 #define ACP_PSP_TIMEOUT_COUNTER 5 59 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 60 #define MP0_C2PMSG_114_REG 0x3810AC8 61 #define MP0_C2PMSG_73_REG 0x3810A24 62 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 63 #define MBOX_DELAY 1000 64 #define MBOX_READY_MASK 0x80000000 65 #define MBOX_STATUS_MASK 0xFFFF 66 67 struct acp_atu_grp_pte { 68 u32 low; 69 u32 high; 70 }; 71 72 union dma_tx_cnt { 73 struct { 74 unsigned int count : 19; 75 unsigned int reserved : 12; 76 unsigned ioc : 1; 77 } bitfields, bits; 78 unsigned int u32_all; 79 signed int i32_all; 80 }; 81 82 struct dma_descriptor { 83 unsigned int src_addr; 84 unsigned int dest_addr; 85 union dma_tx_cnt tx_cnt; 86 unsigned int reserved; 87 }; 88 89 /* Scratch memory structure for communication b/w host and dsp */ 90 struct scratch_ipc_conf { 91 /* DSP mailbox */ 92 u8 sof_out_box[512]; 93 /* Host mailbox */ 94 u8 sof_in_box[512]; 95 /* Debug memory */ 96 u8 sof_debug_box[1024]; 97 /* Exception memory*/ 98 u8 sof_except_box[1024]; 99 /* Stream buffer */ 100 u8 sof_stream_box[1024]; 101 /* Trace buffer */ 102 u8 sof_trace_box[1024]; 103 /* Host msg flag */ 104 u32 sof_host_msg_write; 105 /* Host ack flag*/ 106 u32 sof_host_ack_write; 107 /* DSP msg flag */ 108 u32 sof_dsp_msg_write; 109 /* Dsp ack flag */ 110 u32 sof_dsp_ack_write; 111 }; 112 113 struct scratch_reg_conf { 114 struct scratch_ipc_conf info; 115 struct acp_atu_grp_pte grp1_pte[16]; 116 struct acp_atu_grp_pte grp2_pte[16]; 117 struct acp_atu_grp_pte grp3_pte[16]; 118 struct acp_atu_grp_pte grp4_pte[16]; 119 struct acp_atu_grp_pte grp5_pte[16]; 120 struct acp_atu_grp_pte grp6_pte[16]; 121 struct acp_atu_grp_pte grp7_pte[16]; 122 struct acp_atu_grp_pte grp8_pte[16]; 123 struct dma_descriptor dma_desc[64]; 124 unsigned int reg_offset[8]; 125 unsigned int buf_size[8]; 126 u8 acp_tx_fifo_buf[256]; 127 u8 acp_rx_fifo_buf[256]; 128 unsigned int reserve[]; 129 }; 130 131 struct acp_dsp_stream { 132 struct list_head list; 133 struct snd_sof_dev *sdev; 134 struct snd_pcm_substream *substream; 135 struct snd_dma_buffer *dmab; 136 int num_pages; 137 int stream_tag; 138 int active; 139 unsigned int reg_offset; 140 }; 141 142 /* Common device data struct for ACP devices */ 143 struct acp_dev_data { 144 struct snd_sof_dev *dev; 145 unsigned int fw_bin_size; 146 unsigned int fw_data_bin_size; 147 u32 fw_bin_page_count; 148 dma_addr_t sha_dma_addr; 149 u8 *bin_buf; 150 dma_addr_t dma_addr; 151 u8 *data_buf; 152 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 153 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 154 struct acp_dsp_stream *dtrace_stream; 155 struct pci_dev *smn_dev; 156 }; 157 158 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 159 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 160 161 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 162 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 163 unsigned int dest_addr, int dsp_data_size); 164 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 165 unsigned int start_addr, unsigned int dest_addr, 166 unsigned int image_length); 167 168 /* ACP device probe/remove */ 169 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 170 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 171 172 /* DSP Loader callbacks */ 173 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 174 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 175 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 176 177 /* Block IO callbacks */ 178 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 179 u32 offset, void *src, size_t size); 180 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 181 u32 offset, void *dest, size_t size); 182 183 /* IPC callbacks */ 184 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 185 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 186 void *p, size_t sz); 187 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 188 struct snd_sof_ipc_msg *msg); 189 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 190 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 191 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 192 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 193 194 /* ACP - DSP stream callbacks */ 195 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 196 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 197 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 198 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 199 200 /* 201 * DSP PCM Operations. 202 */ 203 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 204 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 205 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 206 struct snd_pcm_hw_params *params, 207 struct snd_sof_platform_stream_params *platform_params); 208 209 extern struct snd_sof_dsp_ops sof_renoir_ops; 210 211 /* Machine configuration */ 212 int snd_amd_acp_find_config(struct pci_dev *pci); 213 214 /* Trace */ 215 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 216 struct sof_ipc_dma_trace_params_ext *dtrace_params); 217 int acp_sof_trace_release(struct snd_sof_dev *sdev); 218 219 struct sof_amd_acp_desc { 220 unsigned int host_bridge_id; 221 }; 222 223 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 224 { 225 const struct sof_dev_desc *desc = pdata->desc; 226 227 return desc->chip_info; 228 } 229 #endif 230