1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include "../sof-priv.h" 15 #include "../sof-audio.h" 16 17 #define ACP_MAX_STREAM 8 18 19 #define ACP_DSP_BAR 0 20 21 #define ACP_HW_SEM_RETRY_COUNT 10000 22 #define ACP_REG_POLL_INTERVAL 500 23 #define ACP_REG_POLL_TIMEOUT_US 2000 24 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 25 26 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 27 #define ACP_PGFSM_STATUS_MASK 0x03 28 #define ACP_POWERED_ON 0x00 29 #define ACP_ASSERT_RESET 0x01 30 #define ACP_RELEASE_RESET 0x00 31 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 32 33 #define ACP_DSP_INTR_EN_MASK 0x00000001 34 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 35 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 36 #define PAGE_SIZE_4K_ENABLE 0x2 37 #define ACP_PAGE_SIZE 0x1000 38 #define ACP_DMA_CH_RUN 0x02 39 #define ACP_MAX_DESC_CNT 0x02 40 #define DSP_FW_RUN_ENABLE 0x01 41 #define ACP_SHA_RUN 0x01 42 #define ACP_SHA_RESET 0x02 43 #define ACP_DMA_CH_RST 0x01 44 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 45 #define ACP_ATU_CACHE_INVALID 0x01 46 #define ACP_MAX_DESC 128 47 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 48 49 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 50 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 51 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 52 #define ACP_IRAM_BASE_ADDRESS 0x000000 53 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 54 #define ACP_DRAM_PAGE_COUNT 128 55 56 #define ACP_DSP_TO_HOST_IRQ 0x04 57 58 #define ACP_RN_PCI_ID 0x01 59 #define ACP_RMB_PCI_ID 0x6F 60 61 #define HOST_BRIDGE_CZN 0x1630 62 #define HOST_BRIDGE_RMB 0x14B5 63 #define ACP_SHA_STAT 0x8000 64 #define ACP_PSP_TIMEOUT_COUNTER 5 65 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 66 #define MP0_C2PMSG_114_REG 0x3810AC8 67 #define MP0_C2PMSG_73_REG 0x3810A24 68 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 69 #define MBOX_DELAY 1000 70 #define MBOX_READY_MASK 0x80000000 71 #define MBOX_STATUS_MASK 0xFFFF 72 73 #define BOX_SIZE_512 0x200 74 #define BOX_SIZE_1024 0x400 75 76 #define EXCEPT_MAX_HDR_SIZE 0x400 77 #define AMD_STACK_DUMP_SIZE 32 78 79 #define SRAM1_SIZE 0x13A000 80 81 enum clock_source { 82 ACP_CLOCK_96M = 0, 83 ACP_CLOCK_48M, 84 ACP_CLOCK_24M, 85 ACP_CLOCK_ACLK, 86 ACP_CLOCK_MCLK, 87 }; 88 89 struct acp_atu_grp_pte { 90 u32 low; 91 u32 high; 92 }; 93 94 union dma_tx_cnt { 95 struct { 96 unsigned int count : 19; 97 unsigned int reserved : 12; 98 unsigned ioc : 1; 99 } bitfields, bits; 100 unsigned int u32_all; 101 signed int i32_all; 102 }; 103 104 struct dma_descriptor { 105 unsigned int src_addr; 106 unsigned int dest_addr; 107 union dma_tx_cnt tx_cnt; 108 unsigned int reserved; 109 }; 110 111 /* Scratch memory structure for communication b/w host and dsp */ 112 struct scratch_ipc_conf { 113 /* Debug memory */ 114 u8 sof_debug_box[1024]; 115 /* Exception memory*/ 116 u8 sof_except_box[1024]; 117 /* Stream buffer */ 118 u8 sof_stream_box[1024]; 119 /* Trace buffer */ 120 u8 sof_trace_box[1024]; 121 /* Host msg flag */ 122 u32 sof_host_msg_write; 123 /* Host ack flag*/ 124 u32 sof_host_ack_write; 125 /* DSP msg flag */ 126 u32 sof_dsp_msg_write; 127 /* Dsp ack flag */ 128 u32 sof_dsp_ack_write; 129 }; 130 131 struct scratch_reg_conf { 132 struct scratch_ipc_conf info; 133 struct acp_atu_grp_pte grp1_pte[16]; 134 struct acp_atu_grp_pte grp2_pte[16]; 135 struct acp_atu_grp_pte grp3_pte[16]; 136 struct acp_atu_grp_pte grp4_pte[16]; 137 struct acp_atu_grp_pte grp5_pte[16]; 138 struct acp_atu_grp_pte grp6_pte[16]; 139 struct acp_atu_grp_pte grp7_pte[16]; 140 struct acp_atu_grp_pte grp8_pte[16]; 141 struct dma_descriptor dma_desc[64]; 142 unsigned int reg_offset[8]; 143 unsigned int buf_size[8]; 144 u8 acp_tx_fifo_buf[256]; 145 u8 acp_rx_fifo_buf[256]; 146 unsigned int reserve[]; 147 }; 148 149 struct acp_dsp_stream { 150 struct list_head list; 151 struct snd_sof_dev *sdev; 152 struct snd_pcm_substream *substream; 153 struct snd_dma_buffer *dmab; 154 int num_pages; 155 int stream_tag; 156 int active; 157 unsigned int reg_offset; 158 size_t posn_offset; 159 }; 160 161 struct sof_amd_acp_desc { 162 unsigned int rev; 163 unsigned int host_bridge_id; 164 u32 pgfsm_base; 165 u32 ext_intr_stat; 166 u32 dsp_intr_base; 167 u32 sram_pte_offset; 168 u32 hw_semaphore_offset; 169 u32 acp_clkmux_sel; 170 u32 fusion_dsp_offset; 171 }; 172 173 /* Common device data struct for ACP devices */ 174 struct acp_dev_data { 175 struct snd_sof_dev *dev; 176 /* DMIC device */ 177 struct platform_device *dmic_dev; 178 unsigned int fw_bin_size; 179 unsigned int fw_data_bin_size; 180 u32 fw_bin_page_count; 181 dma_addr_t sha_dma_addr; 182 u8 *bin_buf; 183 dma_addr_t dma_addr; 184 u8 *data_buf; 185 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 186 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 187 struct acp_dsp_stream *dtrace_stream; 188 struct pci_dev *smn_dev; 189 }; 190 191 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 192 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 193 194 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 195 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 196 unsigned int dest_addr, int dsp_data_size); 197 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 198 unsigned int start_addr, unsigned int dest_addr, 199 unsigned int image_length); 200 201 /* ACP device probe/remove */ 202 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 203 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 204 205 /* DSP Loader callbacks */ 206 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 207 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 208 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 209 210 /* Block IO callbacks */ 211 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 212 u32 offset, void *src, size_t size); 213 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 214 u32 offset, void *dest, size_t size); 215 216 /* IPC callbacks */ 217 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 218 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 219 void *p, size_t sz); 220 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 221 struct snd_sof_pcm_stream *sps, 222 size_t posn_offset); 223 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 224 struct snd_sof_ipc_msg *msg); 225 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 226 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 227 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 228 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 229 230 /* ACP - DSP stream callbacks */ 231 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 232 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 233 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 234 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 235 236 /* 237 * DSP PCM Operations. 238 */ 239 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 240 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 241 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 242 struct snd_pcm_hw_params *params, 243 struct snd_sof_platform_stream_params *platform_params); 244 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 245 struct snd_pcm_substream *substream); 246 247 extern struct snd_sof_dsp_ops sof_acp_common_ops; 248 249 extern struct snd_sof_dsp_ops sof_renoir_ops; 250 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 251 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 252 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 253 254 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 255 /* Machine configuration */ 256 int snd_amd_acp_find_config(struct pci_dev *pci); 257 258 /* Trace */ 259 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 260 struct sof_ipc_dma_trace_params_ext *dtrace_params); 261 int acp_sof_trace_release(struct snd_sof_dev *sdev); 262 263 /* PM Callbacks */ 264 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 265 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 266 267 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 268 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 269 270 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 271 { 272 const struct sof_dev_desc *desc = pdata->desc; 273 274 return desc->chip_info; 275 } 276 #endif 277