1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include "../ops.h" 20 #include "acp.h" 21 #include "acp-dsp-offset.h" 22 23 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data) 24 { 25 pci_write_config_dword(dev, 0x60, smn_addr); 26 pci_write_config_dword(dev, 0x64, data); 27 28 return 0; 29 } 30 31 static int smn_read(struct pci_dev *dev, u32 smn_addr, u32 *data) 32 { 33 pci_write_config_dword(dev, 0x60, smn_addr); 34 pci_read_config_dword(dev, 0x64, data); 35 36 return 0; 37 } 38 39 static void init_dma_descriptor(struct acp_dev_data *adata) 40 { 41 struct snd_sof_dev *sdev = adata->dev; 42 unsigned int addr; 43 44 addr = ACP_SRAM_PTE_OFFSET + offsetof(struct scratch_reg_conf, dma_desc); 45 46 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr); 47 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT); 48 } 49 50 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 51 struct dma_descriptor *dscr_info) 52 { 53 struct snd_sof_dev *sdev = adata->dev; 54 unsigned int offset; 55 56 offset = ACP_SCRATCH_REG_0 + offsetof(struct scratch_reg_conf, dma_desc) + 57 idx * sizeof(struct dma_descriptor); 58 59 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 60 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 61 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 62 } 63 64 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 65 unsigned int idx, unsigned int dscr_count) 66 { 67 struct snd_sof_dev *sdev = adata->dev; 68 unsigned int val, status; 69 int ret; 70 71 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), 72 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 73 74 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val, 75 val & (1 << ch), ACP_REG_POLL_INTERVAL, 76 ACP_REG_POLL_TIMEOUT_US); 77 if (ret < 0) { 78 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS); 79 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32)); 80 81 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 82 return ret; 83 } 84 85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0); 86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count); 87 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx); 88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0); 89 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 90 91 return ret; 92 } 93 94 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 95 unsigned int dscr_count, struct dma_descriptor *dscr_info) 96 { 97 struct snd_sof_dev *sdev = adata->dev; 98 int ret; 99 u16 dscr; 100 101 if (!dscr_info || !dscr_count) 102 return -EINVAL; 103 104 for (dscr = 0; dscr < dscr_count; dscr++) 105 configure_dma_descriptor(adata, dscr, dscr_info++); 106 107 ret = config_dma_channel(adata, ch, 0, dscr_count); 108 if (ret < 0) 109 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 110 111 return ret; 112 } 113 114 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 115 unsigned int dest_addr, int dsp_data_size) 116 { 117 struct snd_sof_dev *sdev = adata->dev; 118 unsigned int desc_count, index; 119 int ret; 120 121 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 122 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 123 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 124 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 125 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 126 if (dsp_data_size < ACP_PAGE_SIZE) 127 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 128 } 129 130 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 131 if (ret) 132 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 133 134 /* Clear descriptor array */ 135 for (index = 0; index < desc_count; index++) 136 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 137 138 return ret; 139 } 140 141 static int psp_fw_validate(struct acp_dev_data *adata) 142 { 143 struct snd_sof_dev *sdev = adata->dev; 144 int timeout; 145 u32 data; 146 147 smn_write(adata->smn_dev, MP0_C2PMSG_26_REG, MBOX_ACP_SHA_DMA_COMMAND); 148 149 for (timeout = ACP_PSP_TIMEOUT_COUNTER; timeout > 0; timeout--) { 150 msleep(20); 151 smn_read(adata->smn_dev, MP0_C2PMSG_26_REG, &data); 152 if (data & MBOX_READY_MASK) 153 return 0; 154 } 155 156 dev_err(sdev->dev, "FW validation timedout: status %x\n", data & MBOX_STATUS_MASK); 157 return -ETIMEDOUT; 158 } 159 160 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 161 unsigned int start_addr, unsigned int dest_addr, 162 unsigned int image_length) 163 { 164 struct snd_sof_dev *sdev = adata->dev; 165 unsigned int tx_count, fw_qualifier, val; 166 int ret; 167 168 if (!image_addr) { 169 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 170 return -EINVAL; 171 } 172 173 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 174 if (val & ACP_SHA_RUN) { 175 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 176 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 177 val, val & ACP_SHA_RESET, 178 ACP_REG_POLL_INTERVAL, 179 ACP_REG_POLL_TIMEOUT_US); 180 if (ret < 0) { 181 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 182 return ret; 183 } 184 } 185 186 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 187 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 188 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 189 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 190 191 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 192 tx_count, tx_count == image_length, 193 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 194 if (ret < 0) { 195 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 196 return ret; 197 } 198 199 ret = psp_fw_validate(adata); 200 if (ret) 201 return ret; 202 203 fw_qualifier = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER); 204 if (!(fw_qualifier & DSP_FW_RUN_ENABLE)) { 205 dev_err(sdev->dev, "PSP validation failed\n"); 206 return -EINVAL; 207 } 208 209 return 0; 210 } 211 212 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 213 { 214 struct snd_sof_dev *sdev = adata->dev; 215 unsigned int val; 216 int ret = 0; 217 218 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 219 if (val & ACP_DMA_CH_RUN) { 220 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val, 221 ACP_REG_POLL_INTERVAL, 222 ACP_DMA_COMPLETE_TIMEOUT_US); 223 if (ret < 0) 224 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 225 } 226 227 return ret; 228 } 229 230 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 231 { 232 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 233 int i, j; 234 235 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 236 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 237 } 238 239 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 240 { 241 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 242 int i, j; 243 244 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 245 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 246 } 247 248 static int acp_memory_init(struct snd_sof_dev *sdev) 249 { 250 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 251 252 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_CNTL, 253 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 254 init_dma_descriptor(adata); 255 256 return 0; 257 } 258 259 static irqreturn_t acp_irq_thread(int irq, void *context) 260 { 261 struct snd_sof_dev *sdev = context; 262 unsigned int val, count = ACP_HW_SEM_RETRY_COUNT; 263 264 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_EXTERNAL_INTR_STAT); 265 if (val & ACP_SHA_STAT) { 266 /* Clear SHA interrupt raised by PSP */ 267 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_EXTERNAL_INTR_STAT, val); 268 return IRQ_HANDLED; 269 } 270 271 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT); 272 if (val & ACP_DSP_TO_HOST_IRQ) { 273 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0)) { 274 /* Wait until acquired HW Semaphore lock or timeout */ 275 count--; 276 if (!count) { 277 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 278 return IRQ_NONE; 279 } 280 } 281 282 sof_ops(sdev)->irq_thread(irq, sdev); 283 val |= ACP_DSP_TO_HOST_IRQ; 284 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT, val); 285 286 /* Unlock or Release HW Semaphore */ 287 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0, 0x0); 288 289 return IRQ_HANDLED; 290 } 291 292 return IRQ_NONE; 293 }; 294 295 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 296 { 297 struct snd_sof_dev *sdev = dev_id; 298 unsigned int val; 299 300 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT); 301 if (val) 302 return IRQ_WAKE_THREAD; 303 304 return IRQ_NONE; 305 } 306 307 static int acp_power_on(struct snd_sof_dev *sdev) 308 { 309 unsigned int val; 310 int ret; 311 312 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_PGFSM_STATUS); 313 314 if (val == ACP_POWERED_ON) 315 return 0; 316 317 if (val & ACP_PGFSM_STATUS_MASK) 318 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_PGFSM_CONTROL, 319 ACP_PGFSM_CNTL_POWER_ON_MASK); 320 321 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_PGFSM_STATUS, val, !val, 322 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 323 if (ret < 0) 324 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 325 326 return ret; 327 } 328 329 static int acp_reset(struct snd_sof_dev *sdev) 330 { 331 unsigned int val; 332 int ret; 333 334 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 335 336 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 337 val & ACP_SOFT_RESET_DONE_MASK, 338 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 339 if (ret < 0) { 340 dev_err(sdev->dev, "timeout asserting reset\n"); 341 return ret; 342 } 343 344 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 345 346 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 347 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 348 if (ret < 0) 349 dev_err(sdev->dev, "timeout in releasing reset\n"); 350 351 return ret; 352 } 353 354 static int acp_init(struct snd_sof_dev *sdev) 355 { 356 int ret; 357 358 /* power on */ 359 ret = acp_power_on(sdev); 360 if (ret) { 361 dev_err(sdev->dev, "ACP power on failed\n"); 362 return ret; 363 } 364 /* Reset */ 365 return acp_reset(sdev); 366 } 367 368 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 369 { 370 struct pci_dev *pci = to_pci_dev(sdev->dev); 371 struct acp_dev_data *adata; 372 const struct sof_amd_acp_desc *chip; 373 unsigned int addr; 374 int ret; 375 376 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 377 GFP_KERNEL); 378 if (!adata) 379 return -ENOMEM; 380 381 adata->dev = sdev; 382 addr = pci_resource_start(pci, ACP_DSP_BAR); 383 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 384 if (!sdev->bar[ACP_DSP_BAR]) { 385 dev_err(sdev->dev, "ioremap error\n"); 386 return -ENXIO; 387 } 388 389 pci_set_master(pci); 390 391 sdev->pdata->hw_pdata = adata; 392 393 chip = get_chip_info(sdev->pdata); 394 if (!chip) { 395 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 396 return -EIO; 397 } 398 399 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL); 400 if (!adata->smn_dev) { 401 dev_err(sdev->dev, "Failed to get host bridge device\n"); 402 return -ENODEV; 403 } 404 405 sdev->ipc_irq = pci->irq; 406 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 407 IRQF_SHARED, "AudioDSP", sdev); 408 if (ret < 0) { 409 dev_err(sdev->dev, "failed to register IRQ %d\n", 410 sdev->ipc_irq); 411 pci_dev_put(adata->smn_dev); 412 return ret; 413 } 414 415 ret = acp_init(sdev); 416 if (ret < 0) { 417 free_irq(sdev->ipc_irq, sdev); 418 pci_dev_put(adata->smn_dev); 419 return ret; 420 } 421 422 acp_memory_init(sdev); 423 424 acp_dsp_stream_init(sdev); 425 426 return 0; 427 } 428 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON); 429 430 int amd_sof_acp_remove(struct snd_sof_dev *sdev) 431 { 432 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 433 434 if (adata->smn_dev) 435 pci_dev_put(adata->smn_dev); 436 437 if (sdev->ipc_irq) 438 free_irq(sdev->ipc_irq, sdev); 439 440 return acp_reset(sdev); 441 } 442 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); 443 444 MODULE_DESCRIPTION("AMD ACP sof driver"); 445 MODULE_LICENSE("Dual BSD/GPL"); 446