1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 //
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10
11 /*
12 * Hardware interface for generic AMD ACP processor
13 */
14
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18
19 #include "../ops.h"
20 #include "acp.h"
21 #include "acp-dsp-offset.h"
22
23 #define SECURED_FIRMWARE 1
24
25 static bool enable_fw_debug;
26 module_param(enable_fw_debug, bool, 0444);
27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
28
29 const struct dmi_system_id acp_sof_quirk_table[] = {
30 {
31 /* Steam Deck OLED device */
32 .matches = {
33 DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
34 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
35 },
36 .driver_data = (void *)SECURED_FIRMWARE,
37 },
38 {}
39 };
40 EXPORT_SYMBOL_GPL(acp_sof_quirk_table);
41
smn_write(struct pci_dev * dev,u32 smn_addr,u32 data)42 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
43 {
44 pci_write_config_dword(dev, 0x60, smn_addr);
45 pci_write_config_dword(dev, 0x64, data);
46
47 return 0;
48 }
49
smn_read(struct pci_dev * dev,u32 smn_addr)50 static int smn_read(struct pci_dev *dev, u32 smn_addr)
51 {
52 u32 data = 0;
53
54 pci_write_config_dword(dev, 0x60, smn_addr);
55 pci_read_config_dword(dev, 0x64, &data);
56
57 return data;
58 }
59
init_dma_descriptor(struct acp_dev_data * adata)60 static void init_dma_descriptor(struct acp_dev_data *adata)
61 {
62 struct snd_sof_dev *sdev = adata->dev;
63 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
64 unsigned int addr;
65
66 addr = desc->sram_pte_offset + sdev->debug_box.offset +
67 offsetof(struct scratch_reg_conf, dma_desc);
68
69 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
71 }
72
configure_dma_descriptor(struct acp_dev_data * adata,unsigned short idx,struct dma_descriptor * dscr_info)73 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
74 struct dma_descriptor *dscr_info)
75 {
76 struct snd_sof_dev *sdev = adata->dev;
77 unsigned int offset;
78
79 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
80 offsetof(struct scratch_reg_conf, dma_desc) +
81 idx * sizeof(struct dma_descriptor);
82
83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
86 }
87
config_dma_channel(struct acp_dev_data * adata,unsigned int ch,unsigned int idx,unsigned int dscr_count)88 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
89 unsigned int idx, unsigned int dscr_count)
90 {
91 struct snd_sof_dev *sdev = adata->dev;
92 unsigned int val, status;
93 int ret;
94
95 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
96 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
97
98 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
99 val & (1 << ch), ACP_REG_POLL_INTERVAL,
100 ACP_REG_POLL_TIMEOUT_US);
101 if (ret < 0) {
102 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
103 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
104
105 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
106 return ret;
107 }
108
109 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
110 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
111 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
114
115 return ret;
116 }
117
acpbus_dma_start(struct acp_dev_data * adata,unsigned int ch,unsigned int dscr_count,struct dma_descriptor * dscr_info)118 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
119 unsigned int dscr_count, struct dma_descriptor *dscr_info)
120 {
121 struct snd_sof_dev *sdev = adata->dev;
122 int ret;
123 u16 dscr;
124
125 if (!dscr_info || !dscr_count)
126 return -EINVAL;
127
128 for (dscr = 0; dscr < dscr_count; dscr++)
129 configure_dma_descriptor(adata, dscr, dscr_info++);
130
131 ret = config_dma_channel(adata, ch, 0, dscr_count);
132 if (ret < 0)
133 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
134
135 return ret;
136 }
137
configure_and_run_dma(struct acp_dev_data * adata,unsigned int src_addr,unsigned int dest_addr,int dsp_data_size)138 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
139 unsigned int dest_addr, int dsp_data_size)
140 {
141 struct snd_sof_dev *sdev = adata->dev;
142 unsigned int desc_count, index;
143 int ret;
144
145 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
146 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
147 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
148 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
149 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
150 if (dsp_data_size < ACP_PAGE_SIZE)
151 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
152 }
153
154 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
155 if (ret)
156 dev_err(sdev->dev, "acpbus_dma_start failed\n");
157
158 /* Clear descriptor array */
159 for (index = 0; index < desc_count; index++)
160 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
161
162 return ret;
163 }
164
165 /*
166 * psp_mbox_ready- function to poll ready bit of psp mbox
167 * @adata: acp device data
168 * @ack: bool variable to check ready bit status or psp ack
169 */
170
psp_mbox_ready(struct acp_dev_data * adata,bool ack)171 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
172 {
173 struct snd_sof_dev *sdev = adata->dev;
174 int ret;
175 u32 data;
176
177 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US,
178 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG);
179 if (!ret)
180 return 0;
181
182 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
183
184 if (ack)
185 return -ETIMEDOUT;
186
187 return -EBUSY;
188 }
189
190 /*
191 * psp_send_cmd - function to send psp command over mbox
192 * @adata: acp device data
193 * @cmd: non zero integer value for command type
194 */
195
psp_send_cmd(struct acp_dev_data * adata,int cmd)196 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
197 {
198 struct snd_sof_dev *sdev = adata->dev;
199 int ret;
200 u32 data;
201
202 if (!cmd)
203 return -EINVAL;
204
205 /* Get a non-zero Doorbell value from PSP */
206 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false,
207 adata->smn_dev, MP0_C2PMSG_73_REG);
208
209 if (ret) {
210 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
211 return ret;
212 }
213
214 /* Check if PSP is ready for new command */
215 ret = psp_mbox_ready(adata, 0);
216 if (ret)
217 return ret;
218
219 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);
220
221 /* Ring the Doorbell for PSP */
222 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);
223
224 /* Check MBOX ready as PSP ack */
225 ret = psp_mbox_ready(adata, 1);
226
227 return ret;
228 }
229
configure_and_run_sha_dma(struct acp_dev_data * adata,void * image_addr,unsigned int start_addr,unsigned int dest_addr,unsigned int image_length)230 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
231 unsigned int start_addr, unsigned int dest_addr,
232 unsigned int image_length)
233 {
234 struct snd_sof_dev *sdev = adata->dev;
235 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
236 unsigned int tx_count, fw_qualifier, val;
237 int ret;
238
239 if (!image_addr) {
240 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
241 return -EINVAL;
242 }
243
244 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
245 if (val & ACP_SHA_RUN) {
246 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
247 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
248 val, val & ACP_SHA_RESET,
249 ACP_REG_POLL_INTERVAL,
250 ACP_REG_POLL_TIMEOUT_US);
251 if (ret < 0) {
252 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
253 return ret;
254 }
255 }
256
257 if (adata->signed_fw_image)
258 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
259
260 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
262 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
264
265 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
266 tx_count, tx_count == image_length,
267 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
268 if (ret < 0) {
269 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
270 return ret;
271 }
272
273 /* psp_send_cmd only required for renoir platform (rev - 3) */
274 if (desc->rev == 3) {
275 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
276 if (ret)
277 return ret;
278 }
279
280 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
281 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
282 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
283 if (ret < 0) {
284 dev_err(sdev->dev, "PSP validation failed\n");
285 return ret;
286 }
287
288 return 0;
289 }
290
acp_dma_status(struct acp_dev_data * adata,unsigned char ch)291 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
292 {
293 struct snd_sof_dev *sdev = adata->dev;
294 unsigned int val;
295 int ret = 0;
296
297 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
298 if (val & ACP_DMA_CH_RUN) {
299 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,
300 ACP_REG_POLL_INTERVAL,
301 ACP_DMA_COMPLETE_TIMEOUT_US);
302 if (ret < 0)
303 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
304 }
305
306 return ret;
307 }
308
memcpy_from_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * dst,size_t bytes)309 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
310 {
311 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
312 int i, j;
313
314 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
315 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
316 }
317
memcpy_to_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * src,size_t bytes)318 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
319 {
320 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
321 int i, j;
322
323 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
324 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
325 }
326
acp_memory_init(struct snd_sof_dev * sdev)327 static int acp_memory_init(struct snd_sof_dev *sdev)
328 {
329 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
330 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
331
332 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
333 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
334 init_dma_descriptor(adata);
335
336 return 0;
337 }
338
acp_irq_thread(int irq,void * context)339 static irqreturn_t acp_irq_thread(int irq, void *context)
340 {
341 struct snd_sof_dev *sdev = context;
342 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
343 unsigned int count = ACP_HW_SEM_RETRY_COUNT;
344
345 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
346 /* Wait until acquired HW Semaphore lock or timeout */
347 count--;
348 if (!count) {
349 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
350 return IRQ_NONE;
351 }
352 }
353
354 sof_ops(sdev)->irq_thread(irq, sdev);
355 /* Unlock or Release HW Semaphore */
356 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
357
358 return IRQ_HANDLED;
359 };
360
acp_irq_handler(int irq,void * dev_id)361 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
362 {
363 struct snd_sof_dev *sdev = dev_id;
364 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
365 unsigned int base = desc->dsp_intr_base;
366 unsigned int val;
367
368 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
369 if (val & ACP_DSP_TO_HOST_IRQ) {
370 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
371 ACP_DSP_TO_HOST_IRQ);
372 return IRQ_WAKE_THREAD;
373 }
374
375 return IRQ_NONE;
376 }
377
acp_power_on(struct snd_sof_dev * sdev)378 static int acp_power_on(struct snd_sof_dev *sdev)
379 {
380 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
381 unsigned int base = desc->pgfsm_base;
382 unsigned int val;
383 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;
384 int ret;
385
386 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
387
388 if (val == ACP_POWERED_ON)
389 return 0;
390
391 switch (desc->rev) {
392 case 3:
393 case 5:
394 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
395 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
396 break;
397 case 6:
398 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
399 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 if (val & acp_pgfsm_status_mask)
406 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
407 acp_pgfsm_cntl_mask);
408
409 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
410 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
411 if (ret < 0)
412 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
413
414 return ret;
415 }
416
acp_reset(struct snd_sof_dev * sdev)417 static int acp_reset(struct snd_sof_dev *sdev)
418 {
419 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
420 unsigned int val;
421 int ret;
422
423 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
424
425 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
426 val & ACP_SOFT_RESET_DONE_MASK,
427 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
428 if (ret < 0) {
429 dev_err(sdev->dev, "timeout asserting reset\n");
430 return ret;
431 }
432
433 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
434
435 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
436 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
437 if (ret < 0)
438 dev_err(sdev->dev, "timeout in releasing reset\n");
439
440 if (desc->acp_clkmux_sel)
441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
442
443 if (desc->ext_intr_enb)
444 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
445
446 return ret;
447 }
448
acp_init(struct snd_sof_dev * sdev)449 static int acp_init(struct snd_sof_dev *sdev)
450 {
451 int ret;
452
453 /* power on */
454 ret = acp_power_on(sdev);
455 if (ret) {
456 dev_err(sdev->dev, "ACP power on failed\n");
457 return ret;
458 }
459
460 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
461 /* Reset */
462 return acp_reset(sdev);
463 }
464
amd_sof_acp_suspend(struct snd_sof_dev * sdev,u32 target_state)465 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
466 {
467 int ret;
468
469 ret = acp_reset(sdev);
470 if (ret) {
471 dev_err(sdev->dev, "ACP Reset failed\n");
472 return ret;
473 }
474
475 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
476
477 return 0;
478 }
479 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
480
amd_sof_acp_resume(struct snd_sof_dev * sdev)481 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
482 {
483 int ret;
484
485 ret = acp_init(sdev);
486 if (ret) {
487 dev_err(sdev->dev, "ACP Init failed\n");
488 return ret;
489 }
490 return acp_memory_init(sdev);
491 }
492 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON);
493
amd_sof_acp_probe(struct snd_sof_dev * sdev)494 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
495 {
496 struct pci_dev *pci = to_pci_dev(sdev->dev);
497 struct snd_sof_pdata *plat_data = sdev->pdata;
498 struct acp_dev_data *adata;
499 const struct sof_amd_acp_desc *chip;
500 const struct dmi_system_id *dmi_id;
501 unsigned int addr;
502 int ret;
503
504 chip = get_chip_info(sdev->pdata);
505 if (!chip) {
506 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
507 return -EIO;
508 }
509 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
510 GFP_KERNEL);
511 if (!adata)
512 return -ENOMEM;
513
514 adata->dev = sdev;
515 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
516 PLATFORM_DEVID_NONE, NULL, 0);
517 if (IS_ERR(adata->dmic_dev)) {
518 dev_err(sdev->dev, "failed to register platform for dmic codec\n");
519 return PTR_ERR(adata->dmic_dev);
520 }
521 addr = pci_resource_start(pci, ACP_DSP_BAR);
522 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
523 if (!sdev->bar[ACP_DSP_BAR]) {
524 dev_err(sdev->dev, "ioremap error\n");
525 ret = -ENXIO;
526 goto unregister_dev;
527 }
528
529 pci_set_master(pci);
530
531 sdev->pdata->hw_pdata = adata;
532 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);
533 if (!adata->smn_dev) {
534 dev_err(sdev->dev, "Failed to get host bridge device\n");
535 ret = -ENODEV;
536 goto unregister_dev;
537 }
538
539 ret = acp_init(sdev);
540 if (ret < 0)
541 goto free_smn_dev;
542
543 sdev->ipc_irq = pci->irq;
544 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
545 IRQF_SHARED, "AudioDSP", sdev);
546 if (ret < 0) {
547 dev_err(sdev->dev, "failed to register IRQ %d\n",
548 sdev->ipc_irq);
549 goto free_smn_dev;
550 }
551
552 sdev->dsp_box.offset = 0;
553 sdev->dsp_box.size = BOX_SIZE_512;
554
555 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
556 sdev->host_box.size = BOX_SIZE_512;
557
558 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
559 sdev->debug_box.size = BOX_SIZE_1024;
560
561 adata->signed_fw_image = false;
562 dmi_id = dmi_first_match(acp_sof_quirk_table);
563 if (dmi_id && dmi_id->driver_data) {
564 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
565 "%s/sof-%s-code.bin",
566 plat_data->fw_filename_prefix,
567 chip->name);
568 if (!adata->fw_code_bin) {
569 ret = -ENOMEM;
570 goto free_ipc_irq;
571 }
572
573 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
574 "%s/sof-%s-data.bin",
575 plat_data->fw_filename_prefix,
576 chip->name);
577 if (!adata->fw_data_bin) {
578 ret = -ENOMEM;
579 goto free_ipc_irq;
580 }
581
582 adata->signed_fw_image = dmi_id->driver_data;
583 }
584
585 adata->enable_fw_debug = enable_fw_debug;
586 acp_memory_init(sdev);
587
588 acp_dsp_stream_init(sdev);
589
590 return 0;
591
592 free_ipc_irq:
593 free_irq(sdev->ipc_irq, sdev);
594 free_smn_dev:
595 pci_dev_put(adata->smn_dev);
596 unregister_dev:
597 platform_device_unregister(adata->dmic_dev);
598 return ret;
599 }
600 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);
601
amd_sof_acp_remove(struct snd_sof_dev * sdev)602 int amd_sof_acp_remove(struct snd_sof_dev *sdev)
603 {
604 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
605
606 if (adata->smn_dev)
607 pci_dev_put(adata->smn_dev);
608
609 if (sdev->ipc_irq)
610 free_irq(sdev->ipc_irq, sdev);
611
612 if (adata->dmic_dev)
613 platform_device_unregister(adata->dmic_dev);
614
615 return acp_reset(sdev);
616 }
617 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);
618
619 MODULE_DESCRIPTION("AMD ACP sof driver");
620 MODULE_LICENSE("Dual BSD/GPL");
621