1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/soc.h> 17 18 /* REGISTER OFFSET */ 19 #define SSICR 0x000 20 #define SSISR 0x004 21 #define SSIFCR 0x010 22 #define SSIFSR 0x014 23 #define SSIFTDR 0x018 24 #define SSIFRDR 0x01c 25 #define SSIOFR 0x020 26 #define SSISCR 0x024 27 28 /* SSI REGISTER BITS */ 29 #define SSICR_DWL(x) (((x) & 0x7) << 19) 30 #define SSICR_SWL(x) (((x) & 0x7) << 16) 31 32 #define SSICR_CKS BIT(30) 33 #define SSICR_TUIEN BIT(29) 34 #define SSICR_TOIEN BIT(28) 35 #define SSICR_RUIEN BIT(27) 36 #define SSICR_ROIEN BIT(26) 37 #define SSICR_MST BIT(14) 38 #define SSICR_BCKP BIT(13) 39 #define SSICR_LRCKP BIT(12) 40 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 41 #define SSICR_TEN BIT(1) 42 #define SSICR_REN BIT(0) 43 44 #define SSISR_TUIRQ BIT(29) 45 #define SSISR_TOIRQ BIT(28) 46 #define SSISR_RUIRQ BIT(27) 47 #define SSISR_ROIRQ BIT(26) 48 #define SSISR_IIRQ BIT(25) 49 50 #define SSIFCR_AUCKE BIT(31) 51 #define SSIFCR_SSIRST BIT(16) 52 #define SSIFCR_TIE BIT(3) 53 #define SSIFCR_RIE BIT(2) 54 #define SSIFCR_TFRST BIT(1) 55 #define SSIFCR_RFRST BIT(0) 56 57 #define SSIFSR_TDC_MASK 0x3f 58 #define SSIFSR_TDC_SHIFT 24 59 #define SSIFSR_RDC_MASK 0x3f 60 #define SSIFSR_RDC_SHIFT 8 61 62 #define SSIFSR_TDE BIT(16) 63 #define SSIFSR_RDF BIT(0) 64 65 #define SSIOFR_LRCONT BIT(8) 66 67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 69 70 /* Pre allocated buffers sizes */ 71 #define PREALLOC_BUFFER (SZ_32K) 72 #define PREALLOC_BUFFER_MAX (SZ_32K) 73 74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */ 75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 76 #define SSI_CHAN_MIN 2 77 #define SSI_CHAN_MAX 2 78 #define SSI_FIFO_DEPTH 32 79 80 struct rz_ssi_priv; 81 82 struct rz_ssi_stream { 83 struct rz_ssi_priv *priv; 84 struct snd_pcm_substream *substream; 85 int fifo_sample_size; /* sample capacity of SSI FIFO */ 86 int dma_buffer_pos; /* The address for the next DMA descriptor */ 87 int period_counter; /* for keeping track of periods transferred */ 88 int sample_width; 89 int buffer_pos; /* current frame position in the buffer */ 90 int running; /* 0=stopped, 1=running */ 91 92 int uerr_num; 93 int oerr_num; 94 95 struct dma_chan *dma_ch; 96 97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 98 }; 99 100 struct rz_ssi_priv { 101 void __iomem *base; 102 struct platform_device *pdev; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 113 spinlock_t lock; 114 115 /* 116 * The SSI supports full-duplex transmission and reception. 117 * However, if an error occurs, channel reset (both transmission 118 * and reception reset) is required. 119 * So it is better to use as half-duplex (playing and recording 120 * should be done on separate channels). 121 */ 122 struct rz_ssi_stream playback; 123 struct rz_ssi_stream capture; 124 125 /* clock */ 126 unsigned long audio_mck; 127 unsigned long audio_clk_1; 128 unsigned long audio_clk_2; 129 130 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 131 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 132 bool dma_rt; 133 }; 134 135 static void rz_ssi_dma_complete(void *data); 136 137 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 138 { 139 writel(data, (priv->base + reg)); 140 } 141 142 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 143 { 144 return readl(priv->base + reg); 145 } 146 147 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 148 u32 bclr, u32 bset) 149 { 150 u32 val; 151 152 val = readl(priv->base + reg); 153 val = (val & ~bclr) | bset; 154 writel(val, (priv->base + reg)); 155 } 156 157 static inline struct snd_soc_dai * 158 rz_ssi_get_dai(struct snd_pcm_substream *substream) 159 { 160 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 161 162 return asoc_rtd_to_cpu(rtd, 0); 163 } 164 165 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi, 166 struct snd_pcm_substream *substream) 167 { 168 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 169 } 170 171 static inline struct rz_ssi_stream * 172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 173 { 174 struct rz_ssi_stream *stream = &ssi->playback; 175 176 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 177 stream = &ssi->capture; 178 179 return stream; 180 } 181 182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 183 { 184 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 185 } 186 187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 188 struct snd_pcm_substream *substream) 189 { 190 struct rz_ssi_priv *ssi = strm->priv; 191 unsigned long flags; 192 193 spin_lock_irqsave(&ssi->lock, flags); 194 strm->substream = substream; 195 spin_unlock_irqrestore(&ssi->lock, flags); 196 } 197 198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 199 struct rz_ssi_stream *strm) 200 { 201 unsigned long flags; 202 bool ret; 203 204 spin_lock_irqsave(&ssi->lock, flags); 205 ret = strm->substream && strm->substream->runtime; 206 spin_unlock_irqrestore(&ssi->lock, flags); 207 208 return ret; 209 } 210 211 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 212 struct snd_pcm_substream *substream) 213 { 214 struct snd_pcm_runtime *runtime = substream->runtime; 215 216 rz_ssi_set_substream(strm, substream); 217 strm->sample_width = samples_to_bytes(runtime, 1); 218 strm->dma_buffer_pos = 0; 219 strm->period_counter = 0; 220 strm->buffer_pos = 0; 221 222 strm->oerr_num = 0; 223 strm->uerr_num = 0; 224 strm->running = 0; 225 226 /* fifo init */ 227 strm->fifo_sample_size = SSI_FIFO_DEPTH; 228 } 229 230 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 231 struct rz_ssi_stream *strm) 232 { 233 struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream); 234 235 rz_ssi_set_substream(strm, NULL); 236 237 if (strm->oerr_num > 0) 238 dev_info(dai->dev, "overrun = %d\n", strm->oerr_num); 239 240 if (strm->uerr_num > 0) 241 dev_info(dai->dev, "underrun = %d\n", strm->uerr_num); 242 } 243 244 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 245 unsigned int channels) 246 { 247 static s8 ckdv[16] = { 1, 2, 4, 8, 16, 32, 64, 128, 248 6, 12, 24, 48, 96, -1, -1, -1 }; 249 unsigned int channel_bits = 32; /* System Word Length */ 250 unsigned long bclk_rate = rate * channels * channel_bits; 251 unsigned int div; 252 unsigned int i; 253 u32 ssicr = 0; 254 u32 clk_ckdv; 255 256 /* Clear AUCKE so we can set MST */ 257 rz_ssi_reg_writel(ssi, SSIFCR, 0); 258 259 /* Continue to output LRCK pin even when idle */ 260 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 261 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 262 if (ssi->audio_clk_1 % bclk_rate) 263 ssi->audio_mck = ssi->audio_clk_2; 264 else 265 ssi->audio_mck = ssi->audio_clk_1; 266 } 267 268 /* Clock setting */ 269 ssicr |= SSICR_MST; 270 if (ssi->audio_mck == ssi->audio_clk_1) 271 ssicr |= SSICR_CKS; 272 if (ssi->bckp_rise) 273 ssicr |= SSICR_BCKP; 274 if (ssi->lrckp_fsync_fall) 275 ssicr |= SSICR_LRCKP; 276 277 /* Determine the clock divider */ 278 clk_ckdv = 0; 279 div = ssi->audio_mck / bclk_rate; 280 /* try to find an match */ 281 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 282 if (ckdv[i] == div) { 283 clk_ckdv = i; 284 break; 285 } 286 } 287 288 if (i == ARRAY_SIZE(ckdv)) { 289 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 290 return -EINVAL; 291 } 292 293 /* 294 * DWL: Data Word Length = 16 bits 295 * SWL: System Word Length = 32 bits 296 */ 297 ssicr |= SSICR_CKDV(clk_ckdv); 298 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 299 rz_ssi_reg_writel(ssi, SSICR, ssicr); 300 rz_ssi_reg_writel(ssi, SSIFCR, 301 (SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST)); 302 303 return 0; 304 } 305 306 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 307 { 308 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream); 309 u32 ssicr, ssifcr; 310 311 ssicr = rz_ssi_reg_readl(ssi, SSICR); 312 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF; 313 314 /* FIFO interrupt thresholds */ 315 if (rz_ssi_is_dma_enabled(ssi)) 316 rz_ssi_reg_writel(ssi, SSISCR, 0); 317 else 318 rz_ssi_reg_writel(ssi, SSISCR, 319 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 320 SSISCR_RDFS(0)); 321 322 /* enable IRQ */ 323 if (is_play) { 324 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 325 ssifcr |= SSIFCR_TIE | SSIFCR_RFRST; 326 } else { 327 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 328 ssifcr |= SSIFCR_RIE | SSIFCR_TFRST; 329 } 330 331 rz_ssi_reg_writel(ssi, SSICR, ssicr); 332 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 333 334 /* Clear all error flags */ 335 rz_ssi_reg_mask_setl(ssi, SSISR, 336 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 337 SSISR_RUIRQ), 0); 338 339 strm->running = 1; 340 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 341 rz_ssi_reg_writel(ssi, SSICR, ssicr); 342 343 return 0; 344 } 345 346 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 347 { 348 int timeout; 349 350 strm->running = 0; 351 352 /* Disable TX/RX */ 353 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 354 355 /* Cancel all remaining DMA transactions */ 356 if (rz_ssi_is_dma_enabled(ssi)) 357 dmaengine_terminate_async(strm->dma_ch); 358 359 /* Disable irqs */ 360 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 361 SSICR_RUIEN | SSICR_ROIEN, 0); 362 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 363 364 /* Clear all error flags */ 365 rz_ssi_reg_mask_setl(ssi, SSISR, 366 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 367 SSISR_RUIRQ), 0); 368 369 /* Wait for idle */ 370 timeout = 100; 371 while (--timeout) { 372 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ) 373 break; 374 udelay(1); 375 } 376 377 if (!timeout) 378 dev_info(ssi->dev, "timeout waiting for SSI idle\n"); 379 380 /* Hold FIFOs in reset */ 381 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, 382 SSIFCR_TFRST | SSIFCR_RFRST); 383 384 return 0; 385 } 386 387 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 388 { 389 struct snd_pcm_substream *substream = strm->substream; 390 struct snd_pcm_runtime *runtime; 391 int current_period; 392 393 if (!strm->running || !substream || !substream->runtime) 394 return; 395 396 runtime = substream->runtime; 397 strm->buffer_pos += frames; 398 WARN_ON(strm->buffer_pos > runtime->buffer_size); 399 400 /* ring buffer */ 401 if (strm->buffer_pos == runtime->buffer_size) 402 strm->buffer_pos = 0; 403 404 current_period = strm->buffer_pos / runtime->period_size; 405 if (strm->period_counter != current_period) { 406 snd_pcm_period_elapsed(strm->substream); 407 strm->period_counter = current_period; 408 } 409 } 410 411 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 412 { 413 struct snd_pcm_substream *substream = strm->substream; 414 struct snd_pcm_runtime *runtime; 415 u16 *buf; 416 int fifo_samples; 417 int frames_left; 418 int samples; 419 int i; 420 421 if (!rz_ssi_stream_is_valid(ssi, strm)) 422 return -EINVAL; 423 424 runtime = substream->runtime; 425 426 do { 427 /* frames left in this period */ 428 frames_left = runtime->period_size - 429 (strm->buffer_pos % runtime->period_size); 430 if (!frames_left) 431 frames_left = runtime->period_size; 432 433 /* Samples in RX FIFO */ 434 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 435 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 436 437 /* Only read full frames at a time */ 438 samples = 0; 439 while (frames_left && (fifo_samples >= runtime->channels)) { 440 samples += runtime->channels; 441 fifo_samples -= runtime->channels; 442 frames_left--; 443 } 444 445 /* not enough samples yet */ 446 if (!samples) 447 break; 448 449 /* calculate new buffer index */ 450 buf = (u16 *)runtime->dma_area; 451 buf += strm->buffer_pos * runtime->channels; 452 453 /* Note, only supports 16-bit samples */ 454 for (i = 0; i < samples; i++) 455 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 456 457 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 458 rz_ssi_pointer_update(strm, samples / runtime->channels); 459 } while (!frames_left && fifo_samples >= runtime->channels); 460 461 return 0; 462 } 463 464 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 465 { 466 struct snd_pcm_substream *substream = strm->substream; 467 struct snd_pcm_runtime *runtime = substream->runtime; 468 int sample_space; 469 int samples = 0; 470 int frames_left; 471 int i; 472 u32 ssifsr; 473 u16 *buf; 474 475 if (!rz_ssi_stream_is_valid(ssi, strm)) 476 return -EINVAL; 477 478 /* frames left in this period */ 479 frames_left = runtime->period_size - (strm->buffer_pos % 480 runtime->period_size); 481 if (frames_left == 0) 482 frames_left = runtime->period_size; 483 484 sample_space = strm->fifo_sample_size; 485 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 486 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 487 488 /* Only add full frames at a time */ 489 while (frames_left && (sample_space >= runtime->channels)) { 490 samples += runtime->channels; 491 sample_space -= runtime->channels; 492 frames_left--; 493 } 494 495 /* no space to send anything right now */ 496 if (samples == 0) 497 return 0; 498 499 /* calculate new buffer index */ 500 buf = (u16 *)(runtime->dma_area); 501 buf += strm->buffer_pos * runtime->channels; 502 503 /* Note, only supports 16-bit samples */ 504 for (i = 0; i < samples; i++) 505 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 506 507 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 508 rz_ssi_pointer_update(strm, samples / runtime->channels); 509 510 return 0; 511 } 512 513 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 514 { 515 struct rz_ssi_stream *strm = NULL; 516 struct rz_ssi_priv *ssi = data; 517 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 518 519 if (ssi->playback.substream) 520 strm = &ssi->playback; 521 else if (ssi->capture.substream) 522 strm = &ssi->capture; 523 else 524 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 525 526 if (irq == ssi->irq_int) { /* error or idle */ 527 if (ssisr & SSISR_TUIRQ) 528 strm->uerr_num++; 529 if (ssisr & SSISR_TOIRQ) 530 strm->oerr_num++; 531 if (ssisr & SSISR_RUIRQ) 532 strm->uerr_num++; 533 if (ssisr & SSISR_ROIRQ) 534 strm->oerr_num++; 535 536 if (ssisr & (SSISR_TUIRQ | SSISR_TOIRQ | SSISR_RUIRQ | 537 SSISR_ROIRQ)) { 538 /* Error handling */ 539 /* You must reset (stop/restart) after each interrupt */ 540 rz_ssi_stop(ssi, strm); 541 542 /* Clear all flags */ 543 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | 544 SSISR_TUIRQ | SSISR_ROIRQ | 545 SSISR_RUIRQ, 0); 546 547 /* Add/remove more data */ 548 strm->transfer(ssi, strm); 549 550 /* Resume */ 551 rz_ssi_start(ssi, strm); 552 } 553 } 554 555 if (!strm->running) 556 return IRQ_HANDLED; 557 558 /* tx data empty */ 559 if (irq == ssi->irq_tx) 560 strm->transfer(ssi, &ssi->playback); 561 562 /* rx data full */ 563 if (irq == ssi->irq_rx) { 564 strm->transfer(ssi, &ssi->capture); 565 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 566 } 567 568 return IRQ_HANDLED; 569 } 570 571 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 572 struct dma_chan *dma_ch, bool is_play) 573 { 574 struct dma_slave_config cfg; 575 576 memset(&cfg, 0, sizeof(cfg)); 577 578 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 579 cfg.dst_addr = ssi->phys + SSIFTDR; 580 cfg.src_addr = ssi->phys + SSIFRDR; 581 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 582 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 583 584 return dmaengine_slave_config(dma_ch, &cfg); 585 } 586 587 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 588 struct rz_ssi_stream *strm) 589 { 590 struct snd_pcm_substream *substream = strm->substream; 591 struct dma_async_tx_descriptor *desc; 592 struct snd_pcm_runtime *runtime; 593 enum dma_transfer_direction dir; 594 u32 dma_paddr, dma_size; 595 int amount; 596 597 if (!rz_ssi_stream_is_valid(ssi, strm)) 598 return -EINVAL; 599 600 runtime = substream->runtime; 601 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 602 /* 603 * Stream is ending, so do not queue up any more DMA 604 * transfers otherwise we play partial sound clips 605 * because we can't shut off the DMA quick enough. 606 */ 607 return 0; 608 609 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 610 611 /* Always transfer 1 period */ 612 amount = runtime->period_size; 613 614 /* DMA physical address and size */ 615 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 616 strm->dma_buffer_pos); 617 dma_size = frames_to_bytes(runtime, amount); 618 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 619 dir, 620 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 621 if (!desc) { 622 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 623 return -ENOMEM; 624 } 625 626 desc->callback = rz_ssi_dma_complete; 627 desc->callback_param = strm; 628 629 if (dmaengine_submit(desc) < 0) { 630 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 631 return -EIO; 632 } 633 634 /* Update DMA pointer */ 635 strm->dma_buffer_pos += amount; 636 if (strm->dma_buffer_pos >= runtime->buffer_size) 637 strm->dma_buffer_pos = 0; 638 639 /* Start DMA */ 640 dma_async_issue_pending(strm->dma_ch); 641 642 return 0; 643 } 644 645 static void rz_ssi_dma_complete(void *data) 646 { 647 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 648 649 if (!strm->running || !strm->substream || !strm->substream->runtime) 650 return; 651 652 /* Note that next DMA transaction has probably already started */ 653 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 654 655 /* Queue up another DMA transaction */ 656 rz_ssi_dma_transfer(strm->priv, strm); 657 } 658 659 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 660 { 661 if (ssi->playback.dma_ch) { 662 dma_release_channel(ssi->playback.dma_ch); 663 ssi->playback.dma_ch = NULL; 664 if (ssi->dma_rt) 665 ssi->dma_rt = false; 666 } 667 668 if (ssi->capture.dma_ch) { 669 dma_release_channel(ssi->capture.dma_ch); 670 ssi->capture.dma_ch = NULL; 671 } 672 } 673 674 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 675 { 676 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 677 if (IS_ERR(ssi->playback.dma_ch)) 678 ssi->playback.dma_ch = NULL; 679 680 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 681 if (IS_ERR(ssi->capture.dma_ch)) 682 ssi->capture.dma_ch = NULL; 683 684 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 685 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 686 if (IS_ERR(ssi->playback.dma_ch)) { 687 ssi->playback.dma_ch = NULL; 688 goto no_dma; 689 } 690 691 ssi->dma_rt = true; 692 } 693 694 if (!rz_ssi_is_dma_enabled(ssi)) 695 goto no_dma; 696 697 if (ssi->playback.dma_ch && 698 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 699 goto no_dma; 700 701 if (ssi->capture.dma_ch && 702 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 703 goto no_dma; 704 705 return 0; 706 707 no_dma: 708 rz_ssi_release_dma_channels(ssi); 709 710 return -ENODEV; 711 } 712 713 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 714 struct snd_soc_dai *dai) 715 { 716 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 717 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 718 int ret = 0, i, num_transfer = 1; 719 720 switch (cmd) { 721 case SNDRV_PCM_TRIGGER_START: 722 /* Soft Reset */ 723 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 724 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 725 udelay(5); 726 727 rz_ssi_stream_init(strm, substream); 728 729 if (ssi->dma_rt) { 730 bool is_playback; 731 732 is_playback = rz_ssi_stream_is_play(ssi, substream); 733 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 734 is_playback); 735 /* Fallback to pio */ 736 if (ret < 0) { 737 ssi->playback.transfer = rz_ssi_pio_send; 738 ssi->capture.transfer = rz_ssi_pio_recv; 739 rz_ssi_release_dma_channels(ssi); 740 } 741 } 742 743 /* For DMA, queue up multiple DMA descriptors */ 744 if (rz_ssi_is_dma_enabled(ssi)) 745 num_transfer = 4; 746 747 for (i = 0; i < num_transfer; i++) { 748 ret = strm->transfer(ssi, strm); 749 if (ret) 750 goto done; 751 } 752 753 ret = rz_ssi_start(ssi, strm); 754 break; 755 case SNDRV_PCM_TRIGGER_STOP: 756 rz_ssi_stop(ssi, strm); 757 rz_ssi_stream_quit(ssi, strm); 758 break; 759 } 760 761 done: 762 return ret; 763 } 764 765 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 766 { 767 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 768 769 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 770 case SND_SOC_DAIFMT_BP_FP: 771 break; 772 default: 773 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 774 return -EINVAL; 775 } 776 777 /* 778 * set clock polarity 779 * 780 * "normal" BCLK = Signal is available at rising edge of BCLK 781 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 782 */ 783 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 784 case SND_SOC_DAIFMT_NB_NF: 785 ssi->bckp_rise = false; 786 ssi->lrckp_fsync_fall = false; 787 break; 788 case SND_SOC_DAIFMT_NB_IF: 789 ssi->bckp_rise = false; 790 ssi->lrckp_fsync_fall = true; 791 break; 792 case SND_SOC_DAIFMT_IB_NF: 793 ssi->bckp_rise = true; 794 ssi->lrckp_fsync_fall = false; 795 break; 796 case SND_SOC_DAIFMT_IB_IF: 797 ssi->bckp_rise = true; 798 ssi->lrckp_fsync_fall = true; 799 break; 800 default: 801 return -EINVAL; 802 } 803 804 /* only i2s support */ 805 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 806 case SND_SOC_DAIFMT_I2S: 807 break; 808 default: 809 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 810 return -EINVAL; 811 } 812 813 return 0; 814 } 815 816 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 817 struct snd_pcm_hw_params *params, 818 struct snd_soc_dai *dai) 819 { 820 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 821 unsigned int sample_bits = hw_param_interval(params, 822 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 823 unsigned int channels = params_channels(params); 824 825 if (sample_bits != 16) { 826 dev_err(ssi->dev, "Unsupported sample width: %d\n", 827 sample_bits); 828 return -EINVAL; 829 } 830 831 if (channels != 2) { 832 dev_err(ssi->dev, "Number of channels not matched: %d\n", 833 channels); 834 return -EINVAL; 835 } 836 837 return rz_ssi_clk_setup(ssi, params_rate(params), 838 params_channels(params)); 839 } 840 841 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 842 .trigger = rz_ssi_dai_trigger, 843 .set_fmt = rz_ssi_dai_set_fmt, 844 .hw_params = rz_ssi_dai_hw_params, 845 }; 846 847 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 848 .info = SNDRV_PCM_INFO_INTERLEAVED | 849 SNDRV_PCM_INFO_MMAP | 850 SNDRV_PCM_INFO_MMAP_VALID, 851 .buffer_bytes_max = PREALLOC_BUFFER, 852 .period_bytes_min = 32, 853 .period_bytes_max = 8192, 854 .channels_min = SSI_CHAN_MIN, 855 .channels_max = SSI_CHAN_MAX, 856 .periods_min = 1, 857 .periods_max = 32, 858 .fifo_size = 32 * 2, 859 }; 860 861 static int rz_ssi_pcm_open(struct snd_soc_component *component, 862 struct snd_pcm_substream *substream) 863 { 864 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 865 866 return snd_pcm_hw_constraint_integer(substream->runtime, 867 SNDRV_PCM_HW_PARAM_PERIODS); 868 } 869 870 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 871 struct snd_pcm_substream *substream) 872 { 873 struct snd_soc_dai *dai = rz_ssi_get_dai(substream); 874 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 875 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 876 877 return strm->buffer_pos; 878 } 879 880 static int rz_ssi_pcm_new(struct snd_soc_component *component, 881 struct snd_soc_pcm_runtime *rtd) 882 { 883 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 884 rtd->card->snd_card->dev, 885 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 886 return 0; 887 } 888 889 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 890 { 891 .name = "rz-ssi-dai", 892 .playback = { 893 .rates = SSI_RATES, 894 .formats = SSI_FMTS, 895 .channels_min = SSI_CHAN_MIN, 896 .channels_max = SSI_CHAN_MAX, 897 }, 898 .capture = { 899 .rates = SSI_RATES, 900 .formats = SSI_FMTS, 901 .channels_min = SSI_CHAN_MIN, 902 .channels_max = SSI_CHAN_MAX, 903 }, 904 .ops = &rz_ssi_dai_ops, 905 }, 906 }; 907 908 static const struct snd_soc_component_driver rz_ssi_soc_component = { 909 .name = "rz-ssi", 910 .open = rz_ssi_pcm_open, 911 .pointer = rz_ssi_pcm_pointer, 912 .pcm_construct = rz_ssi_pcm_new, 913 .legacy_dai_naming = 1, 914 }; 915 916 static int rz_ssi_probe(struct platform_device *pdev) 917 { 918 struct rz_ssi_priv *ssi; 919 struct clk *audio_clk; 920 struct resource *res; 921 int ret; 922 923 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 924 if (!ssi) 925 return -ENOMEM; 926 927 ssi->pdev = pdev; 928 ssi->dev = &pdev->dev; 929 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 930 if (IS_ERR(ssi->base)) 931 return PTR_ERR(ssi->base); 932 933 ssi->phys = res->start; 934 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 935 if (IS_ERR(ssi->clk)) 936 return PTR_ERR(ssi->clk); 937 938 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 939 if (IS_ERR(ssi->sfr_clk)) 940 return PTR_ERR(ssi->sfr_clk); 941 942 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 943 if (IS_ERR(audio_clk)) 944 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 945 "no audio clk1"); 946 947 ssi->audio_clk_1 = clk_get_rate(audio_clk); 948 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 949 if (IS_ERR(audio_clk)) 950 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 951 "no audio clk2"); 952 953 ssi->audio_clk_2 = clk_get_rate(audio_clk); 954 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 955 return dev_err_probe(&pdev->dev, -EINVAL, 956 "no audio clk1 or audio clk2"); 957 958 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 959 960 /* Detect DMA support */ 961 ret = rz_ssi_dma_request(ssi, &pdev->dev); 962 if (ret < 0) { 963 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 964 ssi->playback.transfer = rz_ssi_pio_send; 965 ssi->capture.transfer = rz_ssi_pio_recv; 966 } else { 967 dev_info(&pdev->dev, "DMA enabled"); 968 ssi->playback.transfer = rz_ssi_dma_transfer; 969 ssi->capture.transfer = rz_ssi_dma_transfer; 970 } 971 972 ssi->playback.priv = ssi; 973 ssi->capture.priv = ssi; 974 975 spin_lock_init(&ssi->lock); 976 dev_set_drvdata(&pdev->dev, ssi); 977 978 /* Error Interrupt */ 979 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 980 if (ssi->irq_int < 0) { 981 rz_ssi_release_dma_channels(ssi); 982 return ssi->irq_int; 983 } 984 985 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 986 0, dev_name(&pdev->dev), ssi); 987 if (ret < 0) { 988 rz_ssi_release_dma_channels(ssi); 989 return dev_err_probe(&pdev->dev, ret, 990 "irq request error (int_req)\n"); 991 } 992 993 if (!rz_ssi_is_dma_enabled(ssi)) { 994 /* Tx and Rx interrupts (pio only) */ 995 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 996 if (ssi->irq_tx < 0) 997 return ssi->irq_tx; 998 999 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1000 &rz_ssi_interrupt, 0, 1001 dev_name(&pdev->dev), ssi); 1002 if (ret < 0) 1003 return dev_err_probe(&pdev->dev, ret, 1004 "irq request error (dma_tx)\n"); 1005 1006 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1007 if (ssi->irq_rx < 0) 1008 return ssi->irq_rx; 1009 1010 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1011 &rz_ssi_interrupt, 0, 1012 dev_name(&pdev->dev), ssi); 1013 if (ret < 0) 1014 return dev_err_probe(&pdev->dev, ret, 1015 "irq request error (dma_rx)\n"); 1016 } 1017 1018 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1019 if (IS_ERR(ssi->rstc)) { 1020 ret = PTR_ERR(ssi->rstc); 1021 goto err_reset; 1022 } 1023 1024 reset_control_deassert(ssi->rstc); 1025 pm_runtime_enable(&pdev->dev); 1026 ret = pm_runtime_resume_and_get(&pdev->dev); 1027 if (ret < 0) { 1028 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1029 goto err_pm; 1030 } 1031 1032 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1033 rz_ssi_soc_dai, 1034 ARRAY_SIZE(rz_ssi_soc_dai)); 1035 if (ret < 0) { 1036 dev_err(&pdev->dev, "failed to register snd component\n"); 1037 goto err_snd_soc; 1038 } 1039 1040 return 0; 1041 1042 err_snd_soc: 1043 pm_runtime_put(ssi->dev); 1044 err_pm: 1045 pm_runtime_disable(ssi->dev); 1046 reset_control_assert(ssi->rstc); 1047 err_reset: 1048 rz_ssi_release_dma_channels(ssi); 1049 1050 return ret; 1051 } 1052 1053 static int rz_ssi_remove(struct platform_device *pdev) 1054 { 1055 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1056 1057 rz_ssi_release_dma_channels(ssi); 1058 1059 pm_runtime_put(ssi->dev); 1060 pm_runtime_disable(ssi->dev); 1061 reset_control_assert(ssi->rstc); 1062 1063 return 0; 1064 } 1065 1066 static const struct of_device_id rz_ssi_of_match[] = { 1067 { .compatible = "renesas,rz-ssi", }, 1068 {/* Sentinel */}, 1069 }; 1070 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1071 1072 static struct platform_driver rz_ssi_driver = { 1073 .driver = { 1074 .name = "rz-ssi-pcm-audio", 1075 .of_match_table = rz_ssi_of_match, 1076 }, 1077 .probe = rz_ssi_probe, 1078 .remove = rz_ssi_remove, 1079 }; 1080 1081 module_platform_driver(rz_ssi_driver); 1082 1083 MODULE_LICENSE("GPL v2"); 1084 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1085 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1086