1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Helper routines for R-Car sound ADG. 4 // 5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 7 #include <linux/clk-provider.h> 8 #include "rsnd.h" 9 10 #define CLKA 0 11 #define CLKB 1 12 #define CLKC 2 13 #define CLKI 3 14 #define CLKMAX 4 15 16 #define CLKOUT 0 17 #define CLKOUT1 1 18 #define CLKOUT2 2 19 #define CLKOUT3 3 20 #define CLKOUTMAX 4 21 22 #define BRRx_MASK(x) (0x3FF & x) 23 24 static struct rsnd_mod_ops adg_ops = { 25 .name = "adg", 26 }; 27 28 struct rsnd_adg { 29 struct clk *clk[CLKMAX]; 30 struct clk *clkout[CLKOUTMAX]; 31 struct clk_onecell_data onecell; 32 struct rsnd_mod mod; 33 u32 flags; 34 u32 ckr; 35 u32 rbga; 36 u32 rbgb; 37 38 int rbga_rate_for_441khz; /* RBGA */ 39 int rbgb_rate_for_48khz; /* RBGB */ 40 }; 41 42 #define LRCLK_ASYNC (1 << 0) 43 #define AUDIO_OUT_48 (1 << 1) 44 45 #define for_each_rsnd_clk(pos, adg, i) \ 46 for (i = 0; \ 47 (i < CLKMAX) && \ 48 ((pos) = adg->clk[i]); \ 49 i++) 50 #define for_each_rsnd_clkout(pos, adg, i) \ 51 for (i = 0; \ 52 (i < CLKOUTMAX) && \ 53 ((pos) = adg->clkout[i]); \ 54 i++) 55 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 56 57 static const char * const clk_name[] = { 58 [CLKA] = "clk_a", 59 [CLKB] = "clk_b", 60 [CLKC] = "clk_c", 61 [CLKI] = "clk_i", 62 }; 63 64 static u32 rsnd_adg_calculate_rbgx(unsigned long div) 65 { 66 int i, ratio; 67 68 if (!div) 69 return 0; 70 71 for (i = 3; i >= 0; i--) { 72 ratio = 2 << (i * 2); 73 if (0 == (div % ratio)) 74 return (u32)((i << 8) | ((div / ratio) - 1)); 75 } 76 77 return ~0; 78 } 79 80 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 81 { 82 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 83 int id = rsnd_mod_id(ssi_mod); 84 int ws = id; 85 86 if (rsnd_ssi_is_pin_sharing(io)) { 87 switch (id) { 88 case 1: 89 case 2: 90 ws = 0; 91 break; 92 case 4: 93 ws = 3; 94 break; 95 case 8: 96 ws = 7; 97 break; 98 } 99 } 100 101 return (0x6 + ws) << 8; 102 } 103 104 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 105 struct rsnd_dai_stream *io, 106 unsigned int target_rate, 107 unsigned int *target_val, 108 unsigned int *target_en) 109 { 110 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 111 struct device *dev = rsnd_priv_to_dev(priv); 112 int idx, sel, div, step; 113 unsigned int val, en; 114 unsigned int min, diff; 115 unsigned int sel_rate[] = { 116 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 117 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ 118 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ 119 adg->rbga_rate_for_441khz, /* 0011: RBGA */ 120 adg->rbgb_rate_for_48khz, /* 0100: RBGB */ 121 }; 122 123 min = ~0; 124 val = 0; 125 en = 0; 126 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 127 idx = 0; 128 step = 2; 129 130 if (!sel_rate[sel]) 131 continue; 132 133 for (div = 2; div <= 98304; div += step) { 134 diff = abs(target_rate - sel_rate[sel] / div); 135 if (min > diff) { 136 val = (sel << 8) | idx; 137 min = diff; 138 en = 1 << (sel + 1); /* fixme */ 139 } 140 141 /* 142 * step of 0_0000 / 0_0001 / 0_1101 143 * are out of order 144 */ 145 if ((idx > 2) && (idx % 2)) 146 step *= 2; 147 if (idx == 0x1c) { 148 div += step; 149 step *= 2; 150 } 151 idx++; 152 } 153 } 154 155 if (min == ~0) { 156 dev_err(dev, "no Input clock\n"); 157 return; 158 } 159 160 *target_val = val; 161 if (target_en) 162 *target_en = en; 163 } 164 165 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 166 struct rsnd_dai_stream *io, 167 unsigned int in_rate, 168 unsigned int out_rate, 169 u32 *in, u32 *out, u32 *en) 170 { 171 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); 172 unsigned int target_rate; 173 u32 *target_val; 174 u32 _in; 175 u32 _out; 176 u32 _en; 177 178 /* default = SSI WS */ 179 _in = 180 _out = rsnd_adg_ssi_ws_timing_gen2(io); 181 182 target_rate = 0; 183 target_val = NULL; 184 _en = 0; 185 if (runtime->rate != in_rate) { 186 target_rate = out_rate; 187 target_val = &_out; 188 } else if (runtime->rate != out_rate) { 189 target_rate = in_rate; 190 target_val = &_in; 191 } 192 193 if (target_rate) 194 __rsnd_adg_get_timesel_ratio(priv, io, 195 target_rate, 196 target_val, &_en); 197 198 if (in) 199 *in = _in; 200 if (out) 201 *out = _out; 202 if (en) 203 *en = _en; 204 } 205 206 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 207 struct rsnd_dai_stream *io) 208 { 209 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 210 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 211 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 212 int id = rsnd_mod_id(cmd_mod); 213 int shift = (id % 2) ? 16 : 0; 214 u32 mask, val; 215 216 rsnd_adg_get_timesel_ratio(priv, io, 217 rsnd_src_get_in_rate(priv, io), 218 rsnd_src_get_out_rate(priv, io), 219 NULL, &val, NULL); 220 221 val = val << shift; 222 mask = 0x0f1f << shift; 223 224 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 225 226 return 0; 227 } 228 229 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, 230 struct rsnd_dai_stream *io, 231 unsigned int in_rate, 232 unsigned int out_rate) 233 { 234 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 235 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 236 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 237 u32 in, out; 238 u32 mask, en; 239 int id = rsnd_mod_id(src_mod); 240 int shift = (id % 2) ? 16 : 0; 241 242 rsnd_mod_confirm_src(src_mod); 243 244 rsnd_adg_get_timesel_ratio(priv, io, 245 in_rate, out_rate, 246 &in, &out, &en); 247 248 in = in << shift; 249 out = out << shift; 250 mask = 0x0f1f << shift; 251 252 switch (id / 2) { 253 case 0: 254 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in); 255 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out); 256 break; 257 case 1: 258 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in); 259 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out); 260 break; 261 case 2: 262 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in); 263 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out); 264 break; 265 case 3: 266 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in); 267 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out); 268 break; 269 case 4: 270 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in); 271 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out); 272 break; 273 } 274 275 if (en) 276 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 277 278 return 0; 279 } 280 281 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 282 { 283 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 284 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 285 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 286 struct device *dev = rsnd_priv_to_dev(priv); 287 int id = rsnd_mod_id(ssi_mod); 288 int shift = (id % 4) * 8; 289 u32 mask = 0xFF << shift; 290 291 rsnd_mod_confirm_ssi(ssi_mod); 292 293 val = val << shift; 294 295 /* 296 * SSI 8 is not connected to ADG. 297 * it works with SSI 7 298 */ 299 if (id == 8) 300 return; 301 302 switch (id / 4) { 303 case 0: 304 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val); 305 break; 306 case 1: 307 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val); 308 break; 309 case 2: 310 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val); 311 break; 312 } 313 314 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); 315 } 316 317 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) 318 { 319 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 320 struct clk *clk; 321 int i; 322 int sel_table[] = { 323 [CLKA] = 0x1, 324 [CLKB] = 0x2, 325 [CLKC] = 0x3, 326 [CLKI] = 0x0, 327 }; 328 329 /* 330 * find suitable clock from 331 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 332 */ 333 for_each_rsnd_clk(clk, adg, i) { 334 if (rate == clk_get_rate(clk)) 335 return sel_table[i]; 336 } 337 338 /* 339 * find divided clock from BRGA/BRGB 340 */ 341 if (rate == adg->rbga_rate_for_441khz) 342 return 0x10; 343 344 if (rate == adg->rbgb_rate_for_48khz) 345 return 0x20; 346 347 return -EIO; 348 } 349 350 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 351 { 352 rsnd_adg_set_ssi_clk(ssi_mod, 0); 353 354 return 0; 355 } 356 357 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 358 { 359 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 360 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 361 struct device *dev = rsnd_priv_to_dev(priv); 362 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 363 int data; 364 u32 ckr = 0; 365 366 data = rsnd_adg_clk_query(priv, rate); 367 if (data < 0) 368 return data; 369 370 rsnd_adg_set_ssi_clk(ssi_mod, data); 371 372 if (rsnd_flags_has(adg, LRCLK_ASYNC)) { 373 if (rsnd_flags_has(adg, AUDIO_OUT_48)) 374 ckr = 0x80000000; 375 } else { 376 if (0 == (rate % 8000)) 377 ckr = 0x80000000; 378 } 379 380 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); 381 rsnd_mod_write(adg_mod, BRRA, adg->rbga); 382 rsnd_mod_write(adg_mod, BRRB, adg->rbgb); 383 384 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", 385 (ckr) ? 'B' : 'A', 386 (ckr) ? adg->rbgb_rate_for_48khz : 387 adg->rbga_rate_for_441khz); 388 389 return 0; 390 } 391 392 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) 393 { 394 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 395 struct device *dev = rsnd_priv_to_dev(priv); 396 struct clk *clk; 397 int i, ret; 398 399 for_each_rsnd_clk(clk, adg, i) { 400 ret = 0; 401 if (enable) 402 ret = clk_prepare_enable(clk); 403 else 404 clk_disable_unprepare(clk); 405 406 if (ret < 0) 407 dev_warn(dev, "can't use clk %d\n", i); 408 } 409 } 410 411 static void rsnd_adg_get_clkin(struct rsnd_priv *priv, 412 struct rsnd_adg *adg) 413 { 414 struct device *dev = rsnd_priv_to_dev(priv); 415 struct clk *clk; 416 int i; 417 418 for (i = 0; i < CLKMAX; i++) { 419 clk = devm_clk_get(dev, clk_name[i]); 420 adg->clk[i] = IS_ERR(clk) ? NULL : clk; 421 } 422 } 423 424 static void rsnd_adg_get_clkout(struct rsnd_priv *priv, 425 struct rsnd_adg *adg) 426 { 427 struct clk *clk; 428 struct device *dev = rsnd_priv_to_dev(priv); 429 struct device_node *np = dev->of_node; 430 struct property *prop; 431 u32 ckr, rbgx, rbga, rbgb; 432 u32 rate, div; 433 #define REQ_SIZE 2 434 u32 req_rate[REQ_SIZE] = {}; 435 uint32_t count = 0; 436 unsigned long req_48kHz_rate, req_441kHz_rate; 437 int i, req_size; 438 const char *parent_clk_name = NULL; 439 static const char * const clkout_name[] = { 440 [CLKOUT] = "audio_clkout", 441 [CLKOUT1] = "audio_clkout1", 442 [CLKOUT2] = "audio_clkout2", 443 [CLKOUT3] = "audio_clkout3", 444 }; 445 int brg_table[] = { 446 [CLKA] = 0x0, 447 [CLKB] = 0x1, 448 [CLKC] = 0x4, 449 [CLKI] = 0x2, 450 }; 451 452 ckr = 0; 453 rbga = 2; /* default 1/6 */ 454 rbgb = 2; /* default 1/6 */ 455 456 /* 457 * ADG supports BRRA/BRRB output only 458 * this means all clkout0/1/2/3 will be same rate 459 */ 460 prop = of_find_property(np, "clock-frequency", NULL); 461 if (!prop) 462 goto rsnd_adg_get_clkout_end; 463 464 req_size = prop->length / sizeof(u32); 465 466 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); 467 req_48kHz_rate = 0; 468 req_441kHz_rate = 0; 469 for (i = 0; i < req_size; i++) { 470 if (0 == (req_rate[i] % 44100)) 471 req_441kHz_rate = req_rate[i]; 472 if (0 == (req_rate[i] % 48000)) 473 req_48kHz_rate = req_rate[i]; 474 } 475 476 if (req_rate[0] % 48000 == 0) 477 rsnd_flags_set(adg, AUDIO_OUT_48); 478 479 if (of_get_property(np, "clkout-lr-asynchronous", NULL)) 480 rsnd_flags_set(adg, LRCLK_ASYNC); 481 482 /* 483 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 484 * have 44.1kHz or 48kHz base clocks for now. 485 * 486 * SSI itself can divide parent clock by 1/1 - 1/16 487 * see 488 * rsnd_adg_ssi_clk_try_start() 489 * rsnd_ssi_master_clk_start() 490 */ 491 adg->rbga_rate_for_441khz = 0; 492 adg->rbgb_rate_for_48khz = 0; 493 for_each_rsnd_clk(clk, adg, i) { 494 rate = clk_get_rate(clk); 495 496 if (0 == rate) /* not used */ 497 continue; 498 499 /* RBGA */ 500 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { 501 div = 6; 502 if (req_441kHz_rate) 503 div = rate / req_441kHz_rate; 504 rbgx = rsnd_adg_calculate_rbgx(div); 505 if (BRRx_MASK(rbgx) == rbgx) { 506 rbga = rbgx; 507 adg->rbga_rate_for_441khz = rate / div; 508 ckr |= brg_table[i] << 20; 509 if (req_441kHz_rate && 510 !rsnd_flags_has(adg, AUDIO_OUT_48)) 511 parent_clk_name = __clk_get_name(clk); 512 } 513 } 514 515 /* RBGB */ 516 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { 517 div = 6; 518 if (req_48kHz_rate) 519 div = rate / req_48kHz_rate; 520 rbgx = rsnd_adg_calculate_rbgx(div); 521 if (BRRx_MASK(rbgx) == rbgx) { 522 rbgb = rbgx; 523 adg->rbgb_rate_for_48khz = rate / div; 524 ckr |= brg_table[i] << 16; 525 if (req_48kHz_rate && 526 rsnd_flags_has(adg, AUDIO_OUT_48)) 527 parent_clk_name = __clk_get_name(clk); 528 } 529 } 530 } 531 532 /* 533 * ADG supports BRRA/BRRB output only. 534 * this means all clkout0/1/2/3 will be * same rate 535 */ 536 537 of_property_read_u32(np, "#clock-cells", &count); 538 /* 539 * for clkout 540 */ 541 if (!count) { 542 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 543 parent_clk_name, 0, req_rate[0]); 544 if (!IS_ERR(clk)) { 545 adg->clkout[CLKOUT] = clk; 546 of_clk_add_provider(np, of_clk_src_simple_get, clk); 547 } 548 } 549 /* 550 * for clkout0/1/2/3 551 */ 552 else { 553 for (i = 0; i < CLKOUTMAX; i++) { 554 clk = clk_register_fixed_rate(dev, clkout_name[i], 555 parent_clk_name, 0, 556 req_rate[0]); 557 if (!IS_ERR(clk)) 558 adg->clkout[i] = clk; 559 } 560 adg->onecell.clks = adg->clkout; 561 adg->onecell.clk_num = CLKOUTMAX; 562 of_clk_add_provider(np, of_clk_src_onecell_get, 563 &adg->onecell); 564 } 565 566 rsnd_adg_get_clkout_end: 567 adg->ckr = ckr; 568 adg->rbga = rbga; 569 adg->rbgb = rbgb; 570 } 571 572 #ifdef DEBUG 573 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg) 574 { 575 struct device *dev = rsnd_priv_to_dev(priv); 576 struct clk *clk; 577 int i; 578 579 for_each_rsnd_clk(clk, adg, i) 580 dev_dbg(dev, "%s : %p : %ld\n", 581 clk_name[i], clk, clk_get_rate(clk)); 582 583 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 584 adg->ckr, adg->rbga, adg->rbgb); 585 dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz); 586 dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz); 587 588 /* 589 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() 590 * by BRGCKR::BRGCKR_31 591 */ 592 for_each_rsnd_clkout(clk, adg, i) 593 dev_dbg(dev, "clkout %d : %p : %ld\n", i, 594 clk, clk_get_rate(clk)); 595 } 596 #else 597 #define rsnd_adg_clk_dbg_info(priv, adg) 598 #endif 599 600 int rsnd_adg_probe(struct rsnd_priv *priv) 601 { 602 struct rsnd_adg *adg; 603 struct device *dev = rsnd_priv_to_dev(priv); 604 int ret; 605 606 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 607 if (!adg) 608 return -ENOMEM; 609 610 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, 611 NULL, NULL, 0, 0); 612 if (ret) 613 return ret; 614 615 rsnd_adg_get_clkin(priv, adg); 616 rsnd_adg_get_clkout(priv, adg); 617 rsnd_adg_clk_dbg_info(priv, adg); 618 619 priv->adg = adg; 620 621 rsnd_adg_clk_enable(priv); 622 623 return 0; 624 } 625 626 void rsnd_adg_remove(struct rsnd_priv *priv) 627 { 628 struct device *dev = rsnd_priv_to_dev(priv); 629 struct device_node *np = dev->of_node; 630 struct rsnd_adg *adg = priv->adg; 631 struct clk *clk; 632 int i; 633 634 for_each_rsnd_clkout(clk, adg, i) 635 if (adg->clkout[i]) 636 clk_unregister_fixed_rate(adg->clkout[i]); 637 638 of_clk_del_provider(np); 639 640 rsnd_adg_clk_disable(priv); 641 } 642