1 /* 2 * Helper routines for R-Car sound ADG. 3 * 4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/clk-provider.h> 11 #include "rsnd.h" 12 13 #define CLKA 0 14 #define CLKB 1 15 #define CLKC 2 16 #define CLKI 3 17 #define CLKMAX 4 18 19 #define CLKOUT 0 20 #define CLKOUT1 1 21 #define CLKOUT2 2 22 #define CLKOUT3 3 23 #define CLKOUTMAX 4 24 25 #define BRRx_MASK(x) (0x3FF & x) 26 27 static struct rsnd_mod_ops adg_ops = { 28 .name = "adg", 29 }; 30 31 struct rsnd_adg { 32 struct clk *clk[CLKMAX]; 33 struct clk *clkout[CLKOUTMAX]; 34 struct clk_onecell_data onecell; 35 struct rsnd_mod mod; 36 37 int rbga_rate_for_441khz; /* RBGA */ 38 int rbgb_rate_for_48khz; /* RBGB */ 39 }; 40 41 #define for_each_rsnd_clk(pos, adg, i) \ 42 for (i = 0; \ 43 (i < CLKMAX) && \ 44 ((pos) = adg->clk[i]); \ 45 i++) 46 #define for_each_rsnd_clkout(pos, adg, i) \ 47 for (i = 0; \ 48 (i < CLKOUTMAX) && \ 49 ((pos) = adg->clkout[i]); \ 50 i++) 51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 52 53 static u32 rsnd_adg_calculate_rbgx(unsigned long div) 54 { 55 int i, ratio; 56 57 if (!div) 58 return 0; 59 60 for (i = 3; i >= 0; i--) { 61 ratio = 2 << (i * 2); 62 if (0 == (div % ratio)) 63 return (u32)((i << 8) | ((div / ratio) - 1)); 64 } 65 66 return ~0; 67 } 68 69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 70 { 71 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 72 int id = rsnd_mod_id(ssi_mod); 73 int ws = id; 74 75 if (rsnd_ssi_is_pin_sharing(io)) { 76 switch (id) { 77 case 1: 78 case 2: 79 ws = 0; 80 break; 81 case 4: 82 ws = 3; 83 break; 84 case 8: 85 ws = 7; 86 break; 87 } 88 } 89 90 return (0x6 + ws) << 8; 91 } 92 93 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 94 struct rsnd_dai_stream *io, 95 unsigned int target_rate, 96 unsigned int *target_val, 97 unsigned int *target_en) 98 { 99 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 100 struct device *dev = rsnd_priv_to_dev(priv); 101 int idx, sel, div, step; 102 unsigned int val, en; 103 unsigned int min, diff; 104 unsigned int sel_rate[] = { 105 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 106 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ 107 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ 108 adg->rbga_rate_for_441khz, /* 0011: RBGA */ 109 adg->rbgb_rate_for_48khz, /* 0100: RBGB */ 110 }; 111 112 min = ~0; 113 val = 0; 114 en = 0; 115 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 116 idx = 0; 117 step = 2; 118 119 if (!sel_rate[sel]) 120 continue; 121 122 for (div = 2; div <= 98304; div += step) { 123 diff = abs(target_rate - sel_rate[sel] / div); 124 if (min > diff) { 125 val = (sel << 8) | idx; 126 min = diff; 127 en = 1 << (sel + 1); /* fixme */ 128 } 129 130 /* 131 * step of 0_0000 / 0_0001 / 0_1101 132 * are out of order 133 */ 134 if ((idx > 2) && (idx % 2)) 135 step *= 2; 136 if (idx == 0x1c) { 137 div += step; 138 step *= 2; 139 } 140 idx++; 141 } 142 } 143 144 if (min == ~0) { 145 dev_err(dev, "no Input clock\n"); 146 return; 147 } 148 149 *target_val = val; 150 if (target_en) 151 *target_en = en; 152 } 153 154 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 155 struct rsnd_dai_stream *io, 156 unsigned int in_rate, 157 unsigned int out_rate, 158 u32 *in, u32 *out, u32 *en) 159 { 160 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); 161 unsigned int target_rate; 162 u32 *target_val; 163 u32 _in; 164 u32 _out; 165 u32 _en; 166 167 /* default = SSI WS */ 168 _in = 169 _out = rsnd_adg_ssi_ws_timing_gen2(io); 170 171 target_rate = 0; 172 target_val = NULL; 173 _en = 0; 174 if (runtime->rate != in_rate) { 175 target_rate = out_rate; 176 target_val = &_out; 177 } else if (runtime->rate != out_rate) { 178 target_rate = in_rate; 179 target_val = &_in; 180 } 181 182 if (target_rate) 183 __rsnd_adg_get_timesel_ratio(priv, io, 184 target_rate, 185 target_val, &_en); 186 187 if (in) 188 *in = _in; 189 if (out) 190 *out = _out; 191 if (en) 192 *en = _en; 193 } 194 195 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 196 struct rsnd_dai_stream *io) 197 { 198 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 199 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 200 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 201 int id = rsnd_mod_id(cmd_mod); 202 int shift = (id % 2) ? 16 : 0; 203 u32 mask, val; 204 205 rsnd_adg_get_timesel_ratio(priv, io, 206 rsnd_src_get_in_rate(priv, io), 207 rsnd_src_get_out_rate(priv, io), 208 NULL, &val, NULL); 209 210 val = val << shift; 211 mask = 0xffff << shift; 212 213 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 214 215 return 0; 216 } 217 218 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, 219 struct rsnd_dai_stream *io, 220 unsigned int in_rate, 221 unsigned int out_rate) 222 { 223 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 224 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 225 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 226 u32 in, out; 227 u32 mask, en; 228 int id = rsnd_mod_id(src_mod); 229 int shift = (id % 2) ? 16 : 0; 230 231 rsnd_mod_confirm_src(src_mod); 232 233 rsnd_adg_get_timesel_ratio(priv, io, 234 in_rate, out_rate, 235 &in, &out, &en); 236 237 in = in << shift; 238 out = out << shift; 239 mask = 0xffff << shift; 240 241 switch (id / 2) { 242 case 0: 243 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in); 244 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out); 245 break; 246 case 1: 247 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in); 248 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out); 249 break; 250 case 2: 251 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in); 252 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out); 253 break; 254 case 3: 255 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in); 256 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out); 257 break; 258 case 4: 259 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in); 260 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out); 261 break; 262 } 263 264 if (en) 265 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 266 267 return 0; 268 } 269 270 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 271 { 272 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 273 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 274 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 275 int id = rsnd_mod_id(ssi_mod); 276 int shift = (id % 4) * 8; 277 u32 mask = 0xFF << shift; 278 279 rsnd_mod_confirm_ssi(ssi_mod); 280 281 val = val << shift; 282 283 /* 284 * SSI 8 is not connected to ADG. 285 * it works with SSI 7 286 */ 287 if (id == 8) 288 return; 289 290 switch (id / 4) { 291 case 0: 292 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val); 293 break; 294 case 1: 295 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val); 296 break; 297 case 2: 298 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val); 299 break; 300 } 301 } 302 303 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 304 { 305 rsnd_adg_set_ssi_clk(ssi_mod, 0); 306 307 return 0; 308 } 309 310 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 311 { 312 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 313 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 314 struct device *dev = rsnd_priv_to_dev(priv); 315 struct clk *clk; 316 int i; 317 u32 data; 318 int sel_table[] = { 319 [CLKA] = 0x1, 320 [CLKB] = 0x2, 321 [CLKC] = 0x3, 322 [CLKI] = 0x0, 323 }; 324 325 dev_dbg(dev, "request clock = %d\n", rate); 326 327 /* 328 * find suitable clock from 329 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 330 */ 331 data = 0; 332 for_each_rsnd_clk(clk, adg, i) { 333 if (rate == clk_get_rate(clk)) { 334 data = sel_table[i]; 335 goto found_clock; 336 } 337 } 338 339 /* 340 * find divided clock from BRGA/BRGB 341 */ 342 if (rate == adg->rbga_rate_for_441khz) { 343 data = 0x10; 344 goto found_clock; 345 } 346 347 if (rate == adg->rbgb_rate_for_48khz) { 348 data = 0x20; 349 goto found_clock; 350 } 351 352 return -EIO; 353 354 found_clock: 355 356 rsnd_adg_set_ssi_clk(ssi_mod, data); 357 358 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n", 359 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod), 360 data, rate); 361 362 return 0; 363 } 364 365 static void rsnd_adg_get_clkin(struct rsnd_priv *priv, 366 struct rsnd_adg *adg) 367 { 368 struct device *dev = rsnd_priv_to_dev(priv); 369 struct clk *clk; 370 static const char * const clk_name[] = { 371 [CLKA] = "clk_a", 372 [CLKB] = "clk_b", 373 [CLKC] = "clk_c", 374 [CLKI] = "clk_i", 375 }; 376 int i, ret; 377 378 for (i = 0; i < CLKMAX; i++) { 379 clk = devm_clk_get(dev, clk_name[i]); 380 adg->clk[i] = IS_ERR(clk) ? NULL : clk; 381 } 382 383 for_each_rsnd_clk(clk, adg, i) { 384 ret = clk_prepare_enable(clk); 385 if (ret < 0) 386 dev_warn(dev, "can't use clk %d\n", i); 387 388 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk)); 389 } 390 } 391 392 static void rsnd_adg_get_clkout(struct rsnd_priv *priv, 393 struct rsnd_adg *adg) 394 { 395 struct clk *clk; 396 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 397 struct device *dev = rsnd_priv_to_dev(priv); 398 struct device_node *np = dev->of_node; 399 u32 ckr, rbgx, rbga, rbgb; 400 u32 rate, req_rate = 0, div; 401 uint32_t count = 0; 402 unsigned long req_48kHz_rate, req_441kHz_rate; 403 int i; 404 const char *parent_clk_name = NULL; 405 static const char * const clkout_name[] = { 406 [CLKOUT] = "audio_clkout", 407 [CLKOUT1] = "audio_clkout1", 408 [CLKOUT2] = "audio_clkout2", 409 [CLKOUT3] = "audio_clkout3", 410 }; 411 int brg_table[] = { 412 [CLKA] = 0x0, 413 [CLKB] = 0x1, 414 [CLKC] = 0x4, 415 [CLKI] = 0x2, 416 }; 417 418 of_property_read_u32(np, "#clock-cells", &count); 419 420 /* 421 * ADG supports BRRA/BRRB output only 422 * this means all clkout0/1/2/3 will be same rate 423 */ 424 of_property_read_u32(np, "clock-frequency", &req_rate); 425 req_48kHz_rate = 0; 426 req_441kHz_rate = 0; 427 if (0 == (req_rate % 44100)) 428 req_441kHz_rate = req_rate; 429 if (0 == (req_rate % 48000)) 430 req_48kHz_rate = req_rate; 431 432 /* 433 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 434 * have 44.1kHz or 48kHz base clocks for now. 435 * 436 * SSI itself can divide parent clock by 1/1 - 1/16 437 * see 438 * rsnd_adg_ssi_clk_try_start() 439 * rsnd_ssi_master_clk_start() 440 */ 441 ckr = 0; 442 rbga = 2; /* default 1/6 */ 443 rbgb = 2; /* default 1/6 */ 444 adg->rbga_rate_for_441khz = 0; 445 adg->rbgb_rate_for_48khz = 0; 446 for_each_rsnd_clk(clk, adg, i) { 447 rate = clk_get_rate(clk); 448 449 if (0 == rate) /* not used */ 450 continue; 451 452 /* RBGA */ 453 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { 454 div = 6; 455 if (req_441kHz_rate) 456 div = rate / req_441kHz_rate; 457 rbgx = rsnd_adg_calculate_rbgx(div); 458 if (BRRx_MASK(rbgx) == rbgx) { 459 rbga = rbgx; 460 adg->rbga_rate_for_441khz = rate / div; 461 ckr |= brg_table[i] << 20; 462 if (req_441kHz_rate) 463 parent_clk_name = __clk_get_name(clk); 464 } 465 } 466 467 /* RBGB */ 468 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { 469 div = 6; 470 if (req_48kHz_rate) 471 div = rate / req_48kHz_rate; 472 rbgx = rsnd_adg_calculate_rbgx(div); 473 if (BRRx_MASK(rbgx) == rbgx) { 474 rbgb = rbgx; 475 adg->rbgb_rate_for_48khz = rate / div; 476 ckr |= brg_table[i] << 16; 477 if (req_48kHz_rate) { 478 parent_clk_name = __clk_get_name(clk); 479 ckr |= 0x80000000; 480 } 481 } 482 } 483 } 484 485 /* 486 * ADG supports BRRA/BRRB output only. 487 * this means all clkout0/1/2/3 will be * same rate 488 */ 489 490 /* 491 * for clkout 492 */ 493 if (!count) { 494 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 495 parent_clk_name, 496 (parent_clk_name) ? 497 0 : CLK_IS_ROOT, req_rate); 498 if (!IS_ERR(clk)) { 499 adg->clkout[CLKOUT] = clk; 500 of_clk_add_provider(np, of_clk_src_simple_get, clk); 501 } 502 } 503 /* 504 * for clkout0/1/2/3 505 */ 506 else { 507 for (i = 0; i < CLKOUTMAX; i++) { 508 clk = clk_register_fixed_rate(dev, clkout_name[i], 509 parent_clk_name, 510 (parent_clk_name) ? 511 0 : CLK_IS_ROOT, 512 req_rate); 513 if (!IS_ERR(clk)) { 514 adg->onecell.clks = adg->clkout; 515 adg->onecell.clk_num = CLKOUTMAX; 516 517 adg->clkout[i] = clk; 518 519 of_clk_add_provider(np, of_clk_src_onecell_get, 520 &adg->onecell); 521 } 522 } 523 } 524 525 rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr); 526 rsnd_mod_write(adg_mod, BRRA, rbga); 527 rsnd_mod_write(adg_mod, BRRB, rbgb); 528 529 for_each_rsnd_clkout(clk, adg, i) 530 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); 531 dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 532 ckr, rbga, rbgb); 533 } 534 535 int rsnd_adg_probe(struct rsnd_priv *priv) 536 { 537 struct rsnd_adg *adg; 538 struct device *dev = rsnd_priv_to_dev(priv); 539 540 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 541 if (!adg) { 542 dev_err(dev, "ADG allocate failed\n"); 543 return -ENOMEM; 544 } 545 546 rsnd_mod_init(priv, &adg->mod, &adg_ops, 547 NULL, NULL, 0, 0); 548 549 rsnd_adg_get_clkin(priv, adg); 550 rsnd_adg_get_clkout(priv, adg); 551 552 priv->adg = adg; 553 554 return 0; 555 } 556 557 void rsnd_adg_remove(struct rsnd_priv *priv) 558 { 559 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 560 struct clk *clk; 561 int i; 562 563 for_each_rsnd_clk(clk, adg, i) { 564 clk_disable_unprepare(clk); 565 } 566 } 567