1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Helper routines for R-Car sound ADG. 4 // 5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 #include <linux/clk-provider.h> 7 #include <linux/clkdev.h> 8 #include "rsnd.h" 9 10 #define CLKA 0 11 #define CLKB 1 12 #define CLKC 2 13 #define CLKI 3 14 #define CLKINMAX 4 15 16 #define CLKOUT 0 17 #define CLKOUT1 1 18 #define CLKOUT2 2 19 #define CLKOUT3 3 20 #define CLKOUTMAX 4 21 22 #define BRRx_MASK(x) (0x3FF & x) 23 24 static struct rsnd_mod_ops adg_ops = { 25 .name = "adg", 26 }; 27 28 #define ADG_HZ_441 0 29 #define ADG_HZ_48 1 30 #define ADG_HZ_SIZE 2 31 32 struct rsnd_adg { 33 struct clk *clkin[CLKINMAX]; 34 struct clk *clkout[CLKOUTMAX]; 35 struct clk *null_clk; 36 struct clk_onecell_data onecell; 37 struct rsnd_mod mod; 38 int clkin_rate[CLKINMAX]; 39 int clkin_size; 40 int clkout_size; 41 u32 ckr; 42 u32 brga; 43 u32 brgb; 44 45 int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */ 46 }; 47 48 #define for_each_rsnd_clkin(pos, adg, i) \ 49 for (i = 0; \ 50 (i < adg->clkin_size) && \ 51 ((pos) = adg->clkin[i]); \ 52 i++) 53 #define for_each_rsnd_clkout(pos, adg, i) \ 54 for (i = 0; \ 55 (i < adg->clkout_size) && \ 56 ((pos) = adg->clkout[i]); \ 57 i++) 58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 59 60 static const char * const clkin_name_gen4[] = { 61 [CLKA] = "clkin", 62 }; 63 64 static const char * const clkin_name_gen2[] = { 65 [CLKA] = "clk_a", 66 [CLKB] = "clk_b", 67 [CLKC] = "clk_c", 68 [CLKI] = "clk_i", 69 }; 70 71 static const char * const clkout_name_gen2[] = { 72 [CLKOUT] = "audio_clkout", 73 [CLKOUT1] = "audio_clkout1", 74 [CLKOUT2] = "audio_clkout2", 75 [CLKOUT3] = "audio_clkout3", 76 }; 77 78 static u32 rsnd_adg_calculate_brgx(unsigned long div) 79 { 80 int i; 81 82 if (!div) 83 return 0; 84 85 for (i = 3; i >= 0; i--) { 86 int ratio = 2 << (i * 2); 87 if (0 == (div % ratio)) 88 return (u32)((i << 8) | ((div / ratio) - 1)); 89 } 90 91 return ~0; 92 } 93 94 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 95 { 96 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 97 int id = rsnd_mod_id(ssi_mod); 98 int ws = id; 99 100 if (rsnd_ssi_is_pin_sharing(io)) { 101 switch (id) { 102 case 1: 103 case 2: 104 case 9: 105 ws = 0; 106 break; 107 case 4: 108 ws = 3; 109 break; 110 case 8: 111 ws = 7; 112 break; 113 } 114 } 115 116 return (0x6 + ws) << 8; 117 } 118 119 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 120 struct rsnd_dai_stream *io, 121 unsigned int target_rate, 122 unsigned int *target_val, 123 unsigned int *target_en) 124 { 125 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 126 struct device *dev = rsnd_priv_to_dev(priv); 127 int sel; 128 unsigned int val, en; 129 unsigned int min, diff; 130 unsigned int sel_rate[] = { 131 adg->clkin_rate[CLKA], /* 0000: CLKA */ 132 adg->clkin_rate[CLKB], /* 0001: CLKB */ 133 adg->clkin_rate[CLKC], /* 0010: CLKC */ 134 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */ 135 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */ 136 }; 137 138 min = ~0; 139 val = 0; 140 en = 0; 141 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 142 int idx = 0; 143 int step = 2; 144 int div; 145 146 if (!sel_rate[sel]) 147 continue; 148 149 for (div = 2; div <= 98304; div += step) { 150 diff = abs(target_rate - sel_rate[sel] / div); 151 if (min > diff) { 152 val = (sel << 8) | idx; 153 min = diff; 154 en = 1 << (sel + 1); /* fixme */ 155 } 156 157 /* 158 * step of 0_0000 / 0_0001 / 0_1101 159 * are out of order 160 */ 161 if ((idx > 2) && (idx % 2)) 162 step *= 2; 163 if (idx == 0x1c) { 164 div += step; 165 step *= 2; 166 } 167 idx++; 168 } 169 } 170 171 if (min == ~0) { 172 dev_err(dev, "no Input clock\n"); 173 return; 174 } 175 176 *target_val = val; 177 if (target_en) 178 *target_en = en; 179 } 180 181 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 182 struct rsnd_dai_stream *io, 183 unsigned int in_rate, 184 unsigned int out_rate, 185 u32 *in, u32 *out, u32 *en) 186 { 187 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); 188 unsigned int target_rate; 189 u32 *target_val; 190 u32 _in; 191 u32 _out; 192 u32 _en; 193 194 /* default = SSI WS */ 195 _in = 196 _out = rsnd_adg_ssi_ws_timing_gen2(io); 197 198 target_rate = 0; 199 target_val = NULL; 200 _en = 0; 201 if (runtime->rate != in_rate) { 202 target_rate = out_rate; 203 target_val = &_out; 204 } else if (runtime->rate != out_rate) { 205 target_rate = in_rate; 206 target_val = &_in; 207 } 208 209 if (target_rate) 210 __rsnd_adg_get_timesel_ratio(priv, io, 211 target_rate, 212 target_val, &_en); 213 214 if (in) 215 *in = _in; 216 if (out) 217 *out = _out; 218 if (en) 219 *en = _en; 220 } 221 222 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 223 struct rsnd_dai_stream *io) 224 { 225 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 226 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 227 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 228 int id = rsnd_mod_id(cmd_mod); 229 int shift = (id % 2) ? 16 : 0; 230 u32 mask, val; 231 232 rsnd_adg_get_timesel_ratio(priv, io, 233 rsnd_src_get_in_rate(priv, io), 234 rsnd_src_get_out_rate(priv, io), 235 NULL, &val, NULL); 236 237 val = val << shift; 238 mask = 0x0f1f << shift; 239 240 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 241 242 return 0; 243 } 244 245 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, 246 struct rsnd_dai_stream *io, 247 unsigned int in_rate, 248 unsigned int out_rate) 249 { 250 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 251 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 252 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 253 u32 in, out; 254 u32 mask, en; 255 int id = rsnd_mod_id(src_mod); 256 int shift = (id % 2) ? 16 : 0; 257 258 rsnd_mod_confirm_src(src_mod); 259 260 rsnd_adg_get_timesel_ratio(priv, io, 261 in_rate, out_rate, 262 &in, &out, &en); 263 264 in = in << shift; 265 out = out << shift; 266 mask = 0x0f1f << shift; 267 268 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in); 269 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out); 270 271 if (en) 272 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 273 274 return 0; 275 } 276 277 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 278 { 279 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 280 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 281 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 282 struct device *dev = rsnd_priv_to_dev(priv); 283 int id = rsnd_mod_id(ssi_mod); 284 int shift = (id % 4) * 8; 285 u32 mask = 0xFF << shift; 286 287 rsnd_mod_confirm_ssi(ssi_mod); 288 289 val = val << shift; 290 291 /* 292 * SSI 8 is not connected to ADG. 293 * it works with SSI 7 294 */ 295 if (id == 8) 296 return; 297 298 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); 299 300 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); 301 } 302 303 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) 304 { 305 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 306 struct clk *clk; 307 int i; 308 int sel_table[] = { 309 [CLKA] = 0x1, 310 [CLKB] = 0x2, 311 [CLKC] = 0x3, 312 [CLKI] = 0x0, 313 }; 314 315 /* 316 * find suitable clock from 317 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 318 */ 319 for_each_rsnd_clkin(clk, adg, i) 320 if (rate == adg->clkin_rate[i]) 321 return sel_table[i]; 322 323 /* 324 * find divided clock from BRGA/BRGB 325 */ 326 if (rate == adg->brg_rate[ADG_HZ_441]) 327 return 0x10; 328 329 if (rate == adg->brg_rate[ADG_HZ_48]) 330 return 0x20; 331 332 return -EIO; 333 } 334 335 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 336 { 337 rsnd_adg_set_ssi_clk(ssi_mod, 0); 338 339 return 0; 340 } 341 342 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 343 { 344 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 345 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 346 struct device *dev = rsnd_priv_to_dev(priv); 347 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 348 int data; 349 u32 ckr = 0; 350 351 data = rsnd_adg_clk_query(priv, rate); 352 if (data < 0) 353 return data; 354 355 rsnd_adg_set_ssi_clk(ssi_mod, data); 356 357 if (0 == (rate % 8000)) 358 ckr = 0x80000000; /* BRGB output = 48kHz */ 359 360 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); 361 rsnd_mod_write(adg_mod, BRRA, adg->brga); 362 rsnd_mod_write(adg_mod, BRRB, adg->brgb); 363 364 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", 365 (ckr) ? 'B' : 'A', 366 (ckr) ? adg->brg_rate[ADG_HZ_48] : 367 adg->brg_rate[ADG_HZ_441]); 368 369 return 0; 370 } 371 372 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) 373 { 374 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 375 struct clk *clk; 376 int i; 377 378 for_each_rsnd_clkin(clk, adg, i) { 379 if (enable) { 380 clk_prepare_enable(clk); 381 382 /* 383 * We shouldn't use clk_get_rate() under 384 * atomic context. Let's keep it when 385 * rsnd_adg_clk_enable() was called 386 */ 387 adg->clkin_rate[i] = clk_get_rate(clk); 388 } else { 389 clk_disable_unprepare(clk); 390 } 391 } 392 } 393 394 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv, 395 const char * const name, 396 const char *parent) 397 { 398 struct device *dev = rsnd_priv_to_dev(priv); 399 struct clk *clk; 400 401 clk = clk_register_fixed_rate(dev, name, parent, 0, 0); 402 if (IS_ERR_OR_NULL(clk)) { 403 dev_err(dev, "create null clk error\n"); 404 return ERR_CAST(clk); 405 } 406 407 return clk; 408 } 409 410 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv) 411 { 412 struct rsnd_adg *adg = priv->adg; 413 414 if (!adg->null_clk) { 415 static const char * const name = "rsnd_adg_null"; 416 417 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL); 418 } 419 420 return adg->null_clk; 421 } 422 423 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv) 424 { 425 struct rsnd_adg *adg = priv->adg; 426 427 if (adg->null_clk) 428 clk_unregister_fixed_rate(adg->null_clk); 429 } 430 431 static int rsnd_adg_get_clkin(struct rsnd_priv *priv) 432 { 433 struct rsnd_adg *adg = priv->adg; 434 struct device *dev = rsnd_priv_to_dev(priv); 435 struct clk *clk; 436 const char * const *clkin_name; 437 int clkin_size; 438 int i; 439 440 clkin_name = clkin_name_gen2; 441 clkin_size = ARRAY_SIZE(clkin_name_gen2); 442 if (rsnd_is_gen4(priv)) { 443 clkin_name = clkin_name_gen4; 444 clkin_size = ARRAY_SIZE(clkin_name_gen4); 445 } 446 447 for (i = 0; i < clkin_size; i++) { 448 clk = devm_clk_get(dev, clkin_name[i]); 449 450 if (IS_ERR_OR_NULL(clk)) 451 clk = rsnd_adg_null_clk_get(priv); 452 if (IS_ERR_OR_NULL(clk)) 453 goto err; 454 455 adg->clkin[i] = clk; 456 } 457 458 adg->clkin_size = clkin_size; 459 460 return 0; 461 462 err: 463 dev_err(dev, "adg clock IN get failed\n"); 464 465 rsnd_adg_null_clk_clean(priv); 466 467 return -EIO; 468 } 469 470 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv) 471 { 472 struct rsnd_adg *adg = priv->adg; 473 struct clk *clk; 474 int i; 475 476 for_each_rsnd_clkout(clk, adg, i) 477 clk_unregister_fixed_rate(clk); 478 } 479 480 static int rsnd_adg_get_clkout(struct rsnd_priv *priv) 481 { 482 struct rsnd_adg *adg = priv->adg; 483 struct clk *clk; 484 struct device *dev = rsnd_priv_to_dev(priv); 485 struct device_node *np = dev->of_node; 486 struct property *prop; 487 u32 ckr, brgx, brga, brgb; 488 u32 rate, div; 489 u32 req_rate[ADG_HZ_SIZE] = {}; 490 uint32_t count = 0; 491 unsigned long req_Hz[ADG_HZ_SIZE]; 492 int clkout_size; 493 int i, req_size; 494 const char *parent_clk_name = NULL; 495 const char * const *clkout_name; 496 int brg_table[] = { 497 [CLKA] = 0x0, 498 [CLKB] = 0x1, 499 [CLKC] = 0x4, 500 [CLKI] = 0x2, 501 }; 502 503 ckr = 0; 504 brga = 2; /* default 1/6 */ 505 brgb = 2; /* default 1/6 */ 506 507 /* 508 * ADG supports BRRA/BRRB output only 509 * this means all clkout0/1/2/3 will be same rate 510 */ 511 prop = of_find_property(np, "clock-frequency", NULL); 512 if (!prop) 513 goto rsnd_adg_get_clkout_end; 514 515 req_size = prop->length / sizeof(u32); 516 if (req_size > ADG_HZ_SIZE) { 517 dev_err(dev, "too many clock-frequency\n"); 518 return -EINVAL; 519 } 520 521 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); 522 req_Hz[ADG_HZ_48] = 0; 523 req_Hz[ADG_HZ_441] = 0; 524 for (i = 0; i < req_size; i++) { 525 if (0 == (req_rate[i] % 44100)) 526 req_Hz[ADG_HZ_441] = req_rate[i]; 527 if (0 == (req_rate[i] % 48000)) 528 req_Hz[ADG_HZ_48] = req_rate[i]; 529 } 530 531 /* 532 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 533 * have 44.1kHz or 48kHz base clocks for now. 534 * 535 * SSI itself can divide parent clock by 1/1 - 1/16 536 * see 537 * rsnd_adg_ssi_clk_try_start() 538 * rsnd_ssi_master_clk_start() 539 */ 540 for_each_rsnd_clkin(clk, adg, i) { 541 rate = clk_get_rate(clk); 542 543 if (0 == rate) /* not used */ 544 continue; 545 546 /* BRGA */ 547 if (!adg->brg_rate[ADG_HZ_441] && (0 == rate % 44100)) { 548 div = 6; 549 if (req_Hz[ADG_HZ_441]) 550 div = rate / req_Hz[ADG_HZ_441]; 551 brgx = rsnd_adg_calculate_brgx(div); 552 if (BRRx_MASK(brgx) == brgx) { 553 brga = brgx; 554 adg->brg_rate[ADG_HZ_441] = rate / div; 555 ckr |= brg_table[i] << 20; 556 if (req_Hz[ADG_HZ_441]) 557 parent_clk_name = __clk_get_name(clk); 558 } 559 } 560 561 /* BRGB */ 562 if (!adg->brg_rate[ADG_HZ_48] && (0 == rate % 48000)) { 563 div = 6; 564 if (req_Hz[ADG_HZ_48]) 565 div = rate / req_Hz[ADG_HZ_48]; 566 brgx = rsnd_adg_calculate_brgx(div); 567 if (BRRx_MASK(brgx) == brgx) { 568 brgb = brgx; 569 adg->brg_rate[ADG_HZ_48] = rate / div; 570 ckr |= brg_table[i] << 16; 571 if (req_Hz[ADG_HZ_48]) 572 parent_clk_name = __clk_get_name(clk); 573 } 574 } 575 } 576 577 clkout_name = clkout_name_gen2; 578 clkout_size = ARRAY_SIZE(clkout_name_gen2); 579 if (rsnd_is_gen4(priv)) 580 clkout_size = 1; /* reuse clkout_name_gen2[] */ 581 582 /* 583 * ADG supports BRRA/BRRB output only. 584 * this means all clkout0/1/2/3 will be * same rate 585 */ 586 587 of_property_read_u32(np, "#clock-cells", &count); 588 /* 589 * for clkout 590 */ 591 if (!count) { 592 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 593 parent_clk_name, 0, req_rate[0]); 594 if (IS_ERR_OR_NULL(clk)) 595 goto err; 596 597 adg->clkout[CLKOUT] = clk; 598 adg->clkout_size = 1; 599 of_clk_add_provider(np, of_clk_src_simple_get, clk); 600 } 601 /* 602 * for clkout0/1/2/3 603 */ 604 else { 605 for (i = 0; i < clkout_size; i++) { 606 clk = clk_register_fixed_rate(dev, clkout_name[i], 607 parent_clk_name, 0, 608 req_rate[0]); 609 if (IS_ERR_OR_NULL(clk)) 610 goto err; 611 612 adg->clkout[i] = clk; 613 } 614 adg->onecell.clks = adg->clkout; 615 adg->onecell.clk_num = clkout_size; 616 adg->clkout_size = clkout_size; 617 of_clk_add_provider(np, of_clk_src_onecell_get, 618 &adg->onecell); 619 } 620 621 rsnd_adg_get_clkout_end: 622 adg->ckr = ckr; 623 adg->brga = brga; 624 adg->brgb = brgb; 625 626 return 0; 627 628 err: 629 dev_err(dev, "adg clock OUT get failed\n"); 630 631 rsnd_adg_unregister_clkout(priv); 632 633 return -EIO; 634 } 635 636 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS) 637 __printf(3, 4) 638 static void dbg_msg(struct device *dev, struct seq_file *m, 639 const char *fmt, ...) 640 { 641 char msg[128]; 642 va_list args; 643 644 va_start(args, fmt); 645 vsnprintf(msg, sizeof(msg), fmt, args); 646 va_end(args); 647 648 if (m) 649 seq_puts(m, msg); 650 else 651 dev_dbg(dev, "%s", msg); 652 } 653 654 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m) 655 { 656 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 657 struct device *dev = rsnd_priv_to_dev(priv); 658 struct clk *clk; 659 int i; 660 661 for_each_rsnd_clkin(clk, adg, i) 662 dbg_msg(dev, m, "%-18s : %pa : %ld\n", 663 __clk_get_name(clk), clk, clk_get_rate(clk)); 664 665 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 666 adg->ckr, adg->brga, adg->brgb); 667 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]); 668 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]); 669 670 /* 671 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() 672 * by BRGCKR::BRGCKR_31 673 */ 674 for_each_rsnd_clkout(clk, adg, i) 675 dbg_msg(dev, m, "%-18s : %pa : %ld\n", 676 __clk_get_name(clk), clk, clk_get_rate(clk)); 677 } 678 #else 679 #define rsnd_adg_clk_dbg_info(priv, m) 680 #endif 681 682 int rsnd_adg_probe(struct rsnd_priv *priv) 683 { 684 struct rsnd_adg *adg; 685 struct device *dev = rsnd_priv_to_dev(priv); 686 int ret; 687 688 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 689 if (!adg) 690 return -ENOMEM; 691 692 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, 693 NULL, 0, 0); 694 if (ret) 695 return ret; 696 697 priv->adg = adg; 698 699 ret = rsnd_adg_get_clkin(priv); 700 if (ret) 701 return ret; 702 703 ret = rsnd_adg_get_clkout(priv); 704 if (ret) 705 return ret; 706 707 rsnd_adg_clk_enable(priv); 708 rsnd_adg_clk_dbg_info(priv, NULL); 709 710 return 0; 711 } 712 713 void rsnd_adg_remove(struct rsnd_priv *priv) 714 { 715 struct device *dev = rsnd_priv_to_dev(priv); 716 struct device_node *np = dev->of_node; 717 718 rsnd_adg_unregister_clkout(priv); 719 720 of_clk_del_provider(np); 721 722 rsnd_adg_clk_disable(priv); 723 724 /* It should be called after rsnd_adg_clk_disable() */ 725 rsnd_adg_null_clk_clean(priv); 726 } 727