1 /* 2 * Helper routines for R-Car sound ADG. 3 * 4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/clk-provider.h> 11 #include "rsnd.h" 12 13 #define CLKA 0 14 #define CLKB 1 15 #define CLKC 2 16 #define CLKI 3 17 #define CLKMAX 4 18 19 #define CLKOUT 0 20 #define CLKOUT1 1 21 #define CLKOUT2 2 22 #define CLKOUT3 3 23 #define CLKOUTMAX 4 24 25 #define BRRx_MASK(x) (0x3FF & x) 26 27 static struct rsnd_mod_ops adg_ops = { 28 .name = "adg", 29 }; 30 31 struct rsnd_adg { 32 struct clk *clk[CLKMAX]; 33 struct clk *clkout[CLKOUTMAX]; 34 struct clk_onecell_data onecell; 35 struct rsnd_mod mod; 36 37 int rbga_rate_for_441khz; /* RBGA */ 38 int rbgb_rate_for_48khz; /* RBGB */ 39 }; 40 41 #define for_each_rsnd_clk(pos, adg, i) \ 42 for (i = 0; \ 43 (i < CLKMAX) && \ 44 ((pos) = adg->clk[i]); \ 45 i++) 46 #define for_each_rsnd_clkout(pos, adg, i) \ 47 for (i = 0; \ 48 (i < CLKOUTMAX) && \ 49 ((pos) = adg->clkout[i]); \ 50 i++) 51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 52 53 static u32 rsnd_adg_calculate_rbgx(unsigned long div) 54 { 55 int i, ratio; 56 57 if (!div) 58 return 0; 59 60 for (i = 3; i >= 0; i--) { 61 ratio = 2 << (i * 2); 62 if (0 == (div % ratio)) 63 return (u32)((i << 8) | ((div / ratio) - 1)); 64 } 65 66 return ~0; 67 } 68 69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 70 { 71 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 72 int id = rsnd_mod_id(ssi_mod); 73 int ws = id; 74 75 if (rsnd_ssi_is_pin_sharing(io)) { 76 switch (id) { 77 case 1: 78 case 2: 79 ws = 0; 80 break; 81 case 4: 82 ws = 3; 83 break; 84 case 8: 85 ws = 7; 86 break; 87 } 88 } 89 90 return (0x6 + ws) << 8; 91 } 92 93 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 94 struct rsnd_dai_stream *io) 95 { 96 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 97 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 98 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 99 int id = rsnd_mod_id(cmd_mod); 100 int shift = (id % 2) ? 16 : 0; 101 u32 mask, val; 102 103 val = rsnd_adg_ssi_ws_timing_gen2(io); 104 105 val = val << shift; 106 mask = 0xffff << shift; 107 108 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 109 110 return 0; 111 } 112 113 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod, 114 struct rsnd_dai_stream *io, 115 u32 timsel) 116 { 117 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 118 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 119 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 120 int is_play = rsnd_io_is_play(io); 121 int id = rsnd_mod_id(src_mod); 122 int shift = (id % 2) ? 16 : 0; 123 u32 mask, ws; 124 u32 in, out; 125 126 rsnd_mod_confirm_src(src_mod); 127 128 ws = rsnd_adg_ssi_ws_timing_gen2(io); 129 130 in = (is_play) ? timsel : ws; 131 out = (is_play) ? ws : timsel; 132 133 in = in << shift; 134 out = out << shift; 135 mask = 0xffff << shift; 136 137 switch (id / 2) { 138 case 0: 139 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in); 140 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out); 141 break; 142 case 1: 143 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in); 144 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out); 145 break; 146 case 2: 147 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in); 148 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out); 149 break; 150 case 3: 151 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in); 152 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out); 153 break; 154 case 4: 155 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in); 156 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out); 157 break; 158 } 159 160 return 0; 161 } 162 163 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod, 164 struct rsnd_dai_stream *io, 165 unsigned int src_rate, 166 unsigned int dst_rate) 167 { 168 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 169 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 170 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 171 struct device *dev = rsnd_priv_to_dev(priv); 172 int idx, sel, div, step, ret; 173 u32 val, en; 174 unsigned int min, diff; 175 unsigned int sel_rate [] = { 176 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 177 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ 178 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ 179 adg->rbga_rate_for_441khz, /* 0011: RBGA */ 180 adg->rbgb_rate_for_48khz, /* 0100: RBGB */ 181 }; 182 183 rsnd_mod_confirm_src(src_mod); 184 185 min = ~0; 186 val = 0; 187 en = 0; 188 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 189 idx = 0; 190 step = 2; 191 192 if (!sel_rate[sel]) 193 continue; 194 195 for (div = 2; div <= 98304; div += step) { 196 diff = abs(src_rate - sel_rate[sel] / div); 197 if (min > diff) { 198 val = (sel << 8) | idx; 199 min = diff; 200 en = 1 << (sel + 1); /* fixme */ 201 } 202 203 /* 204 * step of 0_0000 / 0_0001 / 0_1101 205 * are out of order 206 */ 207 if ((idx > 2) && (idx % 2)) 208 step *= 2; 209 if (idx == 0x1c) { 210 div += step; 211 step *= 2; 212 } 213 idx++; 214 } 215 } 216 217 if (min == ~0) { 218 dev_err(dev, "no Input clock\n"); 219 return -EIO; 220 } 221 222 ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val); 223 if (ret < 0) { 224 dev_err(dev, "timsel error\n"); 225 return ret; 226 } 227 228 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 229 230 dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate); 231 232 return 0; 233 } 234 235 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod, 236 struct rsnd_dai_stream *io) 237 { 238 u32 val = rsnd_adg_ssi_ws_timing_gen2(io); 239 240 rsnd_mod_confirm_src(src_mod); 241 242 return rsnd_adg_set_src_timsel_gen2(src_mod, io, val); 243 } 244 245 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 246 { 247 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 248 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 249 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 250 int id = rsnd_mod_id(ssi_mod); 251 int shift = (id % 4) * 8; 252 u32 mask = 0xFF << shift; 253 254 rsnd_mod_confirm_ssi(ssi_mod); 255 256 val = val << shift; 257 258 /* 259 * SSI 8 is not connected to ADG. 260 * it works with SSI 7 261 */ 262 if (id == 8) 263 return; 264 265 switch (id / 4) { 266 case 0: 267 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val); 268 break; 269 case 1: 270 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val); 271 break; 272 case 2: 273 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val); 274 break; 275 } 276 } 277 278 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 279 { 280 rsnd_adg_set_ssi_clk(ssi_mod, 0); 281 282 return 0; 283 } 284 285 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 286 { 287 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 288 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 289 struct device *dev = rsnd_priv_to_dev(priv); 290 struct clk *clk; 291 int i; 292 u32 data; 293 int sel_table[] = { 294 [CLKA] = 0x1, 295 [CLKB] = 0x2, 296 [CLKC] = 0x3, 297 [CLKI] = 0x0, 298 }; 299 300 dev_dbg(dev, "request clock = %d\n", rate); 301 302 /* 303 * find suitable clock from 304 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 305 */ 306 data = 0; 307 for_each_rsnd_clk(clk, adg, i) { 308 if (rate == clk_get_rate(clk)) { 309 data = sel_table[i]; 310 goto found_clock; 311 } 312 } 313 314 /* 315 * find divided clock from BRGA/BRGB 316 */ 317 if (rate == adg->rbga_rate_for_441khz) { 318 data = 0x10; 319 goto found_clock; 320 } 321 322 if (rate == adg->rbgb_rate_for_48khz) { 323 data = 0x20; 324 goto found_clock; 325 } 326 327 return -EIO; 328 329 found_clock: 330 331 rsnd_adg_set_ssi_clk(ssi_mod, data); 332 333 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n", 334 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod), 335 data, rate); 336 337 return 0; 338 } 339 340 static void rsnd_adg_get_clkin(struct rsnd_priv *priv, 341 struct rsnd_adg *adg) 342 { 343 struct device *dev = rsnd_priv_to_dev(priv); 344 struct clk *clk; 345 static const char * const clk_name[] = { 346 [CLKA] = "clk_a", 347 [CLKB] = "clk_b", 348 [CLKC] = "clk_c", 349 [CLKI] = "clk_i", 350 }; 351 int i, ret; 352 353 for (i = 0; i < CLKMAX; i++) { 354 clk = devm_clk_get(dev, clk_name[i]); 355 adg->clk[i] = IS_ERR(clk) ? NULL : clk; 356 } 357 358 for_each_rsnd_clk(clk, adg, i) { 359 ret = clk_prepare_enable(clk); 360 if (ret < 0) 361 dev_warn(dev, "can't use clk %d\n", i); 362 363 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk)); 364 } 365 } 366 367 static void rsnd_adg_get_clkout(struct rsnd_priv *priv, 368 struct rsnd_adg *adg) 369 { 370 struct clk *clk; 371 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 372 struct device *dev = rsnd_priv_to_dev(priv); 373 struct device_node *np = dev->of_node; 374 u32 ckr, rbgx, rbga, rbgb; 375 u32 rate, req_rate = 0, div; 376 uint32_t count = 0; 377 unsigned long req_48kHz_rate, req_441kHz_rate; 378 int i; 379 const char *parent_clk_name = NULL; 380 static const char * const clkout_name[] = { 381 [CLKOUT] = "audio_clkout", 382 [CLKOUT1] = "audio_clkout1", 383 [CLKOUT2] = "audio_clkout2", 384 [CLKOUT3] = "audio_clkout3", 385 }; 386 int brg_table[] = { 387 [CLKA] = 0x0, 388 [CLKB] = 0x1, 389 [CLKC] = 0x4, 390 [CLKI] = 0x2, 391 }; 392 393 of_property_read_u32(np, "#clock-cells", &count); 394 395 /* 396 * ADG supports BRRA/BRRB output only 397 * this means all clkout0/1/2/3 will be same rate 398 */ 399 of_property_read_u32(np, "clock-frequency", &req_rate); 400 req_48kHz_rate = 0; 401 req_441kHz_rate = 0; 402 if (0 == (req_rate % 44100)) 403 req_441kHz_rate = req_rate; 404 if (0 == (req_rate % 48000)) 405 req_48kHz_rate = req_rate; 406 407 /* 408 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 409 * have 44.1kHz or 48kHz base clocks for now. 410 * 411 * SSI itself can divide parent clock by 1/1 - 1/16 412 * see 413 * rsnd_adg_ssi_clk_try_start() 414 * rsnd_ssi_master_clk_start() 415 */ 416 ckr = 0; 417 rbga = 2; /* default 1/6 */ 418 rbgb = 2; /* default 1/6 */ 419 adg->rbga_rate_for_441khz = 0; 420 adg->rbgb_rate_for_48khz = 0; 421 for_each_rsnd_clk(clk, adg, i) { 422 rate = clk_get_rate(clk); 423 424 if (0 == rate) /* not used */ 425 continue; 426 427 /* RBGA */ 428 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { 429 div = 6; 430 if (req_441kHz_rate) 431 div = rate / req_441kHz_rate; 432 rbgx = rsnd_adg_calculate_rbgx(div); 433 if (BRRx_MASK(rbgx) == rbgx) { 434 rbga = rbgx; 435 adg->rbga_rate_for_441khz = rate / div; 436 ckr |= brg_table[i] << 20; 437 if (req_441kHz_rate) 438 parent_clk_name = __clk_get_name(clk); 439 } 440 } 441 442 /* RBGB */ 443 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { 444 div = 6; 445 if (req_48kHz_rate) 446 div = rate / req_48kHz_rate; 447 rbgx = rsnd_adg_calculate_rbgx(div); 448 if (BRRx_MASK(rbgx) == rbgx) { 449 rbgb = rbgx; 450 adg->rbgb_rate_for_48khz = rate / div; 451 ckr |= brg_table[i] << 16; 452 if (req_48kHz_rate) { 453 parent_clk_name = __clk_get_name(clk); 454 ckr |= 0x80000000; 455 } 456 } 457 } 458 } 459 460 /* 461 * ADG supports BRRA/BRRB output only. 462 * this means all clkout0/1/2/3 will be * same rate 463 */ 464 465 /* 466 * for clkout 467 */ 468 if (!count) { 469 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 470 parent_clk_name, 471 (parent_clk_name) ? 472 0 : CLK_IS_ROOT, req_rate); 473 if (!IS_ERR(clk)) { 474 adg->clkout[CLKOUT] = clk; 475 of_clk_add_provider(np, of_clk_src_simple_get, clk); 476 } 477 } 478 /* 479 * for clkout0/1/2/3 480 */ 481 else { 482 for (i = 0; i < CLKOUTMAX; i++) { 483 clk = clk_register_fixed_rate(dev, clkout_name[i], 484 parent_clk_name, 485 (parent_clk_name) ? 486 0 : CLK_IS_ROOT, 487 req_rate); 488 if (!IS_ERR(clk)) { 489 adg->onecell.clks = adg->clkout; 490 adg->onecell.clk_num = CLKOUTMAX; 491 492 adg->clkout[i] = clk; 493 494 of_clk_add_provider(np, of_clk_src_onecell_get, 495 &adg->onecell); 496 } 497 } 498 } 499 500 rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr); 501 rsnd_mod_write(adg_mod, BRRA, rbga); 502 rsnd_mod_write(adg_mod, BRRB, rbgb); 503 504 for_each_rsnd_clkout(clk, adg, i) 505 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); 506 dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 507 ckr, rbga, rbgb); 508 } 509 510 int rsnd_adg_probe(struct rsnd_priv *priv) 511 { 512 struct rsnd_adg *adg; 513 struct device *dev = rsnd_priv_to_dev(priv); 514 515 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 516 if (!adg) { 517 dev_err(dev, "ADG allocate failed\n"); 518 return -ENOMEM; 519 } 520 521 /* 522 * ADG is special module. 523 * Use ADG mod without rsnd_mod_init() to make debug easy 524 * for rsnd_write/rsnd_read 525 */ 526 adg->mod.ops = &adg_ops; 527 adg->mod.priv = priv; 528 529 rsnd_adg_get_clkin(priv, adg); 530 rsnd_adg_get_clkout(priv, adg); 531 532 priv->adg = adg; 533 534 return 0; 535 } 536 537 void rsnd_adg_remove(struct rsnd_priv *priv) 538 { 539 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 540 struct clk *clk; 541 int i; 542 543 for_each_rsnd_clk(clk, adg, i) { 544 clk_disable_unprepare(clk); 545 } 546 } 547