1 /* 2 * Helper routines for R-Car sound ADG. 3 * 4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/sh_clk.h> 11 #include "rsnd.h" 12 13 #define CLKA 0 14 #define CLKB 1 15 #define CLKC 2 16 #define CLKI 3 17 #define CLKMAX 4 18 19 struct rsnd_adg { 20 struct clk *clk[CLKMAX]; 21 22 int rbga_rate_for_441khz_div_6; /* RBGA */ 23 int rbgb_rate_for_48khz_div_6; /* RBGB */ 24 u32 ckr; 25 }; 26 27 #define for_each_rsnd_clk(pos, adg, i) \ 28 for (i = 0; \ 29 (i < CLKMAX) && \ 30 ((pos) = adg->clk[i]); \ 31 i++) 32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 33 34 35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 36 { 37 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io); 38 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 39 int id = rsnd_mod_id(mod); 40 int ws = id; 41 42 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) { 43 switch (id) { 44 case 1: 45 case 2: 46 ws = 0; 47 break; 48 case 4: 49 ws = 3; 50 break; 51 case 8: 52 ws = 7; 53 break; 54 } 55 } 56 57 return (0x6 + ws) << 8; 58 } 59 60 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai, 61 struct rsnd_mod *mod, 62 struct rsnd_dai_stream *io, 63 u32 timsel) 64 { 65 int is_play = rsnd_dai_is_play(rdai, io); 66 int id = rsnd_mod_id(mod); 67 int shift = (id % 2) ? 16 : 0; 68 u32 mask, ws; 69 u32 in, out; 70 71 ws = rsnd_adg_ssi_ws_timing_gen2(io); 72 73 in = (is_play) ? timsel : ws; 74 out = (is_play) ? ws : timsel; 75 76 in = in << shift; 77 out = out << shift; 78 mask = 0xffff << shift; 79 80 switch (id / 2) { 81 case 0: 82 rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in); 83 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out); 84 break; 85 case 1: 86 rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in); 87 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out); 88 break; 89 case 2: 90 rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in); 91 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out); 92 break; 93 case 3: 94 rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in); 95 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out); 96 break; 97 case 4: 98 rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in); 99 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out); 100 break; 101 } 102 103 return 0; 104 } 105 106 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod, 107 struct rsnd_dai *rdai, 108 struct rsnd_dai_stream *io, 109 unsigned int src_rate, 110 unsigned int dst_rate) 111 { 112 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 113 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 114 struct device *dev = rsnd_priv_to_dev(priv); 115 int idx, sel, div, step, ret; 116 u32 val, en; 117 unsigned int min, diff; 118 unsigned int sel_rate [] = { 119 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 120 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ 121 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ 122 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */ 123 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */ 124 }; 125 126 min = ~0; 127 val = 0; 128 en = 0; 129 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 130 idx = 0; 131 step = 2; 132 133 if (!sel_rate[sel]) 134 continue; 135 136 for (div = 2; div <= 98304; div += step) { 137 diff = abs(src_rate - sel_rate[sel] / div); 138 if (min > diff) { 139 val = (sel << 8) | idx; 140 min = diff; 141 en = 1 << (sel + 1); /* fixme */ 142 } 143 144 /* 145 * step of 0_0000 / 0_0001 / 0_1101 146 * are out of order 147 */ 148 if ((idx > 2) && (idx % 2)) 149 step *= 2; 150 if (idx == 0x1c) { 151 div += step; 152 step *= 2; 153 } 154 idx++; 155 } 156 } 157 158 if (min == ~0) { 159 dev_err(dev, "no Input clock\n"); 160 return -EIO; 161 } 162 163 ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val); 164 if (ret < 0) { 165 dev_err(dev, "timsel error\n"); 166 return ret; 167 } 168 169 rsnd_mod_bset(mod, DIV_EN, en, en); 170 171 return 0; 172 } 173 174 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod, 175 struct rsnd_dai *rdai, 176 struct rsnd_dai_stream *io) 177 { 178 u32 val = rsnd_adg_ssi_ws_timing_gen2(io); 179 180 return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val); 181 } 182 183 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv, 184 struct rsnd_mod *mod, 185 unsigned int src_rate, 186 unsigned int dst_rate) 187 { 188 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 189 struct device *dev = rsnd_priv_to_dev(priv); 190 int idx, sel, div, shift; 191 u32 mask, val; 192 int id = rsnd_mod_id(mod); 193 unsigned int sel_rate [] = { 194 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */ 195 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */ 196 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */ 197 0, /* 011: MLBCLK (not used) */ 198 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */ 199 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */ 200 }; 201 202 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */ 203 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 204 for (div = 128, idx = 0; 205 div <= 2048; 206 div *= 2, idx++) { 207 if (src_rate == sel_rate[sel] / div) { 208 val = (idx << 4) | sel; 209 goto find_rate; 210 } 211 } 212 } 213 dev_err(dev, "can't find convert src clk\n"); 214 return -EINVAL; 215 216 find_rate: 217 shift = (id % 4) * 8; 218 mask = 0xFF << shift; 219 val = val << shift; 220 221 dev_dbg(dev, "adg convert src clk = %02x\n", val); 222 223 switch (id / 4) { 224 case 0: 225 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val); 226 break; 227 case 1: 228 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val); 229 break; 230 case 2: 231 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val); 232 break; 233 } 234 235 /* 236 * Gen1 doesn't need dst_rate settings, 237 * since it uses SSI WS pin. 238 * see also rsnd_src_set_route_if_gen1() 239 */ 240 241 return 0; 242 } 243 244 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val) 245 { 246 int id = rsnd_mod_id(mod); 247 int shift = (id % 4) * 8; 248 u32 mask = 0xFF << shift; 249 250 val = val << shift; 251 252 /* 253 * SSI 8 is not connected to ADG. 254 * it works with SSI 7 255 */ 256 if (id == 8) 257 return; 258 259 switch (id / 4) { 260 case 0: 261 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val); 262 break; 263 case 1: 264 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val); 265 break; 266 case 2: 267 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val); 268 break; 269 } 270 } 271 272 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod) 273 { 274 /* 275 * "mod" = "ssi" here. 276 * we can get "ssi id" from mod 277 */ 278 rsnd_adg_set_ssi_clk(mod, 0); 279 280 return 0; 281 } 282 283 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate) 284 { 285 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 286 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 287 struct device *dev = rsnd_priv_to_dev(priv); 288 struct clk *clk; 289 int i; 290 u32 data; 291 int sel_table[] = { 292 [CLKA] = 0x1, 293 [CLKB] = 0x2, 294 [CLKC] = 0x3, 295 [CLKI] = 0x0, 296 }; 297 298 dev_dbg(dev, "request clock = %d\n", rate); 299 300 /* 301 * find suitable clock from 302 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 303 */ 304 data = 0; 305 for_each_rsnd_clk(clk, adg, i) { 306 if (rate == clk_get_rate(clk)) { 307 data = sel_table[i]; 308 goto found_clock; 309 } 310 } 311 312 /* 313 * find 1/6 clock from BRGA/BRGB 314 */ 315 if (rate == adg->rbga_rate_for_441khz_div_6) { 316 data = 0x10; 317 goto found_clock; 318 } 319 320 if (rate == adg->rbgb_rate_for_48khz_div_6) { 321 data = 0x20; 322 goto found_clock; 323 } 324 325 return -EIO; 326 327 found_clock: 328 329 /* see rsnd_adg_ssi_clk_init() */ 330 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr); 331 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */ 332 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */ 333 334 /* 335 * This "mod" = "ssi" here. 336 * we can get "ssi id" from mod 337 */ 338 rsnd_adg_set_ssi_clk(mod, data); 339 340 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", 341 rsnd_mod_id(mod), i, rate); 342 343 return 0; 344 } 345 346 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg) 347 { 348 struct clk *clk; 349 unsigned long rate; 350 u32 ckr; 351 int i; 352 int brg_table[] = { 353 [CLKA] = 0x0, 354 [CLKB] = 0x1, 355 [CLKC] = 0x4, 356 [CLKI] = 0x2, 357 }; 358 359 /* 360 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 361 * have 44.1kHz or 48kHz base clocks for now. 362 * 363 * SSI itself can divide parent clock by 1/1 - 1/16 364 * So, BRGA outputs 44.1kHz base parent clock 1/32, 365 * and, BRGB outputs 48.0kHz base parent clock 1/32 here. 366 * see 367 * rsnd_adg_ssi_clk_try_start() 368 */ 369 ckr = 0; 370 adg->rbga_rate_for_441khz_div_6 = 0; 371 adg->rbgb_rate_for_48khz_div_6 = 0; 372 for_each_rsnd_clk(clk, adg, i) { 373 rate = clk_get_rate(clk); 374 375 if (0 == rate) /* not used */ 376 continue; 377 378 /* RBGA */ 379 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) { 380 adg->rbga_rate_for_441khz_div_6 = rate / 6; 381 ckr |= brg_table[i] << 20; 382 } 383 384 /* RBGB */ 385 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) { 386 adg->rbgb_rate_for_48khz_div_6 = rate / 6; 387 ckr |= brg_table[i] << 16; 388 } 389 } 390 391 adg->ckr = ckr; 392 } 393 394 int rsnd_adg_probe(struct platform_device *pdev, 395 const struct rsnd_of_data *of_data, 396 struct rsnd_priv *priv) 397 { 398 struct rsnd_adg *adg; 399 struct device *dev = rsnd_priv_to_dev(priv); 400 struct clk *clk, *clk_orig; 401 int i; 402 bool use_old_style = false; 403 404 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 405 if (!adg) { 406 dev_err(dev, "ADG allocate failed\n"); 407 return -ENOMEM; 408 } 409 410 clk_orig = devm_clk_get(dev, NULL); 411 adg->clk[CLKA] = devm_clk_get(dev, "clk_a"); 412 adg->clk[CLKB] = devm_clk_get(dev, "clk_b"); 413 adg->clk[CLKC] = devm_clk_get(dev, "clk_c"); 414 adg->clk[CLKI] = devm_clk_get(dev, "clk_i"); 415 416 /* 417 * It request device dependent audio clock. 418 * But above all clks will indicate rsnd module clock 419 * if platform doesn't it 420 */ 421 for_each_rsnd_clk(clk, adg, i) { 422 if (clk_orig == clk) { 423 dev_warn(dev, 424 "doesn't have device dependent clock, use independent clock\n"); 425 use_old_style = true; 426 break; 427 } 428 } 429 430 /* 431 * note: 432 * these exist in order to keep compatible with 433 * platform which has device independent audio clock, 434 * but will be removed soon 435 */ 436 if (use_old_style) { 437 adg->clk[CLKA] = devm_clk_get(NULL, "audio_clk_a"); 438 adg->clk[CLKB] = devm_clk_get(NULL, "audio_clk_b"); 439 adg->clk[CLKC] = devm_clk_get(NULL, "audio_clk_c"); 440 adg->clk[CLKI] = devm_clk_get(NULL, "audio_clk_internal"); 441 } 442 443 for_each_rsnd_clk(clk, adg, i) { 444 if (IS_ERR(clk)) { 445 dev_err(dev, "Audio clock failed\n"); 446 return -EIO; 447 } 448 } 449 450 rsnd_adg_ssi_clk_init(priv, adg); 451 452 priv->adg = adg; 453 454 dev_dbg(dev, "adg probed\n"); 455 456 return 0; 457 } 458