1 /* 2 * Helper routines for R-Car sound ADG. 3 * 4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/sh_clk.h> 11 #include "rsnd.h" 12 13 #define CLKA 0 14 #define CLKB 1 15 #define CLKC 2 16 #define CLKI 3 17 #define CLKMAX 4 18 19 struct rsnd_adg { 20 struct clk *clk[CLKMAX]; 21 22 int rbga_rate_for_441khz_div_6; /* RBGA */ 23 int rbgb_rate_for_48khz_div_6; /* RBGB */ 24 u32 ckr; 25 }; 26 27 #define for_each_rsnd_clk(pos, adg, i) \ 28 for (i = 0; \ 29 (i < CLKMAX) && \ 30 ((pos) = adg->clk[i]); \ 31 i++) 32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 33 34 35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 36 { 37 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io); 38 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 39 int id = rsnd_mod_id(mod); 40 int ws = id; 41 42 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) { 43 switch (id) { 44 case 1: 45 case 2: 46 ws = 0; 47 break; 48 case 4: 49 ws = 3; 50 break; 51 case 8: 52 ws = 7; 53 break; 54 } 55 } 56 57 return (0x6 + ws) << 8; 58 } 59 60 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod, 61 struct rsnd_dai_stream *io) 62 { 63 int id = rsnd_mod_id(mod); 64 int shift = (id % 2) ? 16 : 0; 65 u32 mask, val; 66 67 val = rsnd_adg_ssi_ws_timing_gen2(io); 68 69 val = val << shift; 70 mask = 0xffff << shift; 71 72 rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val); 73 74 return 0; 75 } 76 77 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *mod, 78 struct rsnd_dai_stream *io, 79 u32 timsel) 80 { 81 int is_play = rsnd_io_is_play(io); 82 int id = rsnd_mod_id(mod); 83 int shift = (id % 2) ? 16 : 0; 84 u32 mask, ws; 85 u32 in, out; 86 87 ws = rsnd_adg_ssi_ws_timing_gen2(io); 88 89 in = (is_play) ? timsel : ws; 90 out = (is_play) ? ws : timsel; 91 92 in = in << shift; 93 out = out << shift; 94 mask = 0xffff << shift; 95 96 switch (id / 2) { 97 case 0: 98 rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in); 99 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out); 100 break; 101 case 1: 102 rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in); 103 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out); 104 break; 105 case 2: 106 rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in); 107 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out); 108 break; 109 case 3: 110 rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in); 111 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out); 112 break; 113 case 4: 114 rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in); 115 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out); 116 break; 117 } 118 119 return 0; 120 } 121 122 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod, 123 struct rsnd_dai_stream *io, 124 unsigned int src_rate, 125 unsigned int dst_rate) 126 { 127 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 128 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 129 struct device *dev = rsnd_priv_to_dev(priv); 130 int idx, sel, div, step, ret; 131 u32 val, en; 132 unsigned int min, diff; 133 unsigned int sel_rate [] = { 134 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 135 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ 136 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ 137 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */ 138 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */ 139 }; 140 141 min = ~0; 142 val = 0; 143 en = 0; 144 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 145 idx = 0; 146 step = 2; 147 148 if (!sel_rate[sel]) 149 continue; 150 151 for (div = 2; div <= 98304; div += step) { 152 diff = abs(src_rate - sel_rate[sel] / div); 153 if (min > diff) { 154 val = (sel << 8) | idx; 155 min = diff; 156 en = 1 << (sel + 1); /* fixme */ 157 } 158 159 /* 160 * step of 0_0000 / 0_0001 / 0_1101 161 * are out of order 162 */ 163 if ((idx > 2) && (idx % 2)) 164 step *= 2; 165 if (idx == 0x1c) { 166 div += step; 167 step *= 2; 168 } 169 idx++; 170 } 171 } 172 173 if (min == ~0) { 174 dev_err(dev, "no Input clock\n"); 175 return -EIO; 176 } 177 178 ret = rsnd_adg_set_src_timsel_gen2(mod, io, val); 179 if (ret < 0) { 180 dev_err(dev, "timsel error\n"); 181 return ret; 182 } 183 184 rsnd_mod_bset(mod, DIV_EN, en, en); 185 186 return 0; 187 } 188 189 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod, 190 struct rsnd_dai_stream *io) 191 { 192 u32 val = rsnd_adg_ssi_ws_timing_gen2(io); 193 194 return rsnd_adg_set_src_timsel_gen2(mod, io, val); 195 } 196 197 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv, 198 struct rsnd_mod *mod, 199 unsigned int src_rate, 200 unsigned int dst_rate) 201 { 202 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 203 struct device *dev = rsnd_priv_to_dev(priv); 204 int idx, sel, div, shift; 205 u32 mask, val; 206 int id = rsnd_mod_id(mod); 207 unsigned int sel_rate [] = { 208 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */ 209 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */ 210 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */ 211 0, /* 011: MLBCLK (not used) */ 212 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */ 213 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */ 214 }; 215 216 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */ 217 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 218 for (div = 128, idx = 0; 219 div <= 2048; 220 div *= 2, idx++) { 221 if (src_rate == sel_rate[sel] / div) { 222 val = (idx << 4) | sel; 223 goto find_rate; 224 } 225 } 226 } 227 dev_err(dev, "can't find convert src clk\n"); 228 return -EINVAL; 229 230 find_rate: 231 shift = (id % 4) * 8; 232 mask = 0xFF << shift; 233 val = val << shift; 234 235 dev_dbg(dev, "adg convert src clk = %02x\n", val); 236 237 switch (id / 4) { 238 case 0: 239 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val); 240 break; 241 case 1: 242 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val); 243 break; 244 case 2: 245 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val); 246 break; 247 } 248 249 /* 250 * Gen1 doesn't need dst_rate settings, 251 * since it uses SSI WS pin. 252 * see also rsnd_src_set_route_if_gen1() 253 */ 254 255 return 0; 256 } 257 258 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val) 259 { 260 int id = rsnd_mod_id(mod); 261 int shift = (id % 4) * 8; 262 u32 mask = 0xFF << shift; 263 264 val = val << shift; 265 266 /* 267 * SSI 8 is not connected to ADG. 268 * it works with SSI 7 269 */ 270 if (id == 8) 271 return; 272 273 switch (id / 4) { 274 case 0: 275 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val); 276 break; 277 case 1: 278 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val); 279 break; 280 case 2: 281 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val); 282 break; 283 } 284 } 285 286 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod) 287 { 288 /* 289 * "mod" = "ssi" here. 290 * we can get "ssi id" from mod 291 */ 292 rsnd_adg_set_ssi_clk(mod, 0); 293 294 return 0; 295 } 296 297 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate) 298 { 299 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 300 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 301 struct device *dev = rsnd_priv_to_dev(priv); 302 struct clk *clk; 303 int i; 304 u32 data; 305 int sel_table[] = { 306 [CLKA] = 0x1, 307 [CLKB] = 0x2, 308 [CLKC] = 0x3, 309 [CLKI] = 0x0, 310 }; 311 312 dev_dbg(dev, "request clock = %d\n", rate); 313 314 /* 315 * find suitable clock from 316 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 317 */ 318 data = 0; 319 for_each_rsnd_clk(clk, adg, i) { 320 if (rate == clk_get_rate(clk)) { 321 data = sel_table[i]; 322 goto found_clock; 323 } 324 } 325 326 /* 327 * find 1/6 clock from BRGA/BRGB 328 */ 329 if (rate == adg->rbga_rate_for_441khz_div_6) { 330 data = 0x10; 331 goto found_clock; 332 } 333 334 if (rate == adg->rbgb_rate_for_48khz_div_6) { 335 data = 0x20; 336 goto found_clock; 337 } 338 339 return -EIO; 340 341 found_clock: 342 343 /* see rsnd_adg_ssi_clk_init() */ 344 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr); 345 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */ 346 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */ 347 348 /* 349 * This "mod" = "ssi" here. 350 * we can get "ssi id" from mod 351 */ 352 rsnd_adg_set_ssi_clk(mod, data); 353 354 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", 355 rsnd_mod_id(mod), i, rate); 356 357 return 0; 358 } 359 360 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg) 361 { 362 struct clk *clk; 363 unsigned long rate; 364 u32 ckr; 365 int i; 366 int brg_table[] = { 367 [CLKA] = 0x0, 368 [CLKB] = 0x1, 369 [CLKC] = 0x4, 370 [CLKI] = 0x2, 371 }; 372 373 /* 374 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 375 * have 44.1kHz or 48kHz base clocks for now. 376 * 377 * SSI itself can divide parent clock by 1/1 - 1/16 378 * So, BRGA outputs 44.1kHz base parent clock 1/32, 379 * and, BRGB outputs 48.0kHz base parent clock 1/32 here. 380 * see 381 * rsnd_adg_ssi_clk_try_start() 382 */ 383 ckr = 0; 384 adg->rbga_rate_for_441khz_div_6 = 0; 385 adg->rbgb_rate_for_48khz_div_6 = 0; 386 for_each_rsnd_clk(clk, adg, i) { 387 rate = clk_get_rate(clk); 388 389 if (0 == rate) /* not used */ 390 continue; 391 392 /* RBGA */ 393 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) { 394 adg->rbga_rate_for_441khz_div_6 = rate / 6; 395 ckr |= brg_table[i] << 20; 396 } 397 398 /* RBGB */ 399 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) { 400 adg->rbgb_rate_for_48khz_div_6 = rate / 6; 401 ckr |= brg_table[i] << 16; 402 } 403 } 404 405 adg->ckr = ckr; 406 } 407 408 int rsnd_adg_probe(struct platform_device *pdev, 409 const struct rsnd_of_data *of_data, 410 struct rsnd_priv *priv) 411 { 412 struct rsnd_adg *adg; 413 struct device *dev = rsnd_priv_to_dev(priv); 414 struct clk *clk; 415 int i; 416 417 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 418 if (!adg) { 419 dev_err(dev, "ADG allocate failed\n"); 420 return -ENOMEM; 421 } 422 423 adg->clk[CLKA] = devm_clk_get(dev, "clk_a"); 424 adg->clk[CLKB] = devm_clk_get(dev, "clk_b"); 425 adg->clk[CLKC] = devm_clk_get(dev, "clk_c"); 426 adg->clk[CLKI] = devm_clk_get(dev, "clk_i"); 427 428 for_each_rsnd_clk(clk, adg, i) 429 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk)); 430 431 rsnd_adg_ssi_clk_init(priv, adg); 432 433 priv->adg = adg; 434 435 dev_dbg(dev, "adg probed\n"); 436 437 return 0; 438 } 439