1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Helper routines for R-Car sound ADG.
4 //
5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include "rsnd.h"
9
10 #define CLKA 0
11 #define CLKB 1
12 #define CLKC 2
13 #define CLKI 3
14 #define CLKINMAX 4
15
16 #define CLKOUT 0
17 #define CLKOUT1 1
18 #define CLKOUT2 2
19 #define CLKOUT3 3
20 #define CLKOUTMAX 4
21
22 #define BRRx_MASK(x) (0x3FF & x)
23
24 static struct rsnd_mod_ops adg_ops = {
25 .name = "adg",
26 };
27
28 #define ADG_HZ_441 0
29 #define ADG_HZ_48 1
30 #define ADG_HZ_SIZE 2
31
32 struct rsnd_adg {
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
35 struct clk *null_clk;
36 struct clk_onecell_data onecell;
37 struct rsnd_mod mod;
38 int clkin_rate[CLKINMAX];
39 int clkin_size;
40 int clkout_size;
41 u32 ckr;
42 u32 brga;
43 u32 brgb;
44
45 int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */
46 };
47
48 #define for_each_rsnd_clkin(pos, adg, i) \
49 for (i = 0; \
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
52 i++)
53 #define for_each_rsnd_clkout(pos, adg, i) \
54 for (i = 0; \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
57 i++)
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
59
60 static const char * const clkin_name_gen4[] = {
61 [CLKA] = "clkin",
62 };
63
64 static const char * const clkin_name_gen2[] = {
65 [CLKA] = "clk_a",
66 [CLKB] = "clk_b",
67 [CLKC] = "clk_c",
68 [CLKI] = "clk_i",
69 };
70
71 static const char * const clkout_name_gen2[] = {
72 [CLKOUT] = "audio_clkout",
73 [CLKOUT1] = "audio_clkout1",
74 [CLKOUT2] = "audio_clkout2",
75 [CLKOUT3] = "audio_clkout3",
76 };
77
rsnd_adg_calculate_brgx(unsigned long div)78 static u32 rsnd_adg_calculate_brgx(unsigned long div)
79 {
80 int i;
81
82 if (!div)
83 return 0;
84
85 for (i = 3; i >= 0; i--) {
86 int ratio = 2 << (i * 2);
87 if (0 == (div % ratio))
88 return (u32)((i << 8) | ((div / ratio) - 1));
89 }
90
91 return ~0;
92 }
93
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream * io)94 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
95 {
96 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
97 int id = rsnd_mod_id(ssi_mod);
98 int ws = id;
99
100 if (rsnd_ssi_is_pin_sharing(io)) {
101 switch (id) {
102 case 1:
103 case 2:
104 case 9:
105 ws = 0;
106 break;
107 case 4:
108 ws = 3;
109 break;
110 case 8:
111 ws = 7;
112 break;
113 }
114 }
115
116 return (0x6 + ws) << 8;
117 }
118
__rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int target_rate,unsigned int * target_val,unsigned int * target_en)119 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
120 struct rsnd_dai_stream *io,
121 unsigned int target_rate,
122 unsigned int *target_val,
123 unsigned int *target_en)
124 {
125 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
126 struct device *dev = rsnd_priv_to_dev(priv);
127 int sel;
128 unsigned int val, en;
129 unsigned int min, diff;
130 unsigned int sel_rate[] = {
131 adg->clkin_rate[CLKA], /* 0000: CLKA */
132 adg->clkin_rate[CLKB], /* 0001: CLKB */
133 adg->clkin_rate[CLKC], /* 0010: CLKC */
134 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */
135 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */
136 };
137
138 min = ~0;
139 val = 0;
140 en = 0;
141 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
142 int idx = 0;
143 int step = 2;
144 int div;
145
146 if (!sel_rate[sel])
147 continue;
148
149 for (div = 2; div <= 98304; div += step) {
150 diff = abs(target_rate - sel_rate[sel] / div);
151 if (min > diff) {
152 val = (sel << 8) | idx;
153 min = diff;
154 en = 1 << (sel + 1); /* fixme */
155 }
156
157 /*
158 * step of 0_0000 / 0_0001 / 0_1101
159 * are out of order
160 */
161 if ((idx > 2) && (idx % 2))
162 step *= 2;
163 if (idx == 0x1c) {
164 div += step;
165 step *= 2;
166 }
167 idx++;
168 }
169 }
170
171 if (min == ~0) {
172 dev_err(dev, "no Input clock\n");
173 return;
174 }
175
176 *target_val = val;
177 if (target_en)
178 *target_en = en;
179 }
180
rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate,u32 * in,u32 * out,u32 * en)181 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
182 struct rsnd_dai_stream *io,
183 unsigned int in_rate,
184 unsigned int out_rate,
185 u32 *in, u32 *out, u32 *en)
186 {
187 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
188 unsigned int target_rate;
189 u32 *target_val;
190 u32 _in;
191 u32 _out;
192 u32 _en;
193
194 /* default = SSI WS */
195 _in =
196 _out = rsnd_adg_ssi_ws_timing_gen2(io);
197
198 target_rate = 0;
199 target_val = NULL;
200 _en = 0;
201 if (runtime->rate != in_rate) {
202 target_rate = out_rate;
203 target_val = &_out;
204 } else if (runtime->rate != out_rate) {
205 target_rate = in_rate;
206 target_val = &_in;
207 }
208
209 if (target_rate)
210 __rsnd_adg_get_timesel_ratio(priv, io,
211 target_rate,
212 target_val, &_en);
213
214 if (in)
215 *in = _in;
216 if (out)
217 *out = _out;
218 if (en)
219 *en = _en;
220 }
221
rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod * cmd_mod,struct rsnd_dai_stream * io)222 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
223 struct rsnd_dai_stream *io)
224 {
225 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
226 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
227 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
228 int id = rsnd_mod_id(cmd_mod);
229 int shift = (id % 2) ? 16 : 0;
230 u32 mask, val;
231
232 rsnd_adg_get_timesel_ratio(priv, io,
233 rsnd_src_get_in_rate(priv, io),
234 rsnd_src_get_out_rate(priv, io),
235 NULL, &val, NULL);
236
237 val = val << shift;
238 mask = 0x0f1f << shift;
239
240 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
241
242 return 0;
243 }
244
rsnd_adg_set_src_timesel_gen2(struct rsnd_mod * src_mod,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate)245 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
246 struct rsnd_dai_stream *io,
247 unsigned int in_rate,
248 unsigned int out_rate)
249 {
250 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
251 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
252 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
253 u32 in, out;
254 u32 mask, en;
255 int id = rsnd_mod_id(src_mod);
256 int shift = (id % 2) ? 16 : 0;
257
258 rsnd_mod_confirm_src(src_mod);
259
260 rsnd_adg_get_timesel_ratio(priv, io,
261 in_rate, out_rate,
262 &in, &out, &en);
263
264 in = in << shift;
265 out = out << shift;
266 mask = 0x0f1f << shift;
267
268 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
269 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
270
271 if (en)
272 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
273
274 return 0;
275 }
276
rsnd_adg_set_ssi_clk(struct rsnd_mod * ssi_mod,u32 val)277 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
278 {
279 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
280 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
281 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
282 struct device *dev = rsnd_priv_to_dev(priv);
283 int id = rsnd_mod_id(ssi_mod);
284 int shift = (id % 4) * 8;
285 u32 mask = 0xFF << shift;
286
287 rsnd_mod_confirm_ssi(ssi_mod);
288
289 val = val << shift;
290
291 /*
292 * SSI 8 is not connected to ADG.
293 * it works with SSI 7
294 */
295 if (id == 8)
296 return;
297
298 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
299
300 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
301 }
302
rsnd_adg_clk_query(struct rsnd_priv * priv,unsigned int rate)303 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
304 {
305 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
306 struct clk *clk;
307 int i;
308 int sel_table[] = {
309 [CLKA] = 0x1,
310 [CLKB] = 0x2,
311 [CLKC] = 0x3,
312 [CLKI] = 0x0,
313 };
314
315 /*
316 * find suitable clock from
317 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
318 */
319 for_each_rsnd_clkin(clk, adg, i)
320 if (rate == adg->clkin_rate[i])
321 return sel_table[i];
322
323 /*
324 * find divided clock from BRGA/BRGB
325 */
326 if (rate == adg->brg_rate[ADG_HZ_441])
327 return 0x10;
328
329 if (rate == adg->brg_rate[ADG_HZ_48])
330 return 0x20;
331
332 return -EIO;
333 }
334
rsnd_adg_ssi_clk_stop(struct rsnd_mod * ssi_mod)335 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
336 {
337 rsnd_adg_set_ssi_clk(ssi_mod, 0);
338
339 return 0;
340 }
341
rsnd_adg_ssi_clk_try_start(struct rsnd_mod * ssi_mod,unsigned int rate)342 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
343 {
344 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
345 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
346 struct device *dev = rsnd_priv_to_dev(priv);
347 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
348 int data;
349 u32 ckr = 0;
350
351 data = rsnd_adg_clk_query(priv, rate);
352 if (data < 0)
353 return data;
354
355 rsnd_adg_set_ssi_clk(ssi_mod, data);
356
357 if (0 == (rate % 8000))
358 ckr = 0x80000000; /* BRGB output = 48kHz */
359
360 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
361
362 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
363 (ckr) ? 'B' : 'A',
364 (ckr) ? adg->brg_rate[ADG_HZ_48] :
365 adg->brg_rate[ADG_HZ_441]);
366
367 return 0;
368 }
369
rsnd_adg_clk_control(struct rsnd_priv * priv,int enable)370 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
371 {
372 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
373 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
374 struct clk *clk;
375 int i;
376
377 if (enable) {
378 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);
379 rsnd_mod_write(adg_mod, BRRA, adg->brga);
380 rsnd_mod_write(adg_mod, BRRB, adg->brgb);
381 }
382
383 for_each_rsnd_clkin(clk, adg, i) {
384 if (enable) {
385 clk_prepare_enable(clk);
386
387 /*
388 * We shouldn't use clk_get_rate() under
389 * atomic context. Let's keep it when
390 * rsnd_adg_clk_enable() was called
391 */
392 adg->clkin_rate[i] = clk_get_rate(clk);
393 } else {
394 clk_disable_unprepare(clk);
395 }
396 }
397 }
398
rsnd_adg_create_null_clk(struct rsnd_priv * priv,const char * const name,const char * parent)399 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
400 const char * const name,
401 const char *parent)
402 {
403 struct device *dev = rsnd_priv_to_dev(priv);
404 struct clk *clk;
405
406 clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
407 if (IS_ERR_OR_NULL(clk)) {
408 dev_err(dev, "create null clk error\n");
409 return ERR_CAST(clk);
410 }
411
412 return clk;
413 }
414
rsnd_adg_null_clk_get(struct rsnd_priv * priv)415 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
416 {
417 struct rsnd_adg *adg = priv->adg;
418
419 if (!adg->null_clk) {
420 static const char * const name = "rsnd_adg_null";
421
422 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
423 }
424
425 return adg->null_clk;
426 }
427
rsnd_adg_null_clk_clean(struct rsnd_priv * priv)428 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
429 {
430 struct rsnd_adg *adg = priv->adg;
431
432 if (adg->null_clk)
433 clk_unregister_fixed_rate(adg->null_clk);
434 }
435
rsnd_adg_get_clkin(struct rsnd_priv * priv)436 static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
437 {
438 struct rsnd_adg *adg = priv->adg;
439 struct device *dev = rsnd_priv_to_dev(priv);
440 struct clk *clk;
441 const char * const *clkin_name;
442 int clkin_size;
443 int i;
444
445 clkin_name = clkin_name_gen2;
446 clkin_size = ARRAY_SIZE(clkin_name_gen2);
447 if (rsnd_is_gen4(priv)) {
448 clkin_name = clkin_name_gen4;
449 clkin_size = ARRAY_SIZE(clkin_name_gen4);
450 }
451
452 for (i = 0; i < clkin_size; i++) {
453 clk = devm_clk_get(dev, clkin_name[i]);
454
455 if (IS_ERR_OR_NULL(clk))
456 clk = rsnd_adg_null_clk_get(priv);
457 if (IS_ERR_OR_NULL(clk))
458 goto err;
459
460 adg->clkin[i] = clk;
461 }
462
463 adg->clkin_size = clkin_size;
464
465 return 0;
466
467 err:
468 dev_err(dev, "adg clock IN get failed\n");
469
470 rsnd_adg_null_clk_clean(priv);
471
472 return -EIO;
473 }
474
rsnd_adg_unregister_clkout(struct rsnd_priv * priv)475 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
476 {
477 struct rsnd_adg *adg = priv->adg;
478 struct clk *clk;
479 int i;
480
481 for_each_rsnd_clkout(clk, adg, i)
482 clk_unregister_fixed_rate(clk);
483 }
484
rsnd_adg_get_clkout(struct rsnd_priv * priv)485 static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
486 {
487 struct rsnd_adg *adg = priv->adg;
488 struct clk *clk;
489 struct device *dev = rsnd_priv_to_dev(priv);
490 struct device_node *np = dev->of_node;
491 struct property *prop;
492 u32 ckr, brgx, brga, brgb;
493 u32 req_rate[ADG_HZ_SIZE] = {};
494 uint32_t count = 0;
495 unsigned long req_Hz[ADG_HZ_SIZE];
496 int clkout_size;
497 int i, req_size;
498 int approximate = 0;
499 const char *parent_clk_name = NULL;
500 const char * const *clkout_name;
501 int brg_table[] = {
502 [CLKA] = 0x0,
503 [CLKB] = 0x1,
504 [CLKC] = 0x4,
505 [CLKI] = 0x2,
506 };
507
508 ckr = 0;
509 brga = 0xff; /* default */
510 brgb = 0xff; /* default */
511
512 /*
513 * ADG supports BRRA/BRRB output only
514 * this means all clkout0/1/2/3 will be same rate
515 */
516 prop = of_find_property(np, "clock-frequency", NULL);
517 if (!prop)
518 goto rsnd_adg_get_clkout_end;
519
520 req_size = prop->length / sizeof(u32);
521 if (req_size > ADG_HZ_SIZE) {
522 dev_err(dev, "too many clock-frequency\n");
523 return -EINVAL;
524 }
525
526 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
527 req_Hz[ADG_HZ_48] = 0;
528 req_Hz[ADG_HZ_441] = 0;
529 for (i = 0; i < req_size; i++) {
530 if (0 == (req_rate[i] % 44100))
531 req_Hz[ADG_HZ_441] = req_rate[i];
532 if (0 == (req_rate[i] % 48000))
533 req_Hz[ADG_HZ_48] = req_rate[i];
534 }
535
536 /*
537 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
538 * have 44.1kHz or 48kHz base clocks for now.
539 *
540 * SSI itself can divide parent clock by 1/1 - 1/16
541 * see
542 * rsnd_adg_ssi_clk_try_start()
543 * rsnd_ssi_master_clk_start()
544 */
545
546 /*
547 * [APPROXIMATE]
548 *
549 * clk_i (internal clock) can't create accurate rate, it will be approximate rate.
550 *
551 * <Note>
552 *
553 * clk_i needs x2 of required maximum rate.
554 * see
555 * - Minimum division of BRRA/BRRB
556 * - rsnd_ssi_clk_query()
557 *
558 * Sample Settings for TDM 8ch, 32bit width
559 *
560 * 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200
561 * 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000
562 *
563 * clock-frequency = <22579200 24576000>;
564 */
565 for_each_rsnd_clkin(clk, adg, i) {
566 u32 rate, div;
567
568 rate = clk_get_rate(clk);
569
570 if (0 == rate) /* not used */
571 continue;
572
573 /* BRGA */
574
575 if (i == CLKI)
576 /* see [APPROXIMATE] */
577 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];
578 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) {
579 div = rate / req_Hz[ADG_HZ_441];
580 brgx = rsnd_adg_calculate_brgx(div);
581 if (BRRx_MASK(brgx) == brgx) {
582 brga = brgx;
583 adg->brg_rate[ADG_HZ_441] = rate / div;
584 ckr |= brg_table[i] << 20;
585 if (req_Hz[ADG_HZ_441])
586 parent_clk_name = __clk_get_name(clk);
587 if (i == CLKI)
588 approximate = 1;
589 }
590 }
591
592 /* BRGB */
593
594 if (i == CLKI)
595 /* see [APPROXIMATE] */
596 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];
597 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) {
598 div = rate / req_Hz[ADG_HZ_48];
599 brgx = rsnd_adg_calculate_brgx(div);
600 if (BRRx_MASK(brgx) == brgx) {
601 brgb = brgx;
602 adg->brg_rate[ADG_HZ_48] = rate / div;
603 ckr |= brg_table[i] << 16;
604 if (req_Hz[ADG_HZ_48])
605 parent_clk_name = __clk_get_name(clk);
606 if (i == CLKI)
607 approximate = 1;
608 }
609 }
610 }
611
612 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) &&
613 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441]))
614 goto rsnd_adg_get_clkout_end;
615
616 if (approximate)
617 dev_info(dev, "It uses CLK_I as approximate rate");
618
619 clkout_name = clkout_name_gen2;
620 clkout_size = ARRAY_SIZE(clkout_name_gen2);
621 if (rsnd_is_gen4(priv))
622 clkout_size = 1; /* reuse clkout_name_gen2[] */
623
624 /*
625 * ADG supports BRRA/BRRB output only.
626 * this means all clkout0/1/2/3 will be * same rate
627 */
628
629 of_property_read_u32(np, "#clock-cells", &count);
630 /*
631 * for clkout
632 */
633 if (!count) {
634 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
635 parent_clk_name, 0, req_rate[0]);
636 if (IS_ERR_OR_NULL(clk))
637 goto err;
638
639 adg->clkout[CLKOUT] = clk;
640 adg->clkout_size = 1;
641 of_clk_add_provider(np, of_clk_src_simple_get, clk);
642 }
643 /*
644 * for clkout0/1/2/3
645 */
646 else {
647 for (i = 0; i < clkout_size; i++) {
648 clk = clk_register_fixed_rate(dev, clkout_name[i],
649 parent_clk_name, 0,
650 req_rate[0]);
651 if (IS_ERR_OR_NULL(clk))
652 goto err;
653
654 adg->clkout[i] = clk;
655 }
656 adg->onecell.clks = adg->clkout;
657 adg->onecell.clk_num = clkout_size;
658 adg->clkout_size = clkout_size;
659 of_clk_add_provider(np, of_clk_src_onecell_get,
660 &adg->onecell);
661 }
662
663 rsnd_adg_get_clkout_end:
664 adg->ckr = ckr;
665 adg->brga = brga;
666 adg->brgb = brgb;
667
668 return 0;
669
670 err:
671 dev_err(dev, "adg clock OUT get failed\n");
672
673 rsnd_adg_unregister_clkout(priv);
674
675 return -EIO;
676 }
677
678 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
679 __printf(3, 4)
dbg_msg(struct device * dev,struct seq_file * m,const char * fmt,...)680 static void dbg_msg(struct device *dev, struct seq_file *m,
681 const char *fmt, ...)
682 {
683 char msg[128];
684 va_list args;
685
686 va_start(args, fmt);
687 vsnprintf(msg, sizeof(msg), fmt, args);
688 va_end(args);
689
690 if (m)
691 seq_puts(m, msg);
692 else
693 dev_dbg(dev, "%s", msg);
694 }
695
rsnd_adg_clk_dbg_info(struct rsnd_priv * priv,struct seq_file * m)696 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
697 {
698 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
699 struct device *dev = rsnd_priv_to_dev(priv);
700 struct clk *clk;
701 int i;
702
703 for_each_rsnd_clkin(clk, adg, i)
704 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
705 __clk_get_name(clk), clk, clk_get_rate(clk));
706
707 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
708 adg->ckr, adg->brga, adg->brgb);
709 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);
710 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);
711
712 /*
713 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
714 * by BRGCKR::BRGCKR_31
715 */
716 for_each_rsnd_clkout(clk, adg, i)
717 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
718 __clk_get_name(clk), clk, clk_get_rate(clk));
719 }
720 #else
721 #define rsnd_adg_clk_dbg_info(priv, m)
722 #endif
723
rsnd_adg_probe(struct rsnd_priv * priv)724 int rsnd_adg_probe(struct rsnd_priv *priv)
725 {
726 struct rsnd_adg *adg;
727 struct device *dev = rsnd_priv_to_dev(priv);
728 int ret;
729
730 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
731 if (!adg)
732 return -ENOMEM;
733
734 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
735 NULL, 0, 0);
736 if (ret)
737 return ret;
738
739 priv->adg = adg;
740
741 ret = rsnd_adg_get_clkin(priv);
742 if (ret)
743 return ret;
744
745 ret = rsnd_adg_get_clkout(priv);
746 if (ret)
747 return ret;
748
749 rsnd_adg_clk_enable(priv);
750 rsnd_adg_clk_dbg_info(priv, NULL);
751
752 return 0;
753 }
754
rsnd_adg_remove(struct rsnd_priv * priv)755 void rsnd_adg_remove(struct rsnd_priv *priv)
756 {
757 struct device *dev = rsnd_priv_to_dev(priv);
758 struct device_node *np = dev->of_node;
759
760 rsnd_adg_unregister_clkout(priv);
761
762 of_clk_del_provider(np);
763
764 rsnd_adg_clk_disable(priv);
765
766 /* It should be called after rsnd_adg_clk_disable() */
767 rsnd_adg_null_clk_clean(priv);
768 }
769